KR100506876B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR100506876B1 KR100506876B1 KR10-2002-0065560A KR20020065560A KR100506876B1 KR 100506876 B1 KR100506876 B1 KR 100506876B1 KR 20020065560 A KR20020065560 A KR 20020065560A KR 100506876 B1 KR100506876 B1 KR 100506876B1
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- 239000004065 semiconductor Substances 0.000 title abstract description 21
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 56
- 238000000034 method Methods 0.000 claims abstract description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 239000000203 mixture Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 230000001052 transient effect Effects 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 abstract description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052799 carbon Inorganic materials 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 abstract 1
- 238000007689 inspection Methods 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 description 3
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- IUHFWCGCSVTMPG-UHFFFAOYSA-N [C].[C] Chemical compound [C].[C] IUHFWCGCSVTMPG-UHFFFAOYSA-N 0.000 description 1
- 150000001450 anions Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 반사방지막인 SiON막의 식각공정 시 적정 식각(just etch)공정 후 과도 식각(over etch)공정으로 갈수록 탄소(carbon)를 다량 함유하는 CF계 가스를 사용함으로써 폴리머를 다량 유발시켜 감광막패턴과 반사방지막 계면으로 식각 가스가 침투하는 것을 방지하여 FICD(Final Inspection Critical Dimension)의 변경 없이 반사방지막의 변형을 방지하고, 그로 인하여 패턴의 균일도를 향상시키고, 반도체소자의 고집적화를 가능하게 하며 반도체소자의 특성 및 수율을 향상시키는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, which uses a CF-based gas containing a large amount of carbon toward the over-etch process after a proper etching process during the etching process of the SiON film as an anti-reflection film This prevents the etching gas from penetrating into the interface between the photoresist pattern and the antireflection film by preventing a large amount of polymer, thereby preventing deformation of the antireflection film without changing the final inspection critical dimension (FICD), thereby improving the uniformity of the pattern, and thereby improving the semiconductor device. This technology enables high integration and improves the characteristics and yield of semiconductor devices.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게 감광막패턴과 반사방지막인 SiON막의 계면에 폴리머를 균일하게 형성하여 SiON막의 상부가 손실되거나(top loss), 줄무늬(striation)가 발생하는 것을 방지하는 반도체소자의 제조방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to form a polymer uniformly at the interface between the photoresist pattern and the anti-reflective SiON film, the top of the SiON film is lost (top loss) or streaks (striation) occurs It relates to a method for manufacturing a semiconductor device to prevent.
일반적으로 반도체 제조 공정 중의 리소그래피 공정은 노광마스크의 광차단막 패턴 밀도에 따라 이를 통과하는 빛의 회절 정도 및 근접 패턴을 통과한 빛과의 간섭 등에 의해 동일한 크기의 패턴에서도 실제 웨이퍼에 형성되는 패턴의 크기가 달라지는 현상이 발생한다.In general, the lithography process in the semiconductor manufacturing process is the size of the pattern formed on the actual wafer even in the same size pattern due to the diffraction degree of light passing through it and the interference with the light passing through the proximity pattern according to the light blocking film pattern density of the exposure mask. The phenomenon occurs.
상기와 같은 문제점을 개선하기 위하여 반사방지막을 사용하고 있으며, 상기 반사방지막은 증착 조건 등의 방법에 의하여 굴절율(refractive index)의 실수(n) 및 허수(k), 반사율(reflectance, R) 등과 같은 광학 상수값을 얻을 수 있는 실리콘 옥시나이트라이드(silicon oxynitride, SiOxNy) 막이 사용되고 있으며, 주로 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition, 이하 PE-CVD 라 함)방법으로 형성한다.In order to improve the above problems, an anti-reflection film is used, and the anti-reflection film has a real index (n), an imaginary number (k), and a reflectance (R) of the refractive index by a method such as deposition conditions. Silicon oxynitride (SiO x N y ) films which can obtain optical constant values are used, and are mainly formed by plasma enhanced chemical vapor deposition (hereinafter referred to as PE-CVD).
이하, 첨부된 도면을 참고로 하여 종래기술에 대하여 설명한다. Hereinafter, with reference to the accompanying drawings will be described in the prior art.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 제조방법에 의한 공정 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
먼저, 실리콘기판(11) 상부에 피식각층으로서 SiN막(13)을 형성한다. First, an SiN film 13 is formed on the silicon substrate 11 as an etching target layer.
다음, 상기 SiN막(13) 상부에 반사방지막인 SiON막(15)을 형성한다. Next, an SiON film 15 which is an antireflection film is formed on the SiN film 13.
그 다음, 상기 SiON막(15) 상부에 패턴으로 예정되는 부분을 보호하는 감광막패턴(17)을 형성한다. (도 1a 참조)Next, a photosensitive film pattern 17 is formed on the SiON film 15 to protect a portion intended as a pattern. (See Figure 1A)
다음, 상기 감광막패턴(17)을 식각마스크로 사용하여 상기 SiON막(15)을 식각하여 SiON막 패턴(16)을 형성한다. 이때, 상기 식각공정은 CF4, CHF3 및 O2 혼합가스를 이용한 건식식각공정으로 실시한다.Next, the SiON film 15 is etched using the photoresist pattern 17 as an etching mask to form a SiON film pattern 16. At this time, the etching process is performed by a dry etching process using a mixture of CF 4 , CHF 3 and O 2 .
그 후, 상기 감광막패턴(17) 및 SiON막 패턴(16)을 식각마스크로 상기 SiN막(15)을 식각한다. (도 1b 참조)Thereafter, the SiN film 15 is etched using the photoresist pattern 17 and the SiON film pattern 16 as an etching mask. (See FIG. 1B)
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 반도체소자가 고집적화되어 감에 따라 종횡비가 증가하여 피식각층의 증착 두께가 증가하고, 상기 피식각층의 하드마스크로서 반사방지막인 SiON막을 두껍게 증착하였으나, 반사방지막의 두께가 증가하면서 식각 시간이 증가하고, 식각가스인 CF4, CHF3 및 O2 혼합가스는 폴리머의 형성이 부족하여 상기 반사방지막과 감광막패턴의 계면 "A" 부분으로 식각 가스가 침투하여 도 2 와 같이 라인/스페이스 패턴의 재현성이 저하되는 현상이 발생하였다.As described above, in the method of manufacturing a semiconductor device according to the related art, as the semiconductor device becomes highly integrated, the aspect ratio increases and the deposition thickness of the etched layer increases, and as the hard mask of the etched layer, the SiON film, which is an anti-reflection film, is deposited thickly. , The etching time increases as the thickness of the anti-reflection film increases, and the etching gas CF 4 , CHF 3 and O 2 mixed gas lacks the formation of a polymer, so that the etching gas enters the "A" portion of the anti-reflection film and the photoresist pattern Penetration caused a decrease in the reproducibility of the line / space pattern as shown in FIG. 2.
한편, 피식각층인 SiN막의 식각가스에 CH2F2 가스를 도입하여 감광막의 식각선택비는 증가시켰지만 반사방지막의 측벽에 줄무늬가 발생하고, 폴리머를 다량 유발시키는 CF 비율이 큰 가스를 식각가스로 이용하였으나 FICD를 조절하기 어려운 문제점이 있다.On the other hand, the etching selectivity of the photoresist film was increased by introducing CH 2 F 2 gas into the etching gas of the SiN film, which is the etching layer, but streaks occurred on the sidewalls of the anti-reflection film, and the gas having a large CF ratio that caused a large amount of polymer was used as the etching gas. Although it is used, there is a problem that is difficult to control the FICD.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 반사방지막인 SiON막 식각 시 적정 식각공정 후 과도 식각공정으로 갈수록 탄소(carbon)을 다량 함유하는 CF계 가스를 사용함으로써 폴리머를 다량 유발시켜 감광막패턴과 반사방지막 계면으로 식각 가스의 침투를 방지하여 FICD의 변경 없이 반사방지막의 변형을 방지할 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다. The present invention, in order to solve the above problems of the prior art, by using a CF-based gas containing a large amount of carbon (carbon) as the excessive etching step after the proper etching process during the etching of the anti-reflective SiON film as a photosensitive film It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing the deformation of the antireflection film without changing the FICD by preventing the penetration of the etching gas into the pattern and the antireflection film interface.
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은, Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
실리콘기판 상부에 SiN막을 형성하는 공정과,Forming a SiN film on the silicon substrate;
상기 SiN막 상부에 반사방지막인 SiON막을 형성하는 공정과,Forming a SiON film as an antireflection film on the SiN film;
상기 SiON막 상부에 패턴으로 예정되는 부분을 정의하는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the SiON film, the portion defining a predetermined pattern;
상기 감광막패턴을 식각마스크로 상기 SiON막을 식각하여 SiON막패턴을 형성하되, C2F6, CHF3 및 O2 혼합가스를 이용한 적정 식각공정과 상기 C2F6 가스보다 CF의 비율이 큰 C4F6, CHF3 및 O2 혼합가스를 이용한 과도 식각공정으로 진행하는 공정과,The SiON film is etched by using the photoresist pattern as an etch mask to form a SiON film pattern, and a proper etching process using a C 2 F 6 , CHF 3 and O 2 mixed gas and a larger C ratio than the C 2 F 6 gas. 4 F 6 , CHF 3 and the process proceeds to the transient etching process using a mixture of O 2 ,
상기 감광막패턴 및 SiON막 패턴을 식각마스크로 상기 SiN막을 식각하는 공정과,Etching the SiN film by using the photoresist pattern and the SiON film pattern as an etching mask;
상기 식각 가스는 C2F6, C4F6, C5F8 등의 CF계 가스를 포함하는 것과,The etching gas includes a CF-based gas such as C 2 F 6 , C 4 F 6 , C 5 F 8 ,
상기 식각 가스는 상기 CF계 가스와 CHF3 및 O2 가스의 혼합가스인 것과,The etching gas is a mixture of the CF-based gas and CHF 3 and O 2 gas,
상기 SiON막 식각 공정은 C2F6, CHF3 및 O2 혼합가스를 이용한 적정 식각공정과 C4F6, CHF3 및 O2 혼합가스를 이용한 과도 식각공정으로 진행되는 것과,As it is the SiON film advances etching process as C 2 F 6, appropriate etching process and C 4 F 6, CHF 3 and O 2 excess etching process using a gas mixture using a CHF 3 and O 2 mixture gas,
삭제delete
상기 SiON막 식각공정은 SO2와 He 혼합가스로 상기 감광막패턴의 측벽을 소정 두께 제거한 후 실시되는 것을 포함하는 것을 특징으로 한다.The SiON film etching process may be performed after removing a predetermined thickness of the sidewall of the photoresist pattern with a mixture of SO 2 and He.
이하, 첨부된 도면을 참고로 하여 본 발명을 설명한다. Hereinafter, the present invention will be described with reference to the accompanying drawings.
도 3a 및 도 3b 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도이고, 도 4 는 본 발명에 따른 반도체소자의 제조방법에 의해 형성된 소자의 라인/스페이스 패턴을 나타낸 사진이다. 3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention, and FIG. 4 is a photograph showing a line / space pattern of a device formed by the method of manufacturing a semiconductor device according to the present invention.
먼저, 실리콘기판(31) 상부에 피식각층으로서 SiN막(33)을 형성한다. First, a SiN film 33 is formed on the silicon substrate 31 as an etched layer.
다음, 상기 SiN막(33) 상부에 반사방지막인 SiON막(35)을 형성한다. Next, an SiON film 35 as an antireflection film is formed on the SiN film 33.
그 다음, 상기 SiON막(35) 상부에 패턴으로 예정되는 부분을 보호하는 감광막패턴(37)을 형성한다. (도 3a 참조)Next, a photosensitive film pattern 37 is formed on the SiON film 35 to protect a portion scheduled as a pattern. (See Figure 3A)
다음, 상기 감광막패턴(37)을 식각마스크로 사용하여 상기 SiON막(35)을 식각하여 SiON막 패턴(36)을 형성한다. 이때, 상기 식각공정은 적정 식각공정 및 과도식각공정으로 실시되며, 상기 과도식각공정 시 상기 적정 식각공정 시보다 탄소를 다량 함유하는 CF계 가스를 포함하는 혼합가스를 사용한다. Next, the SiON film 35 is etched using the photoresist pattern 37 as an etching mask to form a SiON film pattern 36. In this case, the etching process is performed by a proper etching process and a transient etching process, a mixed gas containing a CF-based gas containing a greater amount of carbon than during the proper etching process during the transient etching process.
상기 CF계 가스는 C2F6, C4F6 또는 C5F8 가 사용되고, 식각 가스는 상기 CF계 가스와 CHF3 및 O2 가스의 혼합가스가 사용된다.The CF gas is C 2 F 6 , C 4 F 6 or C 5 F 8 is used, the etching gas is a mixture of the CF gas and CHF 3 and O 2 gas is used.
도 4 는 상기 SiON막(35)을 C2F6, CHF3 및 O2 혼합가스를 이용한 적정 식각공정을 실시하는 경우 C4F6, CHF3 및 O2 혼합가스를 이용한 과도 식각공정을 진행한 후 라인/스페이스 패턴을 나타내는 사진이다.Figure 4 proceeds the excessive etching process using a C 4 F 6, CHF 3 and O 2 mixed gas when carrying out appropriate etching process using the SiON film 35, the C 2 F 6, CHF 3 and O 2 mixed gas This is a picture showing a line / space pattern.
상기 CF계 가스는 CF의 비율이 클수록 폴리머를 다량 유발시키기 때문에 적정 식각공정에서 과도 식각공정으로 갈수록 패턴의 프로파일(profile)은 경사지게 형성된다.Since the CF-based gas induces a large amount of polymer as the ratio of CF increases, the profile of the pattern is inclined gradually from the proper etching process to the excessive etching process.
상기 식각 공정 중 식각 가스 내의 O2의 유량을 조절하여 상기 감광막패턴(37) 및 SiON막 패턴(36)의 상부 및 측벽에 증착되는 폴리머의 양을 조절함으로써 식각 후 형성되는 패턴의 크기를 조절할 수 있다.By controlling the flow rate of O 2 in the etching gas during the etching process, the size of the pattern formed after etching may be controlled by controlling the amount of polymer deposited on the top and sidewalls of the photoresist pattern 37 and the SiON layer pattern 36. have.
여기서, 상기 식각공정은 RIE(Reactive Ion Etching)형 장비에서 ICP(Inductively Coupled Plasma)형 장비까지 플라즈마(plasma)를 사용하는 모든 장비를 이용하여 실시할 수 있다. 특히, 상기 ICP 타입으로 식각 공정을 진행하는 경우 아웃 페이즈(out phase) 펄스 변조(pulse modulation)를 실시하면 폴리머를 형성하면서 감광막패턴(37) 측벽의 거칠기(roughness)를 완만하게 하는 작용이 있어 줄무늬가 형성되는 현상을 개선할 수 있다. 또한, 소오스 파워에 펄스 변조를 실시하면 소오스 파워가 인가되지 않은 경우 전자 냉각(electron cooling) 효과로 음이온 형성을 유발하여 패턴 표면의 전자 충전(electron charge)에 의해 감광막패턴(37) 측벽의 식각을 최소화시킬 수 있다. Here, the etching process may be performed by using all the equipment using plasma from RIE (Reactive Ion Etching) equipment to ICP (Inductively Coupled Plasma) equipment. In particular, when the etching process is performed in the ICP type, when out phase pulse modulation is performed, the polymer is formed to smooth the roughness of the sidewalls of the photoresist pattern 37. It is possible to improve the phenomenon that is formed. In addition, when pulse modulation is applied to the source power, an anion is formed by an electron cooling effect when the source power is not applied, thereby etching the sidewalls of the photoresist pattern 37 by electron charge on the pattern surface. It can be minimized.
한편, 상기 SiON막(35)을 식각하기 전에 SO2 및 He 가스를 이용하여 소정 두께 제거하면 감광막패턴(37)의 측벽 쪽의 거칠기 현상이나 스컴(scum) 성분을 제거하여 줄무늬 현상 방지 및 패턴 크기 조절을 용이하게 할 수도 있다.On the other hand, if the predetermined thickness is removed by using SO 2 and He gas before etching the SiON film 35, roughness or scum components on the side wall of the photosensitive film pattern 37 are removed to prevent streaking and pattern size. It may be easy to adjust.
그 후, 상기 감광막패턴(37) 및 SiON막 패턴(36)을 식각마스크로 상기 SiN막(35)을 식각한다. (도 3b 참조)Thereafter, the SiN film 35 is etched using the photoresist pattern 37 and the SiON film pattern 36 as an etching mask. (See Figure 3b)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 반사방지막인 SiON막의 식각공정 시 적정 식각공정 후 과도 식각공정으로 갈수록 탄소를 다량 함유하는 CF계 가스를 사용함으로써 폴리머를 다량 유발시켜 감광막패턴과 반사방지막 계면으로 식각 가스의 침투를 방지하여 FICD의 변경 없이 반사방지막의 변형을 방지하고, 그로 인하여 패턴의 균일도를 향상시킬 수 있고, 반도체소자의 고집적화를 가능하게 하며 반도체소자의 특성 및 수율을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, during the etching process of the SiON film, which is an antireflection film, the photoresist film is caused by inducing a large amount of polymer by using CF gas containing a large amount of carbon in the transient etching process after the proper etching process. By preventing the penetration of etching gas through the interface between the pattern and the anti-reflection film, it is possible to prevent the deformation of the anti-reflection film without changing the FICD, thereby improving the pattern uniformity, enabling the high integration of the semiconductor device, and the characteristics and yield of the semiconductor device. There is an advantage to improve.
도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 제조방법에 의한 공정 단면도. 1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
도 2 는 종래기술에 따른 반도체소자의 제조방법에 의해 형성된 소자의 라인/스페이스 패턴을 나타낸 사진. Figure 2 is a photograph showing a line / space pattern of the device formed by the method of manufacturing a semiconductor device according to the prior art.
도 3a 및 도 3b 는 본 발명에 따른 반도체소자의 제조방법에 의한 공정 단면도. 3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 4 는 본 발명에 따른 반도체소자의 제조방법에 의해 형성된 소자의 라인/스페이스 패턴을 나타낸 사진. Figure 4 is a photograph showing a line / space pattern of the device formed by the method of manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11, 31 : 실리콘기판 13, 33 : SiN막11, 31: silicon substrate 13, 33: SiN film
15, 35 : SiON막 16, 36 : SiON막 패턴15, 35: SiON film 16, 36: SiON film pattern
17, 37 : 감광막패턴17, 37: photosensitive film pattern
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| JPH0766176A (en) * | 1993-08-25 | 1995-03-10 | Sony Corp | Dry etching method |
| KR970052397A (en) * | 1995-12-27 | 1997-07-29 | 김광호 | Manufacturing Method of Semiconductor Device |
| JPH10312993A (en) * | 1997-05-12 | 1998-11-24 | Sony Corp | Plasma-etching method of organic antireflection film |
| US6214747B1 (en) * | 1999-10-28 | 2001-04-10 | United Microelectronics Corp. | Method for forming opening in a semiconductor device |
| KR20010046749A (en) * | 1999-11-15 | 2001-06-15 | 박종섭 | Method for fabricating node contact in semiconductor device |
| KR20020013708A (en) * | 2000-08-12 | 2002-02-21 | 김승준 | Shallow Trench Forming Method for Semiconductor Isolation |
| KR20030016461A (en) * | 2001-08-16 | 2003-03-03 | 동부전자 주식회사 | Method for providing shallow trench isolation |
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| JPH0766176A (en) * | 1993-08-25 | 1995-03-10 | Sony Corp | Dry etching method |
| KR970052397A (en) * | 1995-12-27 | 1997-07-29 | 김광호 | Manufacturing Method of Semiconductor Device |
| JPH10312993A (en) * | 1997-05-12 | 1998-11-24 | Sony Corp | Plasma-etching method of organic antireflection film |
| US6214747B1 (en) * | 1999-10-28 | 2001-04-10 | United Microelectronics Corp. | Method for forming opening in a semiconductor device |
| KR20010046749A (en) * | 1999-11-15 | 2001-06-15 | 박종섭 | Method for fabricating node contact in semiconductor device |
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