KR100499878B1 - An error correction circuit for pid in dvd ram - Google Patents

Abstract

An error correction unit for PID in a DVD RAM is disclosed. According to the present invention, an input signal R (X) including initial PID information C (X) and error information E (X) consisting of PID data of a predetermined byte, IED data of a predetermined byte is received, and R (X). Syndrome generator for generating a syndrome (Syndrome) S ₀ and S ₁ substituted with the root of the generator Polinomial; Input the syndromes S ₀ and S ₁ to obtain an error position i (i = 0 to n-1 n: the number of symbols constituting a code word) satisfying the equation, S ₁ = S ₀ * α ⁱ An error position determining unit for detecting; And an error correction unit configured to generate an error-corrected result value RC _i by performing XOR logic on the received information r _i and the syndrome S ₀ corresponding to the detected error location i value. The output of the flag to be determined and the correction result can be processed in one code word section, so that the correction time can be shortened to 1/3 or less.

Description

An error correction circuit for PID in DVD RAM {AN ERROR CORRECTION CIRCUIT FOR PID IN DVD RAM}

The present invention relates to error correction, and more particularly, in a DVD RAM for reducing an error operation detection and error correction time of a PID signal of a DVD RAM by a RS (Reed Solomon) code. It relates to an error correction unit and a method for the ID of.

In general, the DVD RAM is configured such that data can be recorded and reproduced at a DVD recording density, compared to a DVD dedicated to reproduction. A disc for DVD RAM is made of a recordable material. Even a blank disc is recorded in accordance with a prescribed track when recording information. To this end, the DVD RAM disc contains information about tracks in advance when a disc is produced for tracking servo when recording information.

Among the stored information, there is a PID signal in which sector information of the DVD RAM and the number of sectors are recorded. The total information consists of 4 bytes and 32 symbols. Important information necessary for tracking servo is recorded, and Reed-Solomon code for error correction is added to protect this information.

Such error correction is generally performed in three stages. The first stage consists of Syndrome calculation, the second stage of error value and error position calculation, and the third stage of error correction / flag processing. This step is processed in units of one block, and one block means one code word and is processed in units of word cycles. A word cycle means a section in which one clock word is input by one clock per symbol and is equal to the number of clocks corresponding to the number of symbols included in one code word. Therefore, it usually takes two word cycles to perform the above three steps.

As shown in FIG. 1, in the first section, the calculation for Syndrome is performed at the same time as the nth received information is input, and thereafter, the received information (R (X)) and R (X) from Syndrome for it are mixed. Find the position and error value for an error. However, this process is very complicated and has a large amount of operation. Instead of directly calculating the error value and the position of the error, it forms the LFSR required in the middle of the operation. After the LFSR is constructed, the error value and the error position are obtained from this. The operation required to configure such an LFSR is performed in a section from one code word to another code word.

In the second section, error correction is performed to remove the error at the location by calculating the location and error value from the LFSR and Syndrome obtained in the previous section. In the third section, the error correction process is terminated by outputting the corrected result in serial.

Therefore, in order to correct the error, a total of three code word sections are required, and a pause for configuring the LFSR must be secured. This is directly connected with the error correction time, so that the time required for error correction takes three sections based on the Code Word section, which causes a problem in that the correction time is prolonged. In addition, there is a problem that an increase in the circuit amount due to the duplication of a circuit due to the parallelization of the three-capacity process and the implementation of a complex theory is inevitable.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide error correction for PID in a DVD RAM to quickly and without error and correction of PID information using a Reed Solomon code. In providing government.

According to an aspect of the present invention for achieving the above object, the error correction unit for the ID in the DVD RAM, in the implementation of the error correction unit for the PID (PID) in the DVD RAM, a predetermined byte (Byte) ), The input signal R (X) including the initial PID information C (X) and error information E (X) consisting of PID data of a predetermined byte, and IED data of a predetermined byte is inputted, and substituted the root of the generator polinomial of the R (X). A syndrome generator for generating a syndrome S ₀ and S ₁ ; Input the syndromes S ₀ and S ₁ to obtain an error position i (i = 0 to n-1 n: the number of symbols constituting a code word) satisfying the equation, S ₁ = S ₀ * α ⁱ An error position determining unit for detecting; And an error correction unit configured to generate an error corrected result value RC _i by performing XOR logic on the received information r _i and the syndrome S ₀ corresponding to the detected error location i value.

In addition, assuming that RC _i generated by the error correcting unit is an input signal R (X) ', generating syndromes S ₀ and S ₁ substituting the root of the generator polinomial of R (X)', And an error flag generator for outputting a corresponding result as a flag value by performing mutual OR logic on the information of S ₀ and S ₁ .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. First, as an embodiment of the present invention, the PID related information includes 4 bytes of PID data and 2 bytes of parity data. That is, as shown in Table 1

PID 4Byte IED 2Byte C5 C4 C3 C2 C1 C0

One code word contains six symbols. Therefore, the code words are expressed in 5th order according to the polynomial definition of Reed Solomon. The polynomial C (X) is as follows.

C (X) = C ₅ X ⁵ + C ₄ X ⁴ + C ₃ X ³ + C ₂ X ² + C ₁ X ¹ + C ₀ X ⁰ --------- Equation 1

The polynomial C (X) represented by Equation 1 includes 4 bytes of PID and 2 bytes of IED, from which C (X) corresponds to PID data (D (X)) and parity data (P (X)). Can be expressed. In this case, D (X) is applied from the second order polynomial, and C (X) is as follows.

C (X) = D (X) * X ² + P (X) --------------- Equation 2

Meanwhile, Equation 2 is expressed as a code word generation polynomial of Reed Solomon.

C (X) = Q (X) * G (X) ------------------- Equation 3

Becomes In addition, if only the PID data used in Equation 2, that is, D (X) is expressed in a four-dimensional polynomial,

D (X) = d ₃ X ³ + d ₂ X ² + d ₁ X ¹ + d ₀ X ⁰ --------- Equation 4

Same as If only IED data, i.e., P (X), which is parity data, is expressed in a two-dimensional polynomial

P (X) = P ₁ X ¹ + P ₀ X ⁰ -------------------- Equation 5

It is expressed as In this case, when an error occurs in the PID data and the IED data, the possibility of such error information for each symbol data will be described.

E (X) = e ₅ X ⁵ + e ₄ X ⁴ + e ₃ X ³ + e ₂ X ² + e ₁ X ¹ + e ₀ X ⁰ ---- Equation 6

Same as This is a six-dimensional polynomial that represents the likelihood of error in the PID data including the parity code. Therefore, the information R (X) to be received substantially consists of the above-mentioned error information E (X) and the code word C (X) which is unique information. In other words,

R (X) = C (X) + E (X) ------------------- Equation 7

And converting Equation 7 to Reed Solomon's polynomial,

R (X) = r ₅ X ⁵ + r ₄ X ⁴ + r ₃ X ³ + r ₂ X ² + r ₁ X ¹ + r ₀ X ⁰ --- Equation 8

Becomes In this case, when G (X) in Equation 3 is expressed by a code word generation polynomial of Reed Solomon,

G (X) = (X + α ¹ ) * (X + α ⁰ ) ---------- Equation 9

Reed Solomon's polynomial root. As shown in Equation 9, the roots are α ¹ and α ⁰ , which are according to Galois Field's rules, and because there are two Symbols of Generator Polinomina in PID of DVD-RAM, two symbols exist. to be. That is, α ¹ + α ¹ = 0, α ⁰ + α ⁰ = 0, and the root of G (X) becomes α ¹ and α ⁰ . The operation method is XOR operation.

Accordingly, the position of the error can be calculated by using Equation 7, and the error is found by substituting the root α ¹ or α ⁰ in Equation 7. If you substitute root α ¹ ,

R (α ¹ ) = 0 + E (α ¹ ) and when the root α ⁰ is substituted

R (α ⁰ ) = 0 + E (α ⁰ ). therefore,

R (α ⁰ ) = E (α ⁰ ) = S ₀ , and R (α ¹ ) = E (α ¹ ) = S ₁ . If the error occurred at the i th position, the error E (X) and the received data R (X)

E (X) = e _i X ⁱ --------------------- Equation 10

R (X) = C (X) + e _i X ⁱ -------------- Equation 11

Same as Substituting this root into S ₀ and S ₁ converts the received data R (X) as follows.

S ₀ = 0 + e _i (α ⁰ ) ⁱ = Σe ⁱ (i = 0 to 5)

S ₁ = 0 + e _i (α ¹ ) ⁱ = Σe _i α ⁱ

₁ S ₁ = ΣS ₀ * α ⁱ (i = 0 ~ 5) -------------------- Equation 12

Eventually, the position of the error will be any one of six symbol data. Looking at six roots corresponding to S ₁ according to Equation 12, S ₀ * α ⁰ , S ₀ * α ¹ , S ₀ * α ² , S ₀ * α ³ , S ₀ * α ⁴ , and S ₀ * α ⁵ . Therefore, any one of the six roots, such as S ₁ , becomes the position of the error. Equation 12 is to find the position of the error, and if implemented in hardware as shown in FIG.

FIG. 2 is an error position discrimination unit, which comprises a multiplier 201 capable of n symbol operations and a comparator 203 capable of comparing n symbols, and includes a result output stage 205. On the input side, previously calculated Syndrome information, that is, S ₀ and S ₁ information is input. Of course, it is input as n symbol.

S ₁ is input to one side of the comparator 203 to find S _{0 equal} to S ₁ according to Equation 12. S ₀ is input to one end of the multiplier 201, and the result value of the multiplier 201 is input to the other end of the comparator 203. Accordingly, the values of S ₀ * α ⁱ and S ₁ are input to the comparator 203 to determine whether the symbols are the same for each symbol. The result output stage 205 outputs only symbols such as S ₀ * α ⁱ and S _{1 at a} high level, and other result values are output at a low level. This is represented by l ₀ ~ l ₅ , and it is the position of the error value when any one of the symbols is switched to the high level. Fast error position determination is possible through the comparator 203 and the multiplier 201.

Meanwhile, referring to the generation of Syndrome, first, Syndrome, that is, S ₀ and S ₁ , as described in Equation 8, the received code R (X) is a PID signal C (X) and an error code E ( X), which is represented by Reed Solomon's polynomial r _i X ⁱ , and then converted to Syndrome.

That is, R (X) = r ₅ X ⁵ + r ₄ X ⁴ + r ₃ X ³ + r ₂ X ² + r ₁ X ¹ + r ₀ X ⁰

= Σr _i X ⁱ (i = 0 ~ 5)

to be. At this time, S ₀ and S ₁ which substituted α ⁰ and α ¹ of the generator polinomial into Syndrome, that is, R (X), are as follows.

S ₀ = Σr _i (i = 0 to 5) = r ₅ + r ₄ + r ₃ + r ₂ + r ₁ + r _0- (13)

S ₁ = Σr _i * α ⁱ (i = 0 ~ 5) ------------------------ Equation 14

= r ₅ * α ⁵ + r ₄ * α ⁴ + r ₃ * α ³ + r ₂ * α ² + r ₁ * α ¹ + r ₀ * α ⁰

Thus, Syndrome S ₀ above When S ₁ is implemented in hardware, as shown in FIG. 3, Reed Solomon is used as an input terminal of the first register 301, the second register 303, and the registers 301 and 303 to store the calculated information and to synchronize the mutual information. XOR gates 305 and 307 for the addition operation of are connected, and the result information through the multiplier 309 of Syndrome S ₁ is implemented to be fed back.

The XOR gates 305 and 307 are used to add the terms of Equations 13 and 14, and the multiplier 309 is used to multiply Equations 14. CLK is used for synchronous control of the registers 301 and 303 as a clock pulse signal.

Syndrome S ₀ is input / stored in the second register 303 as shown in Equation 13, and the stored result information is fed back to perform XOR logic with the information stored in the previous state. The performed result information is stored in the second register 303, and the currently stored result information performs the XOR gate and the information stored in the previous state through the XOR gate 307 again. Of course, since both the PID data and the parity data are set to six bytes, the second register 303 stores the accumulated information six times. The accumulated information stored six times becomes the Syndrome S ₀ .

On the other hand, Syndrome S ₁ stores a signal in which the root α ¹ of the received information R (X) is substituted in the first register 301 as shown in Equation 14, and stores the stored information value through the multiplier 309. Calculate α ⁱ . When the first input value r ₅ for the Syndrome S ₁ is input, it is stored in the first register 301, the r ₅ value is fed back and multiplied by a value of α ¹ through a multiplier 309.

XOR logic with the next input, r4, or addition. And stores the execution result value in the first register 301, and performs the multiplication by α ^1, the stored values, the multiplier 309 and performs the integration constant, the following input values and the XOR logic. Of course, α ⁱ is from 0 to 5 as defined in the embodiment of the present invention. The value obtained through this procedure becomes Syndrome S ₁ .

Next, a method for correcting error information by generating the Syndrome and determining an error position is as follows. First, the information (R (X)) received on the basis of (7) and equation (8) is represented as r _i, r _i, and it can be seen made of an transmitted codes c _i and the error signal e _i.

Therefore, if r _i = c _i + e _i , the code c _i first transmitted is obtained as follows.

r _i + e _i = c _i + e _i + e _i

I c _i = r _i + e _i = RC _i ---------------- (15)

Meanwhile, as inferred from Equation 12, e _i is S ₀ ,

Error Corrected Information RC _i = r _i + S ₀ Here, i is assumed that the error occurs at one position, i will be the error occurrence position, and if no error occurs, the error-corrected information RC _i becomes r _i . Therefore, if there is no error information to correct, RC _i = r _i + 0, and if there is error information to correct, RC _i = r _i + S ₀ . Of course, as described above, addition is done with XOR logic.

As shown in FIG. 4, the r _i and S ₀ perform XOR logic only on a symbol in which an error exists, and r _i and 0 (Zero) perform XOR logic in a symbol in which there is no error. To do. In the illustrated drawing, after selecting S ₀ or Zero based on error position information (l ₀ to l ₅ ) for determining whether an error exists in any one symbol, the R _i value and XOR logic are performed. It is.

In FIG. 4, the selectors sel0 to sle5 are provided to select an input terminal signal of the selectors sel0 to sle5 through the error position information l ₀ to l ₅ , and the input terminals of the selectors sel0 to sle5 are directed to one side. S ₀ is inputted to the other side, that is, zero, and includes XOR gates 401 to 411 to perform XOR logic to the output terminals of the selectors sel0 to sle5. The r _i value is input to the input sides of the XOR gates 401 to 411 so that the corresponding result value RC _i is output.

The error correcting unit receives the position information of the error from the error position determining unit and corrects the data r _i currently received by receiving the S ₀ value from the Syndrome generating circuit. For example, when an error occurs in l ₃ , the error position determining unit switches only l ₃ to a high level and maintains the remaining output at a low level.

Therefore, only the selector sel 3 selects only the "1" input terminal of the selector sel 3 in the selectors sel 0 to sel 5, and the remaining selectors sel 0 to sel 5, ≠ sel 3 are input terminals of "0". Select. This causes the rest of the selector (sel 0 ~ sel 5, ≠ sel 3) is the output value is "0", and the "0" input to each XOR gate (401,403,405,409,411), each received information r _i and a XOR logic Perform That is, the result information of the XOR gates 401, 403, 405, 409, 411 is r ₅ , r ₄ , r ₂ , r ₁ , r ₀ .

However, the output from the l ₃ to a high level, that is, when the l ₃ in the error position determination section is determined to be an error occurrence position, the l ₃ is controlled to be a "1" signal from the input terminal of the selector (sel 3) flows as Accordingly, Ev, S ₀ , which is connected to the "1" input terminal, is input. The S ₀ value is input to the XOR gate 407, and at the same time the r ₃ value is input so that the output of the XOR gate 407 becomes r ₃ + S ₀ . This results in error corrected information RC ₃ as described in the description of equation (15).

Meanwhile, in addition to the above-described one symbol error occurrence, a case where two or more symbol errors occur is described as follows. First of all, the error correction rule adopted in the PID of DVD-RAM stipulates to correct up to one error, and generates an error flag that cannot be corrected when two or more errors occur. Accordingly, the present invention is also designed to output a flag when two or more errors occur.

In detecting the error flag, that is, when two or more errors occur, first, since error corrected information RC _i is only one error corrected, if two or more errors exist, the error corrected information RC _i Syndrome S ₀ for will not become "Zero". S ₁ also doesn't become "Zero" of course. This is because when two or more errors occur, two or more roots are not simultaneously used as a solution. The error-corrected information RC _i itself substitutes only one root and thus does not become “Zero”.

Using this, a new Syndrome S ₁ is obtained based on Equation 14 on the assumption that the error corrected information RC _i is the first received information. That is, S ₁ is obtained by considering RC _i as r _i . At this time, the root is α ¹ , and when α ¹ is substituted, it has a value of “Zero”, which is information that one root (one error) existed, and the output value S ¹ is substituted by α ¹ . If it is not "Zero", it is information data in which two or more roots exist. This is because α ¹ is a root applied when one error occurs.

Therefore, to obtain S ₁ by considering RC _i as r _i is implemented as a first integrator MUX1 for receiving the RC _i based on Equation 14 and integrating the corresponding result through the multiplier 501. . In addition, calculating S ₀ by considering RC _i as r _i may be based on Equation 13. As a result, S ₀ is implemented as a second integrator MUX2 for integrating all RC _i . The output values of S ₁ and S ₀ provide a flag signal which is one output value through an OR gate OR.

In addition, the output terminal 503 is provided to utilize the error corrected information by outputting the RC _i in parallel.

As described above, the Syndrome generator 300 obtains S0 and S1, implements the error location determiner 200 through the S0 and S1, and error information detected through the error location determiner 200. In addition to implementing the error correction unit 400 based on the position information and the value of S0, an error flag generation circuit 500 for determining whether there is more than one error through an error corrected information is implemented. The error correcting unit 600 for the PID configured as described above is shown in FIG. 6, and the shift register 601 which is not described receives the input information R (I) serially input to the error correcting unit 400. It is a register to output in parallel.

On the other hand, since the Syndrome generating circuit 300 can generate the same result using the circuits of the multiplier 501 and the first and second accumulators MUX1 and 2 used in the error flag generator 500. In addition, the Syndrome generating circuit 300 or the multiplier 501 and the first and second accumulators MUX1 and 2 may be used in common in the present circuit.

The above description shows an error correction unit for PID in the DVD RAM. For this purpose, a flag for determining a noon for the correction result and a correction result are implemented by implementing Syndrome generation, error position determination, error correction, and error flag generation units, respectively. The output time can be processed in 1 Code Word section, which can reduce the correction time to less than 1/3. In addition, the implementation circuit is greatly reduced by analyzing the ECC standard in the PID of the DVD-RAM and implementing the simplified optimized circuit. This can be seen as a result of hardware design avoiding the duplication of the circuit due to parallel processing over three sections by processing within a single Code Word section.

What has been described above is only one embodiment for implementing the error correction unit for the PID in the DVD RAM according to the present invention, the present invention is not limited to the above-described embodiment, it is claimed in the claims As will be apparent to those skilled in the art to which the present invention pertains without departing from the gist of the present invention, the technical spirit of the present invention will be described to the extent that various modifications can be made.

1 is a table showing an operation procedure for conventional error correction,

2 is a block diagram showing an error position determining unit according to the present invention,

3 is a block diagram showing a syndrome generating unit (Syndrome) according to the present invention,

4 is a block diagram showing an error correction unit according to the present invention,

5 is a configuration diagram illustrating an error flag generator according to the present invention;

6 is an overall configuration diagram of the present invention.

<Explanation of symbols for the main parts of the drawings>

201, 309, 501: multiplier 203: comparator

301, 303: First and second registers 305, 307, 401 to 411: XOR gate

sel 0 to sel 5: selector MUX1, MUX2: first and second totalizer

OR: OR gate 200: error position discrimination unit

300: syndrome generator 400: error correction unit

500: error flag generator 601: shift register

Claims (5)

In the error correction circuit implementation for the PID (PID) in the DVD RAM, The input signal R (X) including the first PID information C (X) consisting of PID data of a predetermined byte, IED data of a predetermined byte, and error information E (X) is inputted to generate the generator polinomial of the R (X). A syndrome generator for generating syndromes S ₀ and S ₁ substituted with muscle; Receiving the syndromes S ₀ and S ₁ , S ₁ = ΣS ₀ * α ⁱ (i = 0 to 5) error position i (i = 0 to n-1 n: number of symbols constituting the code word) Error position discrimination to detect part; And An error correction unit configured to generate an error corrected result value RC _i by performing XOR logic on the received information r _i and the syndrome S ₀ corresponding to the detected error position i value; Error correction circuit for PD. The method of claim 1, wherein the RC _i generated by the error correcting unit is assumed to be an input signal R (X) ', and syndromes S ₀ and S ₁ are generated by substituting the root of the generator polinomial of the R (X)'. Afterwards, an error flag generator for outputting a result as a flag value by performing mutual OR logic on the information of S ₀ and S ₁ further includes an error for the PID in the DVD RAM. Correction circuit. The multiplier of claim 1, wherein the error position determiner receives a syndrome S ₀ and performs a multiplication operation of α ⁱ for each symbol unit, and the result information of the multiplier and the syndrome S ₁ for each symbol unit. An error correction circuit for a PID in a DVD RAM, comprising: a comparator for comparing and outputting a comparison output. The method of claim 1, wherein the error correction unit of the error location determination part receives said selected at the selector and the selector for selecting the received information r _i according to the error position based on the detected error position information from the information r _i and And an XOR logic gate configured to perform XOR logic on the syndrome S ₀ . 3. The apparatus of claim 2, wherein the error flag generator comprises: a multiplier configured to receive the R (X) 'information and perform a multiplication operation of α ^{i for} each symbol unit; A first accumulator (MUX1) for integrating result information of the multiplier; A second integrator (MUX2) for receiving the R (X) 'information and integrating the symbols for each symbol unit; An OR gate for performing OR logic on the output results of the first and second accumulators and for presuming the OR logic execution result to the flag; And And an output stage for utilizing the information of R (X) 'as a corrected result value.