KR100497962B1 - Liquid Crystal Display Manufacturing Method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of etching an insulating film covering a short circuit to disconnect the short circuit formed in the outer portion of the liquid crystal display after completing the thin film transistor in order to prevent static electricity generated during the manufacturing of the liquid crystal display. The method for manufacturing an active panel according to the present invention is characterized in that the pattern hole exposing the connecting portion of the short-circuit wiring is formed in a circle without a vertex. In the present invention, the shape of the pattern hole is formed in a circular shape with no vertices to prevent various stresses from concentrating on a specific position of the pattern hole. Accordingly, the pattern hole is not damaged or floated by various stresses.

Description

Liquid Crystal Display Manufacturing Method

The present invention relates to a method of disconnecting an antistatic short circuit in a liquid crystal display device manufacturing method. In particular, the present invention relates to a method of etching an insulating film covering a short circuit to disconnect the short circuit formed in the outer portion of the liquid crystal display after completing the thin film transistor in order to prevent static electricity generated during the manufacture of the liquid crystal display. will be.

Among the display devices that display image information on the screen, the CRT (or Cathode Ray Tube (CRT)) has been the most used so far, which is inconvenient to use because it is bulky and heavy compared to the display area. Therefore, even if the display area is large, the thin film type flat panel display device which has a small thickness and can be easily used in any place has been developed, and is gradually replacing the CRT display device. In particular, the liquid crystal display (or liquid crystal display) has the highest resolution than other flat panel displays, and the quality of the moving picture is faster than that of CRT. to be.

The driving principle of the liquid crystal display device is to use the optical anisotropy and polarization property of the liquid crystal. Since the structure is thin and long, the direction of the molecular arrangement can be controlled by artificially applying an electromagnetic field to liquid crystal molecules having directionality and polarization in the molecular arrangement. Accordingly, when the alignment direction is arbitrarily adjusted, light may be transmitted or blocked in accordance with the arrangement direction of the liquid crystal molecules by optical anisotropy of the liquid crystal, thereby applying the screen display device. Nowadays, the active matrix liquid crystal display device in which a thin film transistor (or TFT) and pixel electrodes connected thereto are arranged in a matrix manner is excellent in providing image quality and natural colors. The structure of the liquid crystal panel, which is a basic component of a general liquid crystal display, will be described in detail as follows.

The liquid crystal panel has two panels provided with various elements facing each other and a liquid crystal layer is sandwiched therebetween. One panel of the liquid crystal display includes elements that implement color. This is often called "color filter panel". In the color filter panel, red, green, and blue color filters are sequentially arranged along the positions of the pixels designed in a matrix arrangement on the first transparent substrate. Between these color filters, a very thin black matrix is formed. This prevents the appearance of mixed colors between each color. And the common electrode which covers a color filter is formed. The common electrode serves as one electrode for forming an electric field applied to the liquid crystal.

On the other panel of the liquid crystal display, switch elements and wirings for generating an electric field for driving the liquid crystal are formed. This is often called "active panel". In the active panel, pixel electrodes are formed along positions of pixels designed in a matrix manner on a second transparent substrate. The pixel electrode functions as the other electrode facing the common electrode formed on the color filter panel to form an electric field applied to the liquid crystal. Signal lines are formed along the horizontal array direction of the pixel electrodes, and data lines are formed along the vertical array direction. In the active matrix liquid crystal display device, a thin film transistor which is a switching element for applying an electric field signal to the pixel electrode is formed in one corner of the pixel electrode. In the case of an active matrix liquid crystal display device, the gate electrode of the thin film transistor is connected to the signal wiring (hence the signal wiring is also called "gate wiring"), and the source electrode is connected to the data wiring (thus) The data line is also referred to as a "source line"), and the drain electrode of the thin film transistor is connected to the pixel electrode. In the thin film transistor, a semiconductor layer is formed between the source electrode and the drain electrode, and the source electrode and the semiconductor layer, and the drain electrode and the semiconductor layer are in ohmic contact, respectively. At the ends of the gate wiring and the source wiring, gate pads and source pads, which are terminal terminals (or terminals) for receiving signals applied from the outside, are formed.

When an external electrical signal applied to the gate pad is applied to the gate electrode along the gate wiring, image information applied to the source pad is applied to the source electrode along the source wiring and is conducted to the drain electrode. On the other hand, when no signal is applied to the gate wiring, the source electrode and the drain electrode are disconnected. Therefore, it is possible to determine whether to apply the data signal to the drain electrode by adjusting the signal of the gate electrode. Therefore, the data signal can be artificially transferred to the pixel electrode connected to the drain electrode. That is, the thin film transistor serves as a switch for driving the pixel electrode. A gate insulating film is formed between the layer on which the gate wiring is formed and the layer on which the source wiring is formed, and a protective film for protecting the device is formed on the layer on which the source wiring is formed.

The two panels thus made (color filter panel and active panel) are attached to each other at a predetermined interval (referred to as "cell gap"), and the liquid crystal material is filled therebetween. The edges of the two substrates are sealed with epoxy-like seals to keep the cell gap between the two panels constant and to prevent the liquid crystal material from leaking out. Thus, the liquid crystal panel which is the main part of the liquid crystal display device is completed.

The present invention relates to manufacturing an active panel including a thin film transistor among the elements constituting the liquid crystal panel. In manufacturing an active panel, short wirings are formed at the edges of the panel to prevent static electricity from being generated in the process of forming the thin film transistor. Short-circuit wiring is made to equipotentially connect the wirings temporarily in order to prevent the thin film transistor from being destroyed due to the potential difference caused by static electricity between various wirings such as the gate wiring and the data wiring. However, since the short-circuit wiring is not necessary in the final product, it is removed after the thin film transistor is completed, or the connected parts are disconnected without necessity. Referring to FIG. 1, which is a plan view illustrating an active panel, and FIG. 2, which illustrates a process of manufacturing an active panel, a short circuit is formed in the process of manufacturing an active panel, and a process of disconnecting the short circuit will be described in detail.

A metal including aluminum is deposited on the transparent glass substrate 1 and patterned to form the gate electrode 11, the gate wiring 13, the gate pad 15, and the short circuit wiring 19. The gate electrode 11 is formed at one corner of the pixel designed to be arranged in a matrix manner. The gate line 13 connects the gate electrodes 11 arranged in the row direction. The gate pad 15 is formed at the end of the gate line 13. In addition, the short circuit line 19 is formed at an edge of the substrate 1 while connecting the gate pads 15. The short wiring 19 is also connected to the source pads formed later to prevent static electricity. Therefore, the short wiring 19 is divided into partial wirings connecting the gate pads and partial wirings connecting the source pads, and includes a connecting portion 19a connecting the partial wirings. A gate insulating film 17 is formed by depositing an insulating material containing silicon oxide or silicon nitride on the entire surface of the substrate on which the short wirings 19 and the like are formed (FIG. 2A).

Subsequently, pure semiconductor materials such as pure amorphous silicon and impurity semiconductor materials such as amorphous silicon to which impurities are added are sequentially deposited. The pure semiconductor material and the impurity semiconductor material are patterned to form a semiconductor layer 33 and an impurity semiconductor layer 35 on the gate electrode 11 (FIG. 2B).

The gate insulating layer 17 is patterned to expose a portion of the shorting line 19 to form a shorting line contact hole 29. The exposed portion of the short wiring 19 is preferably a portion in which a source pad formed later can easily contact the short wiring 19. Then, a metal containing chromium or molybdenum is deposited and patterned to form the source wiring 23, the source electrode 21, the drain electrode 31, and the source pad 25. The source wiring 23 runs along the column arrangement of the pixels. The source electrode 21 branches from the source wiring 23 and makes ohmic contact with the impurity semiconductor layer 35 overlapping one side of the gate electrode 11. The drain electrode 31 faces the source electrode 21 and makes ohmic contact with the impurity semiconductor layer 35 overlapping the other side of the gate electrode 11. The source pad 25 is formed at the end of the source wiring 23 and is electrically connected to the short circuit wiring 19 exposed through the short wiring contact hole 29. The impurity semiconductor layer 35 is etched by etching the impurity semiconductor layer 35 using the source electrode 21 and the drain electrode 31 as a mask (FIG. 2C).

A protective film 37 is formed by depositing an insulating material such as silicon oxide or silicon nitride on the entire surface of the substrate on which the source electrode 21 is formed. The passivation layer 37 is patterned to form a source contact hole 69 exposing the source pad 25, and a drain contact hole 79 exposing a portion of the drain electrode 31. The protective layer 37 and the gate insulating layer 17 covering the gate pad 15 are patterned to form a gate contact hole 59 exposing the gate pad 15. In this case, the passivation layer 37 and the gate insulating layer covering the connection portion 19a connecting the partial wirings connecting the gate pads 15 and the partial wirings connecting the source pads 25 among the short wirings 19. A pattern hole 39 is formed in 17 to expose the connecting portion 19a. This is to separate the partial short wiring connecting the gate wiring 13 and the partial short wiring connecting the source wiring 23 by removing the connecting portion 19a by an etching method later (FIG. 2D).

Indium Tin Oxide (ITO) is entirely deposited on the passivation layer 37. At this time, the ITO film 41a covers the connecting portion 19a of the short-circuit wiring 19 exposed through the pattern hole 39. Thus, when the ITO film 41a is deposited, each wiring and the ITO film 41a are covered. An equipotential is formed between them to prevent damage due to static electricity (FIG. 2E).

The ITO layer 41a is patterned to form a pixel electrode 41, a gate pad connection terminal 51, and a source pad connection terminal 61. The pixel electrode 41 is in contact with the drain electrode 31 through the drain contact hole 79. The gate pad connection terminal 51 and the source pad connection terminal 61 are respectively connected to the gate pad 15 through the gate contact hole 59 and the source pad 25 through the source contact hole 69. It is formed to contact with. Then, the connection portion 19a of the exposed short circuit line 19 is removed by an etching method (Fig. 2F).

In the conventional active panel manufacturing process, the pattern hole 39 exposing the connecting portion 19a of the short-circuit wiring 19 as one side for disconnecting the short-circuit wiring 19 generally has a rectangular shape. In this case, as shown in FIGS. 1 and 2F, when the thermal stress applied to the gate insulating film 17 and the protective film 37 is imbalanced, stress is concentrated at the vertex portion of the square pattern, so that the gate insulating film 17 and the protective film are unbalanced. (37) breaks or floats.

As such, when the thin film for protecting or insulating the metal layer is broken or floated, the etching solution penetrates therebetween, and a large portion of the thin film may be damaged, thereby causing a defect in the active panel itself. An object of the present invention is to form a pattern hole for exposing the connection portion to be stable to various stresses in order to disconnect the short circuit. Another object of the present invention is to make the pattern hole have a stress stable form, so that the thin film for insulation or protection having the pattern hole is not broken or lifted. Another object of the present invention is to prevent failure of the active panel by preventing the thin film for insulation or protection.

In order to achieve the objects of the present invention, a method of manufacturing an active panel according to the present invention is characterized by forming a pattern hole that exposes a connection portion of a short-circuit wiring in a circular shape without a vertex. According to an aspect of the present invention, there is provided a method of manufacturing an active panel, the method comprising: forming a plurality of gate wirings and a plurality of short circuit wirings connecting the plurality of gate wirings to a substrate; forming a gate insulating film on the short circuits; and forming a contact hole in the insulating film. Forming a plurality of source wirings connected to the short-circuit wiring through the contact hole, forming a protective film on the source wiring, and patterning the protective film and the gate contact hole to form a portion of the short-circuit wiring. Forming a circular pattern hole that is exposed, and cutting a connection between the gate line and the source line by removing a portion of the diffuser shorting line exposed to the pattern hole. The present invention forms a circular shape of the pattern hole formed to separate the short-circuit wiring, thereby preventing the stress from being concentrated in any one place even if various stresses are applied to the pattern hole. A more detailed description will be made with reference to FIG. 3 showing a plan view of the active panel according to the present invention, and FIG. 4 showing a manufacturing method thereof in a cross section taken along cut line IV-IV of FIG.

A metal including aluminum is deposited on the transparent glass substrate 101 and patterned to form the gate electrode 111, the gate wiring 113, the gate pad 115, and the short circuit wiring 119. The gate electrode 111 is formed at one corner of the pixel designed to be arranged in a matrix manner. The gate line 113 connects the gate electrodes 111 arranged in the row direction. The gate pad 115 is formed at the end of the gate wiring 113. In addition, the short-circuit wiring 119 is formed at the edge of the substrate 101 while connecting the gate pads 115. The short wiring 119 is also connected to source pads formed later to prevent static electricity. Therefore, the short wiring 119 is divided into partial wirings connecting the gate pads and partial wirings connecting the source pads, and includes a connection portion 119a connecting the partial wirings. A gate insulating film 117 is formed by depositing an insulating material including silicon oxide or silicon nitride on the entire surface of the substrate on which the short circuit line 119 and the like are formed (FIG. 4A).

Subsequently, pure semiconductor materials such as pure amorphous silicon and impurity semiconductor materials such as amorphous silicon to which impurities are added are sequentially deposited. The pure semiconductor material and the impurity semiconductor material are patterned to form a semiconductor layer 133 and an impurity semiconductor layer 135 on the gate electrode 111 (FIG. 4B).

The gate insulating layer 117 is patterned to form a short circuit wiring contact hole 129 exposing a part of the short circuit wiring 119. The exposed portion of the short circuit 119 is preferably a portion in which a source pad to be formed later can easily contact the short circuit 119. The metal including chromium or molybdenum is deposited and patterned to form a source wiring 123, a source electrode 121, a drain electrode 131, and a source pad 125. The source wiring 123 runs along the column array of the pixels. The source electrode 121 is branched from the source wiring 123 and makes ohmic contact with the impurity semiconductor layer 133 overlapping one side of the gate electrode 111. The drain electrode 131 faces the source electrode 121 and makes ohmic contact with the impurity semiconductor layer 135 overlapping the other side of the gate electrode 111. The source pad 125 is formed at an end portion of the source wiring 123 and is electrically connected to the short circuit wiring 119 exposed through the short circuit wiring contact hole 129. The impurity semiconductor layer 135 is etched using the source electrode 121 and the drain electrode 131 as a mask to quantify the impurity semiconductor layer 135 (FIG. 4C).

A protective film 137 is formed by depositing an insulating material such as silicon oxide or silicon nitride on the entire surface of the substrate on which the source electrode 121 is formed. The passivation layer 137 is patterned to form a source contact hole 169 exposing the source pad 125, and a drain contact hole 179 exposing a portion of the drain electrode 131. The protective layer 137 and the gate insulating layer 117 covering the gate pad 115 are patterned to form a gate contact hole 159 exposing the gate pad 115. In this case, the passivation layer 137 and the gate insulating layer 117 covering the connection portion 119a connecting the partial wiring connecting the gate pads 115 and the partial wiring connecting the source pads 125 among the short wirings 119. ) To form a circular pattern hole 139 to expose the connecting portion (119a). This is to separate the partial short wiring connecting the gate wiring 113 and the partial short wiring connecting the source wiring 123 by removing the connecting portion 119a by an etching method (FIG. 4D).

Indium Tin Oxide (ITO) is entirely deposited on the passivation layer 137. At this time, the ITO film 141a covers the connection portion 119a of the short circuit line 119 exposed through the circular pattern hole 139. Thus, when the ITO film 141a is deposited, an equipotential is formed between each wiring and the ITO film, thereby preventing damage due to static electricity (FIG. 4E).

The ITO layer 141a is patterned to form a pixel electrode 141, a gate pad connection terminal 151, and a source pad connection terminal 161. The pixel electrode 141 is in contact with the drain electrode 131 through the drain contact hole 179. The gate pad connecting terminal 151 and the source pad connecting terminal 161 are respectively connected to the gate pad 115 through the gate contact hole 159 and the source pad 125 through the source contact hole 169. It is formed to contact with. And. The exposed connecting portion 119a of the short circuit 119 is removed by etching (FIG. 4F).

In the present exemplary embodiment, the pattern hole 139 exposing the connection portion 119a is formed in a circular shape to separate the short circuit line 119. However, even when forming contact holes exposing other portions, the contact holes forming portions of the protective film or the insulating film may be prevented from being broken or lifted by various stresses if they are formed in a circular shape rather than a polygon having vertices. That is, the short-circuit wiring contact hole 129 connecting the short-circuit wiring 119 and the source pad 125, the gate contact hole 159 and the source pad 125 connecting the gate pad 115 and the gate pad connection terminal 151. ) And the source contact hole 169 connecting the source pad connection terminal 161 and the drain contact hole 179 connecting the pixel electrode 141 and the drain electrode 131 may be formed in a circular shape without a vertex. Do.

The present invention relates to a method of connecting the gate wiring and the source wiring to prevent the generation of static electricity during the formation of the thin film transistor when the active panel is manufactured, and disconnecting the short wiring formed at the edge of the panel after the thin film transistor is completed. It is related. Conventionally, the portions in which the partial short wirings connecting the gate wirings and the partial short wirings connecting the source wirings are connected to each other are removed by an etching method. As one of the methods, an insulating film or a protective film covering the connection portion of the short-circuit wiring was patterned and exposed through the pattern hole, and then removed by etching. At this time, the shape of the pattern hole was used to form a square, in which case the thermal stress is concentrated at the vertex, causing the protective film and the insulating film to be damaged. In the present invention, the shape of the pattern hole is formed in a circular shape without a vertex to prevent the thermal stress from concentrating on a specific position of the pattern hole. Accordingly, the pattern hole is not damaged or floated by various stresses. As a result, the yield of active panel production is expected to increase.

1 is a plan view showing a conventional structure of an active panel used in a liquid crystal display device.

2A to 2F are process cross-sectional views showing a conventional method for manufacturing an active panel used in a liquid crystal display device.

3 is a plan view showing the structure of an active panel used in the liquid crystal display according to the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing an active panel used in a liquid crystal display according to the present invention.

<Description of the reference numerals for the main parts of the drawings>

1, 101: substrate 11, 111: gate electrode

13, 113: gate wiring 15, 115: gate pad

17, 117: gate insulating film 19, 119: short-circuit wiring

21, 121: source electrode 23, 123: source wiring

25, 125: source pads 29, 129: short-circuit wiring contact hole

33, 133: semiconductor layer 35, 135: impurity semiconductor layer

37, 137: protective film 39, 139: pattern holes

41a and 141a: ITO film 41 and 141: pixel electrode

19a, 119a: connection part 51, 151: gate pad connection terminal

61, 161: source pad connection terminals 59, 159: gate contact hole

69, 169: source contact hole 79, 179: drain contact hole

Claims (7)

Forming a short circuit wiring connecting the gate wiring and the gate wiring on the transparent substrate; Forming a gate insulating film on the gate wiring and the short circuit; Patterning the gate insulating film to form a circular pattern hole exposing a portion of the short circuit line; And removing a part of the short-circuit wiring exposed through the circular pattern hole. The method of claim 1, And removing portions exposed through the pattern holes of the short-circuit wiring by an etching method. Forming a gate pad, a gate wiring connected to the gate pad, and a short circuit wiring connected to the gate pad on a transparent substrate; Forming a gate insulating film covering the gate pad, the gate wiring, and the short circuit; Patterning the gate insulating film to expose a portion of the short circuit; Forming a source pad in contact with a portion of the exposed short circuit wiring on the gate insulating layer and a source wiring connected to the source pad; Forming a passivation layer covering the source pad and the source wiring; Patterning the passivation layer and the gate insulating layer to form a circular pattern hole exposing a portion of a short circuit line; And removing a part of the short-circuit wiring exposed through the circular pattern hole. The method of claim 3, wherein In the forming of the gate wiring, further forming a gate electrode connected to the gate wiring; Forming a semiconductor layer over the gate insulating film and two impurity semiconductor layers bisected on the semiconductor layer; Forming a source electrode which is branched from the source wiring and contacts the one impurity semiconductor layer in the step of forming the source wiring, and a drain electrode which is in contact with the another impurity semiconductor layer opposite the source electrode; Patterning the passivation layer to expose the drain electrode; And forming a pixel electrode in contact with the exposed drain electrode on the passivation layer. The method according to any one of claims 3 and 4, And removing a portion of the short-circuit wiring exposed to the pattern hole by an etching method. Forming a first metal layer on the transparent substrate; Forming an insulating film covering the first metal layer; Patterning the insulating film to form a circular pattern hole exposing a portion of the first metal layer; And removing a portion of the first metal layer exposed through the circular pattern hole. The method of claim 6, And removing the exposed portion of the first metal layer by etching.