KR100497000B1 - Column driver drive circuit of PD drive - Google Patents

Abstract

The present invention relates to a column driver driving circuit using a multi-phase clock signal of a PDP driving apparatus for driving a column driver using a multi-phase clock signal to improve the operation speed of the column driver to drive a high resolution PDP.

To this end, the present invention provides a PDP 10, which is a display device having m × k × h columns, and m × k column drivers having a shift register composed of h flip-flops, each of which is divided into k groups. First to kth column driver portions 101-1, 101-2, ..., 101-k each having m x h output lines divided therein, and the first to kth column driver portions 101-1. Multi-phase clock signals (clk_1, ..., clk_k) having k different phases for driving .101-2, ..., 101-k, respectively, and each of the bits includes the first to kth columns. It consists of m-bit column driver data buses each connected by shift registers in m column drivers of the driver sections 101-1, 101-2, ..., 101-k.

Description

Column Driver Drive Circuit of PD Drive

The present invention relates to a high resolution plasma display panel (PDP) driving device, and to driving a column driver using a multi-phase clock signal to improve the operation speed of the column driver, The present invention relates to a column driver driving circuit using a multi-phase clock signal of a PDP driving device for driving a PDP.

As shown in the block diagram of FIG. 1, a general PDP driving apparatus includes a data arranging unit 20 for arranging input image signal data RGB according to a scanning method of the PDP 10, and the data arranging unit ( A frame / field memory 30 for storing the data sorted by 20), a row driver unit 40 for selecting a row to drive the PDP 10, and A column driver which receives the line data of the row selected by the row driver 40 and converts it into a high voltage after applying it to the frame / field memory 30 and applies it to the PDP 10. The part 50 is comprised.

In the drawing, reference numeral 60 denotes a controller unit which generates a timing signal for a high voltage pulse input to each electrode of the PDP 10 and controls the operation of the entire circuit.

FIG. 2 shows a block diagram of each of the column drivers constituting the column driver unit 50. Input data is changed from IN_data to F / F_1 and F / F_1 to F / F_2 at the starting point of the clock CLK. To,… … And a shift register section 51 for shifting from F / F_ (n-1) to F / F_n (OUT_data) directions, respectively, and S_1 to S_n at a positive edge of LE. Parallel register section 52 for latching the signals L_1 to L_n, and a high voltage driver for converting the voltage of the low logic signal into a high voltage capable of driving the pixels of the PDP ( 53).

The operation of the conventional PDP driving apparatus configured as described above will be described with reference to FIGS. 1 to 4.

First, FIG. 3 is a timing diagram showing the operation of the column driver shown in FIG. Here, Di, j represents data input to the column driver unit 50. This data is received from the shift register section 51 at the positive starting point of the LE by the parallel register section 52, and held up to the starting point of the next positive LE.

4 shows a block diagram of a column driver driving circuit using the column driver 50 shown in FIG.

The data bus connected to the column driver section 50 has a width of r bits, and each bit line has r column drivers, i.e., the first to r th column drivers C1, C2, ..., and And a single phase clock signal is used as a trigger signal for operating the shift register section 51 composed of flip-flops (F / F) in the column driver. If you use h flip-flops in every column driver, the row data has rxh bits.

The parallel register unit 52 accepts the Joule data entered into the shift register unit 51 in accordance with the positive starting point of the LE signal, and maintains it until it becomes the positive starting point of the LE signal again. The time for which the parallel register unit 52 maintains data is determined by the vertical resolution of the PDP panel 10 and the number of image frames or fields displayed at a unit time. The shift register section 51 of the driver aligns the line data to be used next.

Such a column driver driving circuit can be used when the number of columns Col_n of the PDP panel 10 is equal to or less than r × h, as shown in Equation 1 below.

[Equation 1]

Col_n ≤ r × h

If the horizontal resolution of the PDP panel 10 is increased and the number of columns is greater than r × h, the column having the shift register section 51 composed of H flip-flops satisfying Equation 2 below is given. A screwdriver must be used (where H> h)

[Equation 2]

Col_n ≤ r × H

When the number of flip-flops in the internal shift register 51 of the column driver increases from h to H, the operating speed of the column driver and the frequency of the clock signal are aligned in H / h to align data to the H flip-flops during the same time. You need to increase your stomach.

If the operation speed of the shift register unit 51 of the column driver is limited and cannot be operated at a higher speed, the number of column drivers and the number of bits of the data bus must be increased. That is, if the number of columns of the PDP panel 10 increases from r × h to r × H and the operation speed of the column driver cannot be increased, the number of column drivers and the number of bits of the data bus must be increased by H / h.

Even when the vertical resolution of the PDP panel 10 is increased and the number of rows is increased, the time for which the parallel register unit 52 retains Joule data becomes relatively small. Suppose the number of lines of vertical resolution has increased from a to A. In this case, since the time given by the parallel register unit 52 to hold the joule data is reduced by a / A times, the operating speed of the column driver must be increased by A / a times.

If the operation speed of the column driver cannot be increased, the number of flip-flops used in the shift register section 51 should be reduced, and the number of bits of the data bus should be increased. For example, if the number of rows of the PDP panel 10 increases from a to A but the operation speed of the column driver cannot be increased, the number of shift registers 51 flip-flops in the column driver to be used is a / A. The number of bits in the column driver and data bus must be increased by H / h.

However, due to the high voltage driver, the column driver of the related art has a slower operating speed than a logic gate or flip-flip. Therefore, a difficult problem of increasing the number of bits of the column driver and the data bus has arisen.

Therefore, in order to more easily improve the resolution of the PDP panel, the technical development of the column driver operating at high speed has been an urgent demand.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional requirements. First, the operating speed of the column driver is improved by driving the column driver using a multi-phase clock signal. In the design of a resolution PDP driving circuit, the purpose is to reduce the number of column drivers and the width of the data bus connected thereto or to apply Joule data to the columns of the PDP at high speed.

The technical means of the present invention for achieving the above object is a PDP, which is a display device, first to kth column driver sections each divided by m into m groups of m × k column drivers, and the first to kth columns. A multi-phase clock signal having k different phases for driving the column driver unit independently, and each bit is composed of an m-bit column driver data bus each connected to m column drivers of the first through k-th column driver units. It is done.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

Fig. 5 shows a block diagram of a column driver driving circuit according to the present invention, in which a PDP 10 which is a display device having m × k × h columns and m having a shift register composed of h flip-flops is shown. The first to kth column driver portions 101-1, 101-2, ..., 101-k each having m x h column drivers divided into k groups each having m x h output lines; Multi-phase clock signals (clk_1, ..., clk_k) having k different phases for independently driving the first to k th column driver units 101-1, 101-2, ..., 101-k, respectively. ) And an m-bit column driver data bus each of which bits are connected to shift registers in m column drivers of the first through k th column driver units 101-1, 101-2,..., 101-k, respectively. column driver data bus).

The operation and effect of the present invention configured as described above will be described with reference to FIGS. 1 and 5 to 8 as follows.

First, the connection state of m bits constituting the column driver data bus will be described by way of example, that is, the first to k th column driver units 101-1, 101-2,... Bit number 1 is connected to column driver C1 of column m driver of 101-k), and bit 2 is connected to column driver C2 of column 2. … bit m is connected to column driver Cm. That is, the column driver data bus divides data in time in order of inputting the first to k th column driver units 101-1, 101-2,..., 101-k and transfers the data to each column driver unit.

Meanwhile, the first to k th column driver units 101-1, 101-2,..., 101-k illustrated in FIG. 5 correspond to the column driver unit 50 in the PDP driving apparatus illustrated in FIG. 1. .

Therefore, the first to kth column driver portions 101-1, 101-2, ..., 101-k dividing m x k column drivers into k groups by m are multi-phases having k different phases. It is driven independently by the clock signals clk_1, ..., clk_k.

The column driver data bus is m bits, each bit is connected to one of the column drivers in each column driver part, and since the column driver has a shift register composed of h flip-flops, the first to k th column driver parts ( The number of output lines from 101-1, 101-2, ..., 101-k) is not only m x h, but also the number of columns of the PDP panel 10 is m x h x k.

In addition, the controller unit 60 of the PDP driving apparatus transmits m-bit data from the frame / field memory 30 to the row data of the corresponding row in the order of the clock phase. When driving the column drivers belonging to the j-th column driver unit 101-j using ≤ j ≤ k), the j-th column driver unit 101-j of the j-th column driver unit 101-j is synchronized with the clock j at the same time. By transferring data, only the column drivers of the j-th column driver unit 101-j are accepted. That is, only the column drivers of the group operating by the corresponding clock phase signal among the first to k th column driver units 101-1, 101-2,..., 101-k receive this.

FIG. 6 is a timing diagram for the operation of the column driver driving circuit shown in FIG. 5, FIG. 7 is a diagram showing data input to the column driver data bus shown in FIG. 5, and FIG. 8 is m column drivers ( The data stored in the shift registers in C1, C2, ..., Cm) are shown.

6 and 7, Tij means time for inputting the i-th data to the j-th column driver unit 101-j. Since each column driver has a shift register consisting of h flip-flops and all of the k column driver sections, the alignment of the row data starts at T11 and is completed at Thk.

In FIG. 6, the number shown in the column driver data bus means that m-bit data to be input to the corresponding column driver enters the data bus.

Therefore, in FIG. 6, each column driver receives data at each clock signal period, but data of the column driver data bus is transmitted by changing data at adjacent clock phase difference periods, and the speed of sorting the data is improved by k times. It can be seen.

In FIG. 7, the data bit number indicates the data bit number of the column driver data bus, and Dabc means the bit data to be input into the c-th column driver Cc belonging to the b-th column driver unit 101-b.

That is, as shown in FIG. 7, when the alignment of the row data is completed, Dabc is the a-th from the last flip-flop among the flip-flops of the shift register of the c-th column driver Cc of the b-th column driver 101-b. The flip-drop is saved.

8 illustrates data input to the shift register in the column driver at the time when the row data starts to be input and the h data cycle is completed and the row data is input.

As described above, the present invention not only improves the operation speed of the column driver by driving the column driver by using the multi-phase clock signal, but also in the design of the high resolution PDP driving circuit, the number of column drivers and their connection to them. This reduces the width of the data bus, or allows high speed data to be applied to the columns of the PDP.

When the width of the data bus of the PDP column driver needs to be increased, the data is divided over the bus in time, and the width of the data bus is equally increased by selectively accepting the data using the multi-phase clock signal. There is an effect that can be used to.

In particular, the shift register, the parallel register unit, and the high voltage driver constituting the column driver unit may be utilized when the chip is implemented as a single chip, or when the column driver unit is implemented as a single chip, and the shift register and the parallel register unit are the clock signals. It can be applied to all cases implemented using a latch operated by the level of the flip-flop or the clock signal operated by the starting point of.

1 is a block diagram of a general PDP driving apparatus.

FIG. 2 is a block diagram of each of a plurality of column drivers forming the column driver shown in FIG. 1; FIG.

3 is a timing diagram showing the operation of the column driver shown in FIG. 2;

4 is a block diagram of a column driver driving circuit using the column driver shown in FIG.

5 is a block diagram of a column driver driving circuit according to the present invention;

6 is a timing diagram for the operation of the column driver driving circuit shown in FIG.

FIG. 7 is data input to the column driver data bus shown in FIG. 5; FIG.

8 is data stored in a shift register in the column driver shown in FIG.

*** Explanation of symbols for the main parts of the drawing ***

101-1: First column driver part 101-2: Second column driver part

101-k: kth column driver part

clk_1, ..., clk_k: multi phase clock signal

Claims (4)

PDP, which is a display device, First to kth column driver sections each of m column drivers divided into k groups, m each; A multi-phase clock signal having k different phases respectively driving the first to k th column driver units independently; And each bit comprises an m-bit column driver data bus connected to m column drivers of the first to k-th column driver units, respectively. The method of claim 1, When the number of columns of the PDP is m × k × h, the shift register in the column driver is configured as h flip-flops, so that the first to k th column driver parts have m × h output lines, respectively. Column driver drive circuit of the PD drive. The method of claim 1, And said column driver data bus transfers data to each column driver section in time in order of inputting said first to k th column driver sections. The method of claim 1, The j-th column driver part of the multi-phase clock signal is driven to the column driver data bus by synchronizing with the clock j while driving the column drivers belonging to the j-th column driver part using the clock j (1 ≦ j ≦ k). A column driver driving circuit of a PD driver for transmitting data so that only the column drivers of the j-th column driver are accepted.

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