KR100489167B1 - Thin film transistor and its manufacturing method - Google Patents
Thin film transistor and its manufacturing method Download PDFInfo
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- KR100489167B1 KR100489167B1 KR10-1998-0033784A KR19980033784A KR100489167B1 KR 100489167 B1 KR100489167 B1 KR 100489167B1 KR 19980033784 A KR19980033784 A KR 19980033784A KR 100489167 B1 KR100489167 B1 KR 100489167B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000010408 film Substances 0.000 claims abstract description 231
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 117
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 113
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 78
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 239000001301 oxygen Substances 0.000 claims abstract description 38
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000137 annealing Methods 0.000 claims abstract description 22
- -1 oxygen ions Chemical class 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 239000013078 crystal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000001179 sorption measurement Methods 0.000 claims description 6
- 230000035515 penetration Effects 0.000 claims description 4
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 47
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 16
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000011521 glass Substances 0.000 description 10
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 9
- 229910052750 molybdenum Inorganic materials 0.000 description 9
- 239000011733 molybdenum Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000005224 laser annealing Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 125000004430 oxygen atom Chemical group O* 0.000 description 6
- 239000011734 sodium Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009832 plasma treatment Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052708 sodium Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Abstract
본 발명은 박막트랜지스터에 관한 것으로서, 비정질실리콘 막의 어닐링처리 후에, 게이트 실리콘산화막과 폴리실리콘막 계면에서 불순물이나 부정합(mismatch)을 감소시키는 데 그 목적이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and aims to reduce impurities and mismatches at the interface between the gate silicon oxide film and the polysilicon film after annealing the amorphous silicon film.
본 발명은 기판 상에 비정질실리콘막을 증착하고, 비정질실리콘막의 계면에 산소이온을 흡착시킴으로써 비정질실리콘 산화막을 형성하고, 비정질실리콘막을 어닐링에 의해 폴리실리콘막으로 결정화하고, 비정질실리콘 산화막을 일정한 당량비를 가지는 실리콘산화막으로 변화시키는 것을 포함하는 박막트랜지스터 제조방법 및 그 제조방법에 의해 제조된 박막트랜지스터를 개시하고 있다.The present invention forms an amorphous silicon oxide film by depositing an amorphous silicon film on a substrate, adsorbing oxygen ions at the interface of the amorphous silicon film, crystallizing the amorphous silicon film into a polysilicon film by annealing, and having the amorphous silicon oxide film have a constant equivalent ratio. A method of manufacturing a thin film transistor comprising changing to a silicon oxide film and a thin film transistor manufactured by the method are disclosed.
Description
본 발명은 박막트랜지스터 (TFT : Thin Film Transistor)에 관한 것으로서, 특히, 게이트 실리콘산화막과 폴리실리콘막 계면에서 불순물이나 부정합(mismatch)을 감소시키는 박막트랜지스터 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT), and more particularly, to a thin film transistor and a method of manufacturing the same, which reduce impurities and mismatches at the interface between a gate silicon oxide film and a polysilicon film.
액티브 매트릭스 액정 디스플레이에서, 액티브소자로 주로 사용되는 박막트랜지스터(이하 TFT라 한다)는 활성층(active layer)에 사용되는 박막의 종류에 따라 비정질실리콘막 박막트랜지스터(a-Si TFT)와 폴리실리콘막 박막트랜지스터(p-Si TFT)로 나누어진다. 도 1은 종래의 폴리실리콘막 박막트랜지스터 활성층으로 사용되는 폴리실리콘막 공정의 개략도이다. 여기서, 도면의 명료성을 위해 박막트랜지스터의 전극으로 사용되는 게이트, 소오스/드레인 전극 등은 도시를 생략한다.In an active matrix liquid crystal display, a thin film transistor (hereinafter referred to as TFT) mainly used as an active element is an amorphous silicon thin film transistor (a-Si TFT) and a polysilicon film thin film depending on the type of thin film used for the active layer. It is divided into a transistor (p-Si TFT). 1 is a schematic diagram of a polysilicon film process used as a conventional polysilicon film thin film transistor active layer. Here, the gate, source / drain electrodes, etc. used as the electrodes of the thin film transistors are omitted for clarity.
도 1 (a) ∼ 도 1 (d)에 도시된 바와 같이, 박막트랜지스터 내로 나트륨(Na)등 불순물의 침투를 방지하고, 또한, 유리기판(1)과 박막트랜지스터를 구성하는 막과의 응력(stress) 및 접착력을 향상시키기 위해 일종의 버퍼 층으로서 실리콘산화막(2)이 유리기판(1) 상에 증착된다 (도 1 (a)). 다음에, 비정질실리콘막(3)을 실리콘산화막(2) 상에 연속으로 순차 증착하고 (도 1 (b)), 비정질실리콘막(3)은 레이저 어닐링에 의해 폴리실리콘막(4)으로 결정화된다 (도 1 (c)). 결정화된 폴리실리콘막 (4)은 박막트랜지스터의 활성층(active layer)으로 사용된다.As shown in FIGS. 1A to 1D, the penetration of impurities such as sodium (Na) into the thin film transistor is prevented, and the stress between the glass substrate 1 and the film constituting the thin film transistor ( In order to improve stress) and adhesion, a silicon oxide film 2 is deposited on the glass substrate 1 as a kind of buffer layer (Fig. 1 (a)). Next, the amorphous silicon film 3 is successively deposited on the silicon oxide film 2 (FIG. 1 (b)), and the amorphous silicon film 3 is crystallized into the polysilicon film 4 by laser annealing. (FIG. 1 (c)). The crystallized polysilicon film 4 is used as an active layer of the thin film transistor.
다음에, 박막트랜지스터의 전하유도를 위해 게이트실리콘 산화막(5)이 폴리실리콘막에 증착되며, 액정디스플레이용 박막트랜지스터의 게이트실리콘 산화막은 비교적 저온(300∼450℃)에서 증착되는 PECVD(Plasma Enhanced Chemical Vapor Deposition) 실리콘 산화막이나 APCVD(Atmospheric Pressure Chemical Vapor Deposition) 실리콘 산화막이 주로 사용되고 있다 (도 1 (d)).Next, the gate silicon oxide film 5 is deposited on the polysilicon film for inducing charge of the thin film transistor, and the gate silicon oxide film of the thin film transistor for liquid crystal display is deposited at a relatively low temperature (300 to 450 ° C.). Vapor Deposition) A silicon oxide film or an APCVD (Atmospheric Pressure Chemical Vapor Deposition) silicon oxide film is mainly used (Fig. 1 (d)).
또한, 폴리실리콘막 박막트랜지스터의 전기적 특성(전하이동도, 문턱전압 등)은 상기 게이트실리콘 산화막(6)과 활성층인 폴리실리콘막(4)의 전기적 특성뿐만아니라 계면(5)에서 트랩에너지의 상태밀도 (Density of Trap Energy States)에 의해 결정된다. 계면(5)에 형성되는 트랩에너지의 상태밀도는 비정질실리콘막과 실리콘 산화막 사이의 응력에 의해 주로 결정되지만, 어닐링 될때, 과도한 열에너지에 의한 손상 정도로 결정된다. 이렇게 결정된 계면의 트랩에너지의 상태밀도가 높을수록 TFT 소자는 높은 누설전류를 가지고, 낮을수록 낮은 누설 전류를 가진다. 따라서, 각 박막의 특성을 개선하고, 게이트실리콘 산화막(6)과 폴리실리콘막(4) 계면(5)에서 전하를 트랩하는 트랩에너지의 상태밀도를 감소시키는 방법이 연구되고 있다.In addition, the electrical characteristics (charge mobility, threshold voltage, etc.) of the polysilicon thin film transistor are not only the electrical characteristics of the gate silicon oxide film 6 and the polysilicon film 4 as the active layer, but also the state of the trap energy at the interface 5. Determined by Density of Trap Energy States. The state density of the trap energy formed at the interface 5 is mainly determined by the stress between the amorphous silicon film and the silicon oxide film, but when annealed, it is determined to the extent of damage due to excessive thermal energy. The higher the state density of the trap energy at the interface thus determined, the higher the leakage current of the TFT element, and the lower the lower the current leakage. Therefore, a method of improving the characteristics of each thin film and reducing the state density of trap energy trapping charge at the interface 5 of the gate silicon oxide film 6 and the polysilicon film 4 has been studied.
또한, 트랩에너지의 상태밀도를 감소시키는 방법은 어닐링장치에 의존성이 있기 때문에 어닐링장치의 개량도 연구되고 있다. 하지만, 종래에 사용되고 있는 퍼니스(furnace) 장치는 결정화에 장시간이 소요되고, 고온을 사용하기 때문에 유리기판(1)이 사용되는 디스플레이용 소자에는 적합하지 않아, 최근에는 결정화가 단시간에 되고, 저온 공정이 되는 엑시머 레이저 어닐링 방법이 주로 연구되고 있다.In addition, since the method of reducing the state density of trap energy depends on the annealing apparatus, improvement of the annealing apparatus is also studied. However, a furnace apparatus conventionally used takes a long time to crystallize and is not suitable for a display element in which the glass substrate 1 is used because it uses a high temperature. The excimer laser annealing method is mainly studied.
최근, 트랩에너지 상태밀도를 감소시키는 연구는 비정질실리콘막(3)과 게이트실리콘 산화막(6)을 동시에 형성하여 레이저 어닐링 처리하는 방법이 일반적으로 사용되고 있다. 예를 들어, 비정질실리콘막(3)을 형성한 후, 별도로 산소를 박막 내로 임플란트 (implant)시킨다. 그 후, 레이저로 어닐링하여 비정질실리콘막(3)을 폴리실리콘막(4)으로 결정화시키고, 상기 임프란트에 의해 비정질실리콘박막 내로 주입된 산소는 비정질실리콘 원자와 반응하여 게이트 실리콘산화막(6)을 형성함으로써, 계면(5)에서 전하를 트랩하는 트랩에너지의 상태밀도를 감소시키고 있다.In recent years, in the study of reducing the trap energy state density, a method of forming an amorphous silicon film 3 and a gate silicon oxide film 6 simultaneously and performing laser annealing is generally used. For example, after the amorphous silicon film 3 is formed, oxygen is separately implanted into the thin film. Thereafter, annealing with a laser crystallizes the amorphous silicon film 3 into the polysilicon film 4, and oxygen injected into the amorphous silicon thin film by the implant reacts with the amorphous silicon atoms to form the gate silicon oxide film 6 This reduces the density of states of trap energy trapping charges at the interface 5.
그러나, 상기와 같은 산소이온 임프란트 방법은 산소이온을 화학적인 반응 없이 박막 내부까지 물리적인 방법으로 강제로 침투시키는 방법이기 때문에, 원자반경이 큰 산소와 같은 원소는 비정질실리콘막 박막의 격자 (원자 배열)에 많은 손상을 주어 목적하는 바와 달리 산소가 일종의 불순물로 작용하는 문제가 있다.However, since the oxygen ion implant method is a method of forcing oxygen ion into the thin film physically without chemical reaction, the element such as oxygen having a large atomic radius is a lattice (atomic arrangement) of the amorphous silicon film thin film. ), There is a problem that oxygen acts as a kind of impurity.
상기의 문제점을 해결하기 위해 본 발명은 박막트랜지스터의 제조 방법에 있어서, 게이트실리콘 산화막과 폴리실리콘막 계면에서 전하를 트랩하는 계면의 불순물이나 부정합을 감소시키는 데 그 목적이 있다.In order to solve the above problems, an object of the present invention is to reduce impurities or mismatches at an interface trapping charge at an interface between a gate silicon oxide film and a polysilicon film in a method of manufacturing a thin film transistor.
상기와 같은 본 발명의 목적을 달성하기 위해 본 발명은 박막트랜지스터 제조 방법에 있어서, 기판 상에 비정질실리콘막을 증착하는 단계와, 비정질실리콘막의 상부 계면에 비정질실리콘 산화막을 형성하도록 산소이온을 흡착하는 단계와, 비정질실리콘막을 폴리실리콘막으로 결정화하고, 비정질실리콘 산화막을 일정한 당량비를 가지는 실리콘산화막으로 변환하도록 하기 위하여 어닐링하는 단계를 포함하는 박막트랜지스터 제조방법 및 그 제조방법에 의해 제조된 박막트랜지스터를 제시하고 있다. In order to achieve the object of the present invention as described above, the present invention provides a method of manufacturing a thin film transistor, comprising depositing an amorphous silicon film on a substrate, and adsorbing oxygen ions to form an amorphous silicon oxide film on an upper interface of the amorphous silicon film. And annealing to crystallize the amorphous silicon film into a polysilicon film and convert the amorphous silicon oxide film into a silicon oxide film having a predetermined equivalent ratio, and a thin film transistor prepared by the method and a thin film transistor prepared by the method. have.
또한, 본 발명은 비정질실리콘 막에 산소이온을 흡착하는 단계는 플라즈마상태의 산소이온을 형성하여 흡착하는 것을 특징으로 하는 박막트랜지스터 제조방법 및 그 제조방법에 의해 제조된 박막트랜지스터를 제시하고 있다.In addition, the present invention proposes a thin film transistor manufacturing method and a thin film transistor prepared by the method for adsorbing oxygen ions to the amorphous silicon film to form and adsorb oxygen ions in the plasma state.
또한, 본 발명의 어닐링하는 단계는 산소이온이 흡착된 비정질실리콘막에 레이저를 가하는 방법을 특징으로 하는 박막트랜지스터 제조방법 및 그 제조방법에 의해 제조된 박막트랜지스터를 제시하고 있다.In addition, the annealing step of the present invention proposes a thin film transistor manufacturing method and a thin film transistor prepared by the manufacturing method, characterized in that the laser is applied to the amorphous silicon film adsorbed oxygen ions.
도 2는 본 발명에 관계하는 폴리실리콘 박막트랜지스터의 폴리실리콘막의 개략 공정도를 나타낸 것으로 본 발명의 구성과 작용을 개략적으로 설명하기 위하여 다른 구성요소는 생략한다.2 is a schematic process diagram of a polysilicon film of a polysilicon thin film transistor according to the present invention, and other components are omitted in order to schematically explain the structure and operation of the present invention.
도 2 (a) 내지 도 2 (d)에 도시된 바와 같이, 박막트랜지스터 내로 나트륨(Na)등 불순물의 침투를 방지하고, 유리기판(1)과 박막트랜지스터 막과의 응력(stress) 및 접착력을 향상시키기 위해 일종의 버퍼 층으로서 5000Å 두께의 제1 실리콘 산화막(10)이 유리기판(1) 상에 증착된다. 하지만, 제 1 실리콘 산화막(10)을 버퍼층으로 사용여부는 박막트랜지스터의 용도에 따라 다를 수 있기 때문에 임의적일 수 있다(도 2 (a)).As shown in Fig. 2 (a) to 2 (d), to prevent the infiltration of impurities such as sodium (Na) into the thin film transistor, and the stress and adhesion between the glass substrate 1 and the thin film transistor film In order to improve, a 5000 버퍼 thick first silicon oxide film 10 is deposited on the glass substrate 1 as a buffer layer. However, the use of the first silicon oxide film 10 as the buffer layer may be arbitrary because it may vary depending on the use of the thin film transistor (FIG. 2 (a)).
다음에, 제1 실리콘 산화막(10) 상에 500Å 두께의 비정질실리콘막 (11)을 증착한 후, 비정질실리콘막 (11) 표면에 산소유량을 조절하여 산소플라즈마를 한다. 이러한 플라즈마 처리를 통해 형성된 산소이온이 비정질실리콘막(11) 표면에 흡착되어 산소가 흡착된 비정질실리콘막(11)은 50Å 두께의 비정질실리콘 산화막(12, SiOx) 및 비정질실리콘막(11)의 구조로 형성된다. 즉, 50Å 두께의 비정질실리콘 산화막(12)은 표면에서 약한 결합을 하고 있기 때문에, 실리콘원자와 산소원자가 일정한 당량비로 결합하지 못하여 비정질실리콘막(11)의 표면에서 무질서하게 배열된 아몰퍼스 상태가 된다 (도 2 (b), 도 2 (c)).Next, after depositing an amorphous silicon film 11 having a thickness of 500 kPa on the first silicon oxide film 10, oxygen flow rate is controlled on the surface of the amorphous silicon film 11 to perform oxygen plasma. Oxygen ions formed through the plasma treatment are adsorbed onto the surface of the amorphous silicon film 11, and the amorphous silicon film 11 in which oxygen is adsorbed has the structure of the amorphous silicon oxide film 12 (SiOx) 12 and the amorphous silicon film 11 having a thickness of 50 kHz. Is formed. That is, since the 50 Å thick amorphous silicon oxide film 12 is weakly bonded at the surface, silicon atoms and oxygen atoms are not bonded at a constant equivalent ratio, resulting in an amorphous state in which the amorphous silicon film 11 is randomly arranged on the surface of the amorphous silicon film 11 ( 2 (b) and 2 (c)).
또한, 레이저 어닐링으로 비정질실리콘 산화막(SiOx)/비정질실리콘막(a-Si) 구조는 실리콘 산화막(SiO2)/폴리실리콘막(p-Si) 구조로 재결합함과 동시에 재결정화 된다. 즉, 레이저의 열에너지에 의해 비정질실리콘 산화막(12) 내에 약하게 결합되어 있는 실리콘원자와 산소원자가 재배치되어 일정한 당량비를 가진 50Å 내지 100Å 두께의 제2 실리콘산화막(14)으로 변화된다. 또한, 비정질실리콘 막(11)은 어닐링 공정에 의해 폴리실리콘막(13)으로 변경되고, 어닐링할 때, 비정질실리콘 산화막(12)과 재결합함으로써, 상기 계면에서 발생하는 격자의 부정합에 따른 불순물 수를 감소시켜 전하를 트랩하는 트랩에너지의 상태밀도가 감소한다.In addition, the amorphous silicon oxide film (SiOx) / amorphous silicon film (a-Si) structure is recrystallized at the same time as the silicon oxide film (SiO 2 ) / polysilicon film (p-Si) structure by laser annealing. That is, silicon atoms and oxygen atoms that are weakly bound in the amorphous silicon oxide film 12 are rearranged by the thermal energy of the laser, and are changed to the second silicon oxide film 14 having a thickness of 50 kV to 100 kV having a constant equivalent ratio. In addition, the amorphous silicon film 11 is changed to the polysilicon film 13 by an annealing process, and when annealed, the amorphous silicon film 11 is recombined with the amorphous silicon oxide film 12 to thereby reduce the impurity number due to mismatch of the lattice generated at the interface. This reduces the density of states of trap energy that trap charges.
또한, 제2 실리콘 산화막(14)은 게이트실리콘 산화막의 사용할 수 있기 때문에, 박막트랜지스터 제작공정중 별도의 실리콘산화막 증착공정은 수반되지 않고, 박막트랜지스터의 제조공정 수는 감소된다. 그러나, 박막트랜지스터의 전기적 특성에 따라 게이트 절연막으로서 별도의 실리콘산화막을 증착할 수 있다(도 2 (c), 도 2 (d)).In addition, since the second silicon oxide film 14 can use a gate silicon oxide film, a separate silicon oxide film deposition process is not involved in the thin film transistor fabrication process, and the number of thin film transistor manufacturing processes is reduced. However, depending on the electrical characteristics of the thin film transistor, it is possible to deposit a separate silicon oxide film as a gate insulating film (Fig. 2 (c), Fig. 2 (d)).
또한, 어닐링처리할 때, 비정질실리콘 산화막/비정질실리콘막 구조이기 때문에, 캡핑(capping)효과에 의해 결정화되는 비정질실리콘막(11)은 비정질실리콘 산화막(12)로 인해 열에너지가 보온되어 결정입자(grain) 크기가 증대된다. 이 때문에, 제2 실리콘산화막(14)과 폴리실리콘막(13) 계면에서 전하를 트랩하는 트랩에너지의 상태밀도에 영향을 주는 결정입자 경계면 (grain boundary) 수가 감소한다. 즉, 작은 결정입자는 단위면적당 많은 결정입자 경계면 수를 가지지만, 큰 결정입자는 단위면적당 적은 결정입자 경계면의 수를 가지기 때문에, 결정입자 경계면 수가 감소되고, 전하를 트랩하는 트랩에너지 상태밀도는 감소된다 (도 2 (d)).In addition, when annealing, the amorphous silicon oxide film / amorphous silicon film structure, the amorphous silicon film 11 that is crystallized by the capping effect, the thermal energy is kept warm due to the amorphous silicon oxide film 12 to crystal grain (grain) ) The size is increased. For this reason, the number of grain boundaries that affect the state density of trap energy trapping charges at the interface between the second silicon oxide film 14 and the polysilicon film 13 is reduced. That is, small crystal grains have a large number of crystal grain boundaries per unit area, but large crystal grains have a small number of crystal grain boundaries per unit area, so that the number of crystal grain boundaries decreases, and the trap energy state density trapping charge decreases. (FIG. 2 (d)).
이하, 본 발명에 따른 실시예를 구성과 작용을 첨부된 도면을 참조하여 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 3a 내지 도 3h는 본 발명을 적용한 박막트랜지스터의 제 1 실시예를 설명하기 위한 도면으로 코플라나(Coplanar) 구조를 채용한 폴리실리콘막 박막트랜지스터의 제조공정도를 나타낸 것이다.3A to 3H are views for explaining a first embodiment of a thin film transistor to which the present invention is applied, and show a manufacturing process diagram of a polysilicon film thin film transistor having a coplanar structure.
절연기판인 유리기판(1:glass)에 500Å 두께의 비정질실리콘막 (50)을 증착한 후, 포토리소그래피 공정에 의해 비정질산화막을 활성층으로 패턴닝한다. 패턴된 비정질실리콘막 (50) 표면에 산소유량을 조절하여 산소플라즈마를 한다. 이 플라즈마상태의 산소이온은 두 전극 사이에 위치한 산소기체에 전압을 걸어 형성한다. 이러한 플라즈마 처리를 통해 형성된 산소이온이 비정질실리콘막(50) 표면에 흡착되어 산소가 흡착된 비정질실리콘막(50)은 50Å 두께의 비정질실리콘 산화막(SiOx) 및 비정질실리콘막의 구조로 형성된다. 즉, 50Å 두께의 비정질실리콘 산화막은 표면에서 약한 결합을 하고 있기 때문에, 실리콘원자와 산소원자가 일정한 당량비로 결합하지 못하여 비정질실리콘막의 표면에서 무질서하게 배열된 아몰퍼스 상태가 된다 (도 3a).After depositing an amorphous silicon film 50 having a thickness of 500 에 on a glass substrate (1: glass), which is an insulating substrate, the amorphous oxide film is patterned into an active layer by a photolithography process. Oxygen plasma is performed by adjusting the oxygen flow rate on the surface of the patterned amorphous silicon film 50. Oxygen ions in the plasma state are formed by applying a voltage to an oxygen gas located between two electrodes. Oxygen ions formed through the plasma treatment are adsorbed onto the surface of the amorphous silicon film 50, and the amorphous silicon film 50 to which oxygen is adsorbed is formed in a structure of an amorphous silicon oxide film (SiOx) and an amorphous silicon film having a thickness of 50 kHz. That is, since the 50 Å thick amorphous silicon oxide film is weakly bonded at the surface, silicon atoms and oxygen atoms are not bonded at a constant equivalent ratio, resulting in an amorphous state in which the amorphous silicon film is randomly arranged (FIG. 3A).
또한, 레이저 어닐링으로 비정질실리콘 산화막(SiOx)/비정질실리콘막(a-Si) 구조는 실리콘 산화막(SiO2)/폴리실리콘막(p-Si) 구조로 재결합함과 동시에 재결정화 된다. 즉, 레이저의 열에너지에 의해 비정질실리콘 산화막(51) 내에 약하게 결합되어 있는 실리콘원자와 산소원자가 재배치되어 일정한 당량비를 가진 50Å 내지 100Å 두께의 제2 실리콘산화막(52)으로 변화된다. 또한, 비정질실리콘 막(50)은 어닐링 공정에 의해 폴리실리콘막(53)으로 변경되고, 어닐링할 때, 비정질실리콘 산화막(51)과 재결합함으로써, 상기 계면에서 발생하는 격자의 부정합에 따른 불순물 수를 감소시켜 전하를 트랩하는 트랩에너지의 상태밀도가 감소한다.In addition, the amorphous silicon oxide film (SiOx) / amorphous silicon film (a-Si) structure is recrystallized at the same time as the silicon oxide film (SiO 2 ) / polysilicon film (p-Si) structure by laser annealing. That is, silicon atoms and oxygen atoms that are weakly bound in the amorphous silicon oxide film 51 are rearranged by the thermal energy of the laser to be changed to the second silicon oxide film 52 having a thickness of 50 to 100 kHz with a constant equivalent ratio. In addition, the amorphous silicon film 50 is changed to the polysilicon film 53 by an annealing process, and when annealed, the amorphous silicon film 50 is recombined with the amorphous silicon oxide film 51 to thereby reduce the impurity number due to the mismatch of the lattice generated at the interface. This reduces the density of states of trap energy that trap charges.
또한, 제2 실리콘 산화막(52)은 게이트실리콘 산화막의 사용할 수 있기 때문에, 박막트랜지스터 제작공정중 별도의 실리콘산화막 증착공정은 수반되지 않고, 박막트랜지스터의 제조공정 수는 감소된다. 그러나, 박막트랜지스터의 전기적 특성에 따라 게이트 절연막으로서 별도의 실리콘산화막을 증착할 수 있다.In addition, since the second silicon oxide film 52 can use a gate silicon oxide film, a separate silicon oxide film deposition process is not involved in the thin film transistor manufacturing process, and the number of thin film transistor manufacturing processes is reduced. However, according to the electrical characteristics of the thin film transistor, a separate silicon oxide film may be deposited as the gate insulating film.
또한, 어닐링처리할 때, 비정질실리콘 산화막/비정질실리콘막 구조이기 때문에, 캡핑(capping)효과에 의해 결정화되는 비정질실리콘막(50)은 비정질실리콘 산화막(51)로 인해 열에너지가 보온되어 결정입자(grain) 크기가 증대된다. 이 때문에, 게이트 실리콘산화막과 폴리실리콘막 계면에서 전하를 트랩하는 트랩에너지의 상태밀도에 영향을 주는 결정입자 경계면 (grain boundary) 수가 감소한다. 즉, 작은 결정입자는 단위면적당 많은 결정입자 경계면 수를 가지지만, 큰 결정입자는 단위면적당 적은 결정입자 경계면의 수를 가지기 때문에, 결정입자 경계면 수가 감소되고, 전하를 트랩하는 트랩에너지 상태밀도는 감소된다 (도 3b, 도3c).In addition, when annealing, the amorphous silicon oxide film / amorphous silicon film structure, the amorphous silicon film 50 that is crystallized by the capping effect, the thermal energy is kept warm due to the amorphous silicon oxide film 51 to crystal grains (grain ) The size is increased. For this reason, the number of grain boundaries affecting the density of states of trap energy trapping charges at the gate silicon oxide film and the polysilicon film interface is reduced. That is, small crystal grains have a large number of crystal grain boundaries per unit area, but large crystal grains have a small number of crystal grain boundaries per unit area, so that the number of crystal grain boundaries decreases, and the trap energy state density trapping charge decreases. 3B and 3C.
이 후, 제2 실리콘 산화막(52)위에 500Å 두께의 몰리텅스텐과 3000Å 두께의 알루미늄을 사용하여 금속도전층(54)을 증착한다. 또한, 게이트 전극(55)을 패턴닝하기 위해 금속도전층을 사진식각한다. 게이트 전극(55)은 이중층으로 할 수 있고, 단일층으로 크롬을 사용할 수도 있다. 따라서, 알루미늄층과 몰리텅스텐층이외에 적절한 도전물질을 사용할 수 있다.Thereafter, on the second silicon oxide film 52, a metal conductive layer 54 is deposited using molybdenum having a thickness of 500 mW and aluminum having a thickness of 3000 mW. In addition, the metal conductive layer is photo-etched to pattern the gate electrode 55. The gate electrode 55 can be a double layer, or chromium can be used as a single layer. Therefore, a suitable conductive material can be used in addition to the aluminum layer and the molybdenum layer.
또한, 실리콘 산화막(SiO2)/폴리실리콘막(p-Si) 구조의 실리콘 산화막을 사진식각하여 상기 제2 실리콘 산화막(52)은 게이트 실리콘산화막으로 패턴닝된다.In addition, a silicon oxide film having a silicon oxide film (SiO 2 ) / polysilicon film (p-Si) structure is photo-etched to pattern the second silicon oxide film 52 as a gate silicon oxide film.
다음에, 기판 전면에 불순물 도핑공정을 진행하여 게이트 전극이 블로킹하지 않는 패턴된 폴리실리콘(53) 부분에 소스 영역(56S)과 드레인 영역(56D)이 형성된다. 또, 불순물은 n형 또는 p형 박막트랜지스터 형성할 것인지에 따라 다르게 도핑할 수 있다(도 3c, 도 3d).Next, an impurity doping process is performed on the entire surface of the substrate to form source and drain regions 56S and 56D on portions of the patterned polysilicon 53 where the gate electrodes are not blocked. Also, impurities may be doped differently depending on whether an n-type or p-type thin film transistor is to be formed (FIGS. 3C and 3D).
또한, 제 3 실리콘 산화막(57)을 증착하고 소스 영역(56S)과 드레인 영역(56D)에 소스 영역 콘택홀(58)과 드레인 영역 콘택홀(59)을 형성하여 소스 영역(56S) 및 드레인 영역(56D)과 게이트 전극(55)을 격리한다(도 3e).Further, the third silicon oxide film 57 is deposited and the source region contact hole 58 and the drain region contact hole 59 are formed in the source region 56S and the drain region 56D to form the source region 56S and the drain region. 56D and the gate electrode 55 are isolated (FIG. 3E).
다음에, 소오스/드레인 배선의 단선을 방지하고 낮은 저항을 가질수 있는 이중층의 금속막을 증착할 수 있다. 즉, 알루미늄층을 3000Å 두께로 증착하고 몰리브덴층을 500Å 두께로 증착한 후, 이들 금속을 동시에 식각하거나, 노출된 기판전면에 알루미늄층을 연속적으로 증착한 후, 식각하고, 다시 그 전면을 덮는 몰리브덴층을 증착하여 식각함으로써, 이중층의 구조를 가지는 상기 소오스/드레인 배선(60S/60D)을 패턴닝한다. 상기 소오스/드레인 배선(60S/60D)은 적어도 단일층 이상의 구조로 할 수 있으며, 알루미늄층과 몰리브덴층이외에 적절한 도전물질을 사용할 수 있다 (도 3f).Next, a double layer metal film can be deposited which can prevent disconnection of the source / drain wiring and can have a low resistance. That is, the aluminum layer is deposited to 3000 Å thickness and the molybdenum layer is deposited to 500 Å thickness, and these metals are simultaneously etched, or the aluminum layer is continuously deposited on the exposed front surface of the substrate, and then molybdenum is covered again. By depositing and etching a layer, the source / drain interconnects 60S / 60D having a double layer structure are patterned. The source / drain interconnects 60S / 60D may have a structure of at least a single layer or more, and an appropriate conductive material may be used in addition to the aluminum layer and the molybdenum layer (FIG. 3F).
또한, 노출된 전면을 덮는 제 4 실리콘 산화막(61)을 증착한 후, 제 4 실리콘 산화막(61)을 사진 식각하여 드레인전극(62)을 노출시키는 콘택홀을 형성한다 (도 3g).In addition, after the fourth silicon oxide layer 61 covering the exposed entire surface is deposited, the fourth silicon oxide layer 61 is photo-etched to form a contact hole exposing the drain electrode 62 (FIG. 3G).
다음에, 노출된 전면을 덮는 투명도전층(ITO)을 증착한 후, 투명도전층을 사진식각하여 드레인 배선(60D)에 연결되는 화소전극(63)을 형성할 수 있다(도 3h).Next, after depositing the transparent conductive layer (ITO) covering the exposed entire surface, the transparent conductive layer may be photo-etched to form the pixel electrode 63 connected to the drain wiring 60D (FIG. 3H).
도 4a 내지 도 4e는 본 발명을 적용한 박막트랜지스터의 제 2실시예로서 BBC(Buried Bus Coplanar) 구조의 박막트랜지스터 제조공정을 나타낸 것이다.4A to 4E illustrate a process of fabricating a thin film transistor having a BBC (Buried Bus Coplanar) structure as a second embodiment of the thin film transistor to which the present invention is applied.
절연기판인 유리기판(1:glass)에 소오스 전극(100S)과 드레인 전극(100D)을 포함하는 소오스/드레인 배선을 패턴닝한다. 또한, 소오스/드레인 배선의 단선을 방지하고 낮은 저항을 가질수 있는 이중층을 증착할 수 있다. 즉, 제 1실시예에서는 노출된 기판 전면에 알루미늄층을 3000Å 두께로 증착하고 몰리브덴층을 500Å 두께로 증착한 후, 이들 금속을 동시에 식각하거나, 노출된 기판전면에 알루미늄층을 연속적으로 증착한 후, 식각하고, 다시 그 전면을 덮는 몰리브덴층을 증착하여 식각함으로써, 이중층의 구조를 가지는 상기 소오스/드레인 배선(100S/100D)을 패턴닝한다. 상기 소오스/드레인 배선(100S/100D)은 적어도 단일층 이상의 구조로 할 수 있으며, 알루미늄층과 몰리브덴층이외에 적절한 도전물질을 사용할 수 있다.The source / drain wirings including the source electrode 100S and the drain electrode 100D are patterned on a glass substrate (1), which is an insulating substrate. In addition, it is possible to deposit a double layer which can prevent disconnection of the source / drain wiring and can have a low resistance. That is, in the first embodiment, an aluminum layer is deposited to a thickness of 3000 kPa on the entire surface of the exposed substrate, and a molybdenum layer is deposited to a thickness of 500 kPa, and these metals are simultaneously etched or the aluminum layer is continuously deposited on the entire surface of the exposed substrate. After etching, the molybdenum layer covering the entire surface is deposited and etched to pattern the source / drain wiring 100S / 100D having a double layer structure. The source / drain interconnection 100S / 100D may have a structure of at least a single layer or more, and an appropriate conductive material may be used in addition to the aluminum layer and the molybdenum layer.
또한, 박막트랜지스터 내로 나트륨(Na)등 불순물의 침투를 방지하고, 유리기판(1)과 박막트랜지스터 막과의 응력(stress) 및 접착력을 향상시키기 위해 일종의 버퍼 층으로서 5000Å 두께의 제1 실리콘 산화막(101)이 유리기판(1) 상에 증착된다. 하지만, 제 1 실리콘 산화막(101)을 버퍼층으로 사용여부는 박막트랜지스터의 용도에 따라 다를 수 있기 때문에 임의적일 수 있다.In addition, in order to prevent penetration of impurities such as sodium (Na) into the thin film transistor and to improve stress and adhesion between the glass substrate 1 and the thin film transistor film, a first silicon oxide film having a thickness of 5000 Å as a buffer layer is used. 101 is deposited on the glass substrate 1. However, the use of the first silicon oxide film 101 as a buffer layer may be arbitrary because it may vary depending on the use of the thin film transistor.
다음에, 제1 실리콘 산화막(101) 상에 500Å 두께의 비정질실리콘막 (102)을 증착한 후, 비정질실리콘막 (102) 표면에 산소유량을 조절하여 산소플라즈마를 한다. 이러한 플라즈마 처리를 통해 형성된 산소이온이 비정질실리콘막(102) 표면에 흡착되어 산소가 흡착된 비정질실리콘막(102)은 50Å 두께의 비정질실리콘 산화막(104, SiOx) 및 비정질실리콘막의 구조로 형성된다. 즉, 50Å 두께의 비정질실리콘 산화막(104)은 표면에서 약한 결합을 하고 있기 때문에, 실리콘원자와 산소원자가 일정한 당량비로 결합하지 못하여 비정질실리콘막의 표면에서 무질서하게 배열된 아몰퍼스 상태가 된다 (도 4a, 도 4b).Next, after depositing an amorphous silicon film 102 having a thickness of 500 kPa on the first silicon oxide film 101, oxygen flow rate is controlled on the surface of the amorphous silicon film 102 to produce an oxygen plasma. Oxygen ions formed through the plasma treatment are adsorbed onto the surface of the amorphous silicon film 102, and the amorphous silicon film 102 on which oxygen is adsorbed is formed in the structure of the amorphous silicon oxide film 104 (SiOx) 104 and the amorphous silicon film having a thickness of 50 kHz. That is, since the 50-nm-thick amorphous silicon oxide film 104 is weakly bonded at the surface, silicon atoms and oxygen atoms are not bonded at a constant equivalent ratio, resulting in an amorphous state in which the amorphous silicon film is randomly arranged on the surface of the amorphous silicon film (Fig. 4A, Fig. 4). 4b).
또한, 레이저 어닐링으로 비정질실리콘 산화막(SiOx)/비정질실리콘막(a-Si) 구조는 실리콘 산화막(SiO2)/폴리실리콘막(p-Si) 구조로 재결합함과 동시에 재결정화 된다. 즉, 레이저의 열에너지에 의해 비정질실리콘 산화막(104) 내에 약하게 결합되어 있는 실리콘원자와 산소원자가 재배치되어 일정한 당량비를 가진 50Å 내지 100Å 두께의 제2 실리콘산화막(105)으로 변화된다. 또한, 비정질실리콘 막(102)은 어닐링 공정에 의해 폴리실리콘막(103)으로 변경되고, 어닐링할 때, 비정질실리콘 산화막(104)과 재결합함으로써, 상기 계면에서 발생하는 격자의 부정합에 따른 불순물 수를 감소시켜 전하를 트랩하는 트랩에너지의 상태밀도가 감소한다.In addition, the amorphous silicon oxide film (SiOx) / amorphous silicon film (a-Si) structure is recrystallized at the same time as the silicon oxide film (SiO 2 ) / polysilicon film (p-Si) structure by laser annealing. That is, silicon atoms and oxygen atoms that are weakly bound in the amorphous silicon oxide film 104 are rearranged by the thermal energy of the laser to be changed to the second silicon oxide film 105 having a thickness of 50 to 100 kHz with a constant equivalent ratio. In addition, the amorphous silicon film 102 is changed to the polysilicon film 103 by an annealing process, and when annealed, the amorphous silicon film 102 is recombined with the amorphous silicon oxide film 104 to thereby reduce the impurity number due to the mismatch of the lattice generated at the interface. This reduces the density of states of trap energy that trap charges.
또한, 제2 실리콘 산화막(105)은 게이트실리콘 산화막의 사용할 수 있기 때문에, 박막트랜지스터 제작공정중 별도의 실리콘산화막 증착공정은 수반되지 않고, 박막트랜지스터의 제조공정 수는 감소된다. 그러나, 박막트랜지스터의 전기적 특성에 따라 게이트 절연막으로서 별도의 실리콘산화막을 증착할 수 있다.In addition, since the second silicon oxide film 105 can use a gate silicon oxide film, a separate silicon oxide film deposition process is not involved in the thin film transistor fabrication process, and the number of thin film transistor manufacturing processes is reduced. However, according to the electrical characteristics of the thin film transistor, a separate silicon oxide film may be deposited as the gate insulating film.
또한, 어닐링처리할 때, 비정질실리콘 산화막/비정질실리콘막 구조이기 때문에, 캡핑(capping)효과에 의해 결정화되는 비정질실리콘막(102)은 비정질실리콘 산화막(104)로 인해 열에너지가 보온되어 결정입자(grain) 크기가 증대된다. 이 때문에, 게이트 실리콘산화막과 폴리실리콘막 계면에서 전하를 트랩하는 트랩에너지의 상태밀도에 영향을 주는 결정입자 경계면 (grain boundary) 수가 감소한다. 즉, 작은 결정입자는 단위면적당 많은 결정입자 경계면 수를 가지지만, 큰 결정입자는 단위면적당 적은 결정입자 경계면의 수를 가지기 때문에, 결정입자 경계면 수가 감소되고, 전하를 트랩하는 트랩에너지 상태밀도는 감소된다 (도 4b).In addition, when annealing, the amorphous silicon oxide film / amorphous silicon film structure, the amorphous silicon film 102 that is crystallized by the capping effect, the thermal energy is kept warm due to the amorphous silicon oxide film 104 to crystal grain (grain) ) The size is increased. For this reason, the number of grain boundaries affecting the density of states of trap energy trapping charges at the gate silicon oxide film and the polysilicon film interface is reduced. That is, small crystal grains have a large number of crystal grain boundaries per unit area, but large crystal grains have a small number of crystal grain boundaries per unit area, so that the number of crystal grain boundaries decreases, and the trap energy state density trapping charge decreases. (FIG. 4B).
이 후, 제2 실리콘 산화막(105)위에 500Å 두께의 몰리텅스텐과 3000Å 두께의 알루미늄을 사용하여 금속도전층을 증착한다. 또한, 게이트 전극(106)을 패턴닝하기 위해 금속도전층을 사진식각한다. 게이트 전극(106)은 이중층으로 할 수 있고, 단일층으로 크롬을 사용할 수도 있다. 따라서, 알루미늄층과 몰리텅스텐층이외에 적절한 도전물질을 사용할 수 있다.Subsequently, a metal conductive layer is deposited on the second silicon oxide film 105 by using 500 μm thick molten tungsten and 3000 μm thick aluminum. In addition, the metal conductive layer is photo-etched to pattern the gate electrode 106. The gate electrode 106 can be a double layer, and chromium can be used as a single layer. Therefore, a suitable conductive material can be used in addition to the aluminum layer and the molybdenum layer.
또한, 실리콘 산화막(SiO2)/폴리실리콘막(p-Si) 구조의 실리콘 산화막을 사진식각하여 상기 제2 실리콘 산화막(105)은 게이트 실리콘산화막으로 패턴닝된다. 다음에, 결정화된 실리콘층을 사진식각하여 제 1 실리콘 산화막(101) 상에 활성층(103)이 형성된다. 그러나, 비정질실리콘 산화막 및 비정질실리콘막을 먼저 박막트랜지스터의 활성층으로 리소그래피한 후에 어닐링 단계를 실시해도 좋다.Further, the silicon oxide film having a silicon oxide film (SiO 2 ) / polysilicon film (p-Si) structure is photo-etched to pattern the second silicon oxide film 105 into a gate silicon oxide film. Next, an active layer 103 is formed on the first silicon oxide film 101 by photolithography of the crystallized silicon layer. However, the amorphous silicon oxide film and the amorphous silicon film may be first lithography with the active layer of the thin film transistor, followed by the annealing step.
다음에, 기판 전면에 불순물 도핑공정을 진행하여 게이트 전극이 블로킹하지 않는 활성층(103) 부분에 소스 전극(103S)과 드레인 영역(103D)이 형성된다. 또, 불순물은 n형 또는 p형 박막트랜지스터 형성할 것인지에 따라 다르게 도핑할 수 있다 (도 4c).Next, an impurity doping process is performed on the entire surface of the substrate, whereby the source electrode 103S and the drain region 103D are formed in the portion of the active layer 103 where the gate electrode does not block. Also, impurities may be doped differently depending on whether to form an n-type or p-type thin film transistor (FIG. 4C).
또한, 노출된 전면을 덮는 제 3 실리콘 산화막(106)을 증착한 후, 제 3 실리콘 산화막(107)과 제 1 실리콘 산화막(101)을 사진 식각하여 소오스전극(108), 소오스 영역(109), 드레인 전극(110) 및 드레인 영역(111)을 노출시키는 콘택홀을 형성한다 (도 4d).After the deposition of the third silicon oxide film 106 covering the exposed entire surface, the third silicon oxide film 107 and the first silicon oxide film 101 are photo-etched to obtain a source electrode 108, a source region 109, A contact hole exposing the drain electrode 110 and the drain region 111 is formed (FIG. 4D).
다음에, 노출된 전면을 덮는 투명도전층(ITO)을 증착한 후, 투명도전층을 사진식각하여 소오스전극과 소오스 영역을 연결하는 제1 연결배선(112)과 드레인전극과 드레인 영역을 연결하는 제2 연결배선(113)을 패턴닝한다. 이 때, 제 1 연결배선(112)과 제 2 연결배선(113)은 박막트랜지스터를 전기적으로 연결하는 연결배선으로 사용할 수 있다. 또한, 제 2 연결배선(113)은 액정표시장치에서 드레인 전극에 연결되는 화소전극을 적용할 수 있다. 또한, 제 1연결배선(112)과 제 2 연결배선(113)은 투명도전물질이외에 다른 종류의 도전물질로 형성할 수 있다 (도4e).Next, after depositing the transparent conductive layer (ITO) covering the exposed front surface, the first conductive wiring 112 connecting the source electrode and the source region by photo-etching the transparent conductive layer and the second connecting the drain electrode and the drain region The connection wiring 113 is patterned. In this case, the first connection line 112 and the second connection line 113 may be used as a connection line for electrically connecting the thin film transistor. In addition, the second connection wiring 113 may apply a pixel electrode connected to the drain electrode in the liquid crystal display. In addition, the first connection wire 112 and the second connection wire 113 may be formed of another kind of conductive material in addition to the transparent conductive material (FIG. 4E).
상기한 바와 같이, 본 발명은 기판 상에 비정질실리콘막을 증착한 후, 비정질실리콘막 표면에 산소플라즈마를 실시하여 산소이온을 흡착시킴으로써, 어닐링 후에 폴리실리콘막과 실리콘산화막 계면에서 격자의 부정합에 의해 발생하여 전하를 트랩하는 트랩에너지의 상태밀도를 감소시킨다. 또한, 비정질실리콘막 증착 중에 산소플라즈마 처리를 하는 연속공정함으로써, 표면이 오염되지 않아 불순물에 의해 형성되는 전하를 트랩하는 트랩에너지의 상태밀도도 감소시킨다.As described above, according to the present invention, an amorphous silicon film is deposited on a substrate, followed by oxygen plasma adsorption on the surface of the amorphous silicon film, thereby adsorbing oxygen ions, which is caused by lattice mismatch at the interface between the polysilicon film and the silicon oxide film after annealing. This reduces the density of states of trap energy trapping charge. In addition, by performing a continuous process of performing oxygen plasma treatment during the deposition of the amorphous silicon film, the surface density is not contaminated and the state density of trap energy trapping charges formed by impurities is also reduced.
또한, 비정질실리콘막의 산소흡착에 의해 형성된 비정질실리콘 산화막(SiOx)/비정질실리콘막(a-Si) 구조로 어닐링처리를 하면, 캡핑(capping)효과에 의해 폴리실리콘 결정입자(grain) 크기가 증대되기 때문에, 게이트 실리콘 산화막과 폴리실리콘막 계면에서 폴리실리콘 결정입자 경계면 (grain boundary) 수가 감소되는 효과가 있다.In addition, when annealing the amorphous silicon oxide film (SiOx) / amorphous silicon film (a-Si) structure formed by oxygen adsorption of the amorphous silicon film, the polysilicon grain size is increased by the capping effect. Therefore, there is an effect that the number of polysilicon grain boundaries is reduced at the interface of the gate silicon oxide film and the polysilicon film.
상기와 같은 방법에 의해 형성된 폴리실리콘막을 박막트랜지스터에 적용할 경우, 폴리실리콘막 박막트랜지스터의 오프상태에서 누설전류 증가나 온 전류의 감소를 억제할 수 있다. 또한, 문턱전압의 증가도 억제할 수 있어 폴리실리콘막 박막트랜지스터의 전기적특성을 개선하는 효과가 있다.When the polysilicon film formed by the above method is applied to the thin film transistor, it is possible to suppress an increase in leakage current or a decrease in on current in the off state of the polysilicon film thin film transistor. In addition, the increase in the threshold voltage can be suppressed, thereby improving the electrical characteristics of the polysilicon thin film transistor.
도 1는 종래의 레이저어닐링 처리 방법에 의한 폴리실리콘막을 형성하는 공정의 개략도.1 is a schematic diagram of a step of forming a polysilicon film by a conventional laser annealing treatment method.
도 2는 본 발명의 레이저어닐링 처리 방법에 의한 폴리실리콘막을 형성하는 공정의 개략도.2 is a schematic view of a step of forming a polysilicon film by the laser annealing treatment method of the present invention.
도 3a 내지 도 3h는 본 발명에 관계하는 제1 실시예가 도시된 박막트랜지스터의 개략 단면도.3A to 3H are schematic cross-sectional views of a thin film transistor in which a first embodiment according to the present invention is shown;
도 4a 내지 도 4e는 본 발명에 관계하는 제2 실시예가 도시된 박막트랜지스터의 개략 단면도.4A to 4E are schematic cross-sectional views of a thin film transistor in which a second embodiment according to the present invention is shown;
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
1 : 기판 (Glass) 2 : 제 1 실리콘 산화막1: substrate 2: first silicon oxide film
50 : 비정질실리콘막 52 : 비정질실리콘 산화막50: amorphous silicon film 52: amorphous silicon oxide film
53 : 폴리실리콘막 54 : 게이트 금속층53 polysilicon film 54 gate metal layer
55 : 게이트 전극 60S, 60D : 소오스, 드레인 전극55 gate electrode 60S, 60D source, drain electrode
63 : 화소전극63: pixel electrode
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| KR20010098269A (en) * | 2000-04-29 | 2001-11-08 | 윤종용 | A Low Temperature Polycrystaline Silicon Type Thin Film Transistor and A Method of Forming It |
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| KR100231936B1 (en) * | 1994-12-20 | 1999-12-01 | 마찌다 가쯔히꼬 | Thin film transistor and manufacturing thereof |
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