KR100488490B1 - Power module for liquid crystal display - Google Patents

Abstract

The present invention relates to a power module for a liquid crystal display device capable of minimizing power consumption and reducing error components due to resistance.

A power module for a liquid crystal display of the present invention includes an input control unit for receiving a clock signal, a gate high voltage, and a control signal; An output control unit which receives a control signal, a driving voltage and a gate high voltage, and outputs a base potential when a low control signal is input; And a first resistor provided between the input controller and the output controller.

Description

Power module for liquid crystal display device {POWER MODULE FOR LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power module for a liquid crystal display device, and more particularly, to a power module for a liquid crystal display device capable of minimizing power consumption and reducing error components caused by resistance.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal. An active matrix liquid crystal display device in which switching elements are formed for each liquid crystal cell is suitable for displaying moving images. As a switching element used in an active matrix liquid crystal display device, a thin film transistor (hereinafter, referred to as TFT) is mainly used.

A gate driver and a data driver are used to drive the liquid crystal display. The gate driver sequentially supplies a gate high voltage VGH to the TFT to sequentially turn on the TFT. The data driver supplies a predetermined data voltage to the TFT when the TFT is turned on. The TFT adjusts the angle of the liquid crystal by the data voltage supplied from the data driver, so that a predetermined image is displayed on the panel. The gate driver and the data driver are operated by receiving the driving voltage VDD from the power module.

Meanwhile, the conventional power module generates a predetermined AC voltage by using the gate high voltage VGH and the driving voltage VDD, and supplies the generated AC voltage to the LCD.

1 is a circuit diagram showing a conventional power module.

Referring to FIG. 1, a conventional power module receives a gate high voltage VGH, a driving voltage VDD, a control signal CS, and a clock signal CLK, and outputs an AC voltage to an output line Vout as shown in FIG. 2. Will be supplied. The voltage value of the gate high voltage VGH is set between 18V and 25V. The voltage value of the driving voltage VDD is set at 6.5V to 10V.

The conventional power module has a first transistor (Q1) and a third resistor (R3) installed between the clock signal (CLK) and the base voltage source (GND), and between the first TR (Q1) and the gate high voltage (VGH). A first resistor R1 and a second resistor R2 connected to the second resistor; a sixth resistor R6 and a fifth TR Q5 provided between the clock signal CLK and the ground voltage source GND; VGH) and a fourth resistor R4, a fifth resistor R5, and a second TR Q2 connected between the base voltage source GND and a ninth provided between the fifth TR Q5 and the gate high voltage VGH. The output resistor Ro and the sixth TR Q6 provided between the resistor R9, the eighth resistor R8, the fourth TR Q4 and the third TR Q3, and the output terminal Vout and the driving voltage VDD. And a seventh resistor R7 provided between the sixth TR Q6 and the first resistor R1.

The control signal CS is supplied to the base terminal of the second TR Q2. The clock signal CLK is supplied to the base terminals of the first TR Q1 and the fifth TR Q5. The driving voltage VDD is supplied to the emitter terminal of the sixth TR Q6. The gate high voltage VGH is supplied to the collector terminal of the first TR Q1, the base terminal of the sixth TR Q6, and the emitter terminal of the third TR Q3.

The operation of the conventional power module will be described with reference to FIG. 2. First, when the row control signal CS is input, the driving voltage VDD is output to the output terminal Vout. In detail, the row control signal CS is supplied to the base terminal of the second TR Q2. When a low control signal is input to the second TR Q2, the second TR Q2 maintains a turn-off state.

When the second TR Q2 is turned off, the gate high voltage VGH is applied to the fourth resistor R4 to turn off the third TR Q3. In other words, the voltage applied to the fourth resistor R4 (the base terminal of the third TR Q3) and the voltage applied to the emitter terminal of the third TR Q3 become equal, so that the third TR Q3 is equal to. Turn off. When the third TR Q3 is turned off, no voltage is applied to the eighth resistor R8 and the ninth resistor R9, and accordingly, the fourth TR Q4 is turned off. As such, when the fourth TR Q4 is turned off, the gate high voltage VGH is not supplied to the output terminal Vout. In other words, when the low control signal CS is input, the gate high voltage VGH is not supplied to the output terminal Vout.

On the other hand, when the clock signal CLK is in the low state, the first TR Q1 is turned off. When the first TR Q1 is turned off, a predetermined voltage is applied to the first and seventh resistors R1 and R7. At this time, the sixth TR Q6 is turned on by the voltage difference between the voltage applied to the seventh resistor R7 and the driving voltage VDD. When the sixth TR Q6 is turned on, the driving voltage VDD is applied to the output resistance Ro. Therefore, the driving voltage VDD is supplied to the output terminal Vout.

In addition, when the clock signal CLK is high, the first TR Q1 is turned on. When the first TR Q1 is turned on, a predetermined voltage is applied to the first and second resistors R1 and R2. At this time, the sixth TR Q6 is turned on by the voltage applied to the second resistor R72. When the sixth TR Q6 is turned on, the driving voltage VDD is applied to the output resistance Ro. The driving voltage VDD is supplied to the output terminal Vout.

That is, the conventional power module supplies the driving voltage VDD to the output terminal Vout when the control signal CS is kept low regardless of the high or low state of the clock signal CLK.

The operation process when the high control signal CS and the low clock signal CLK are input will be described in detail. When the high control signal CS is input, the second TR Q2 is turned on. When the second TR Q2 is turned on, the gate high voltage VGH is divided and applied to the fourth resistor R4 and the fifth resistor R5. Accordingly, a predetermined voltage difference (over a threshold voltage) is generated between the voltage applied to the fourth resistor R4 and the voltage applied to the emitter of the third TR Q3, thereby turning on the third TR Q3. do.

On the other hand, when the low clock signal CLK is input, the fifth TR Q5 maintains the turn-off state. Accordingly, the gate high voltage VGH is applied to the emitters of the eighth resistor R8 and the fourth TR Q4, and accordingly, the fourth TR Q4 maintains the turn-off state. Therefore, the voltage of the driving voltage VDD is supplied to the output terminal Vout.

The operation process when the high control signal CS and the high clock signal CLK are input will be described in detail. When the high control signal CS is input, the second TR Q2 is turned on. When the second TR Q2 is turned on, the gate high voltage VGH is divided and applied to the fourth resistor R4 and the fifth resistor R5. Accordingly, a predetermined voltage difference (over a threshold voltage) is generated between the voltage applied to the fourth resistor R4 and the voltage applied to the emitter of the third TR Q3, thereby turning on the third TR Q3. do.

When the high clock signal CLK is input, the fifth TR Q5 is turned on. When the fifth TR Q5 is turned on, the gate high voltage VGH is divided and applied to the eighth resistor R8 and the ninth resistor R9. Therefore, the fourth TR Q4 is turned on by the voltage applied to the ninth resistor R9. When the fourth TR Q4 is turned on, the gate high voltage VGH is supplied to the output terminal Vout.

In the conventional power module, the voltage used to drive the liquid crystal display is an AC voltage output to the output terminal Vout when the control signal CS maintains a high state. However, in the conventional power module, when the control signal CS is kept low, that is, when the output of the output terminal Vout is not actually used to drive the liquid crystal display, the driving voltage VDD is output. Therefore, the conventional power module consumes a lot of power consumption.

In addition, the first resistor (R1), the second resistor (R2), the fourth resistor (R4), the fifth resistor (R5), the seventh resistor (R7), and the eighth resistor (R8) included in the conventional power module. ) And the ninth resistor (R9) is used as a voltage divider and the like affecting the operation of the power module. In other words, all of the resistors except the sixth resistor R6 and the third resistor R3 used as protection resistors affect the operation of the power module. Therefore, the conventional power module has an error of about 30% to 40% due to the resistances, and accordingly, the conventional power module is difficult to directly direct.

Accordingly, an object of the present invention is to provide a power module for a liquid crystal display device which can minimize power consumption and reduce error components caused by resistance.

In order to achieve the above object, a liquid crystal display power module of the present invention includes an input control unit for receiving a clock signal, a gate high voltage and a control signal; An output control unit which receives a control signal, a driving voltage and a gate high voltage, and outputs a base potential when a low control signal is input; And a first resistor provided between the input controller and the output controller.

The input control unit; A first transistor receiving a clock signal at its base terminal and being turned on when the clock signal is high; A second transistor receiving a control signal at its base terminal and having its emitter terminal connected to a ground potential and being turned on when the control signal is high; A second resistor connected between the emitter terminal of the first transistor and the collector terminal of the second transistor; A third resistor connected between the collector terminal of the first transistor and the gate high voltage; A clock signal is input to its base terminal, a gate high voltage is input to its collector terminal, and a third transistor having an emitter terminal connected to the ground potential is provided.

The output control unit; A fourth transistor having its base terminal connected to a collector terminal of the first transistor and an emitter terminal connected to a gate high voltage; A fifth transistor whose base terminal is connected to the collector terminal of the fourth transistor and the collector terminal is connected to the gate high voltage; A sixth transistor connected to the collector terminal of the third transistor and its base terminal via the first resistor, and to the collector terminal of the fifth transistor connected to the emitter terminal of the fifth transistor; A seventh transistor having its own emitter terminal connected to the emitter terminal of the sixth transistor, a collector terminal connected to a base potential, and a base terminal connected to a driving voltage; An eighth transistor in which the collector terminal is connected to the emitter terminal of the fifth transistor, the emitter terminal is connected to the ground potential, and the base terminal is connected to the gate high voltage; A ninth transistor connected to the base terminal of the eighth transistor, the emitter terminal connected to the base potential, and receiving a control signal from the base terminal to be turned on when the control signal is high; An output terminal connected to the collector terminal of the eighth transistor.

When the control signal is a low signal, the second transistor is turned off, the fourth transistor and the fifth transistor controlled by the second transistor are turned off so that the gate high voltage is not supplied to the output terminal, and the control signal is low. In the case of the foil, the ninth transistor is turned off, and the eighth transistor controlled by the ninth transistor is turned on to supply the ground potential to the output terminal.

When the control signal is supplied as a high signal and the clock signal is supplied as a high state, the first and second transistors are turned on, and the fourth and fifth transistors controlled by the first and second transistors are turned on. On, the gate high voltage is supplied to the output terminal.

When the control signal is supplied as the high signal and the clock signal is supplied in the low state, the sixth and seventh transistors are turned on to supply the voltage value of the driving voltage to the output terminal.

The input controller, the output controller and the first resistor are integrated.

And a delay resistor disposed between the collector terminal of the third transistor and the gate high voltage, and a delay capacitor disposed between the base terminal and the ground potential of the sixth transistor.

The delay time of the power module is set by adjusting the magnitude of the delay resistor and the capacitance of the delay capacitor.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 4.

3 is a circuit diagram illustrating a power module according to an embodiment of the present invention.

Referring to FIG. 3, a power module according to an embodiment of the present invention includes an input controller 14 and an output controller 12. A seventh resistor R7 is provided between the input control unit 14 and the output control unit 12. The resistance affecting the operation of the power module of the present invention is one of the seventh resistor (R7), the remaining resistors (R1 to R6, R8) is used as a protection resistor for protecting the TR.

Therefore, the power module including the input control unit 14 and the output control unit 12 of the present invention can be integrated. The portion that can be integrated in this manner will be referred to as an integration unit 10. A delay adjusting resistor RE and a capacitor CE are installed outside the integration unit 10. By adjusting the size of the delay adjusting resistor RE and the capacitance of the capacitor CE, the delay time of the power module can be adjusted as desired.

The gate high voltage VGH is input to the gate high input terminal 2. The gate high input terminal 2 is the collector terminal of the first TR Q1, the emitter terminal of the fourth TR Q4, the collector terminal of the fifth TR Q5, the base terminal of the eighth TR Q8, and the ninth TR Q9. Is electrically connected to the collector terminal of.

The clock signal CLK is input to the clock input terminal 4. The clock input terminal 4 is electrically connected to the base terminal of the first TR Q1 and the base terminal of the third TR Q3. The control signal CS is input to the control input terminal 6. The control input terminal 6 is electrically connected to the base terminal of the second TR Q2 and the base terminal of the ninth TR Q9. The driving voltage VDD is input to the driving input terminal 8. The driving input terminal 8 is electrically connected to the base terminal of the seventh TR Q7.

This operation of the power module of the present invention will be described in detail with reference to FIG.

First, an operation process when the row control signal CS and the row clock signal CLK are input will be described. The low control signal CS is input to the base terminal of the second TR Q2 via the second resistor R2 and to the base terminal of the ninth TR Q9 via the fourth resistor R4. The second TR Q2 and the ninth TR Q9 that have received the row control signal CS are turned off.

The low clock signal CLK is input to the base terminal of the first TR Q1 via the first resistor R1 and to the base terminal of the third TR Q3 via the third resistor R3. The first TR Q1 and the third TR Q3 receiving the low clock signal CLK are turned off. When the first TR Q1 is turned off, the gate high voltage VGH is applied to the sixth resistor R6. This gate high voltage VGH is input to the base terminal of the fourth TR Q4. Therefore, the fourth TR Q4, which receives the gate high voltage VGH at the emitter terminal, is turned off.

When the fourth TR Q4 is turned off, the fifth TR Q5 is turned off. The gate high voltage VGH is applied to the eighth resistor R8, and the gate high voltage VGH applied to the eighth resistor R8 is input to the base terminal of the eighth TR Q8. At this time, the eighth TR Q8 is turned on. When the eighth TR Q8 is turned on, the voltage of the ground voltage source GND is supplied to the output terminal Vout. On the other hand, the gate high voltage VGH is applied to the delay resistor RE and the seventh resistor R7 to turn on the sixth TR Q6. At this time, since the seventh TR Q7 is turned off, the voltage of the ground voltage source GND is supplied to the output terminal Vout.

That is, when the low control signal CS is input and the low clock signal CLK is input, the voltage of the base voltage source GND is supplied to the output terminal Vout.

Next, an operation process when the low control signal CS is input and the high clock signal CLK is input will be described. The low control signal CS is input to the base terminal of the second TR Q2 via the second resistor R2 and to the base terminal of the ninth TR Q9 via the fourth resistor R4. The second TR Q2 and the ninth TR Q9 that have received the row control signal CS are turned off.

The high clock signal CLK is input to the base terminal of the first TR Q1 via the first resistor R1 and to the base terminal of the third TR Q3 via the third resistor R3. The first TR Q1 and the third TR Q3 receiving the high clock signal CLK are turned on.

As described above, since the second TR Q2 remains turned off even when the first TR Q1 is turned on, the gate high voltage VGH is applied to the sixth resistor R6, and accordingly, the fourth TR Q4 is applied. Remains turned off.

When the fourth TR Q4 is turned off, the fifth TR Q5 is turned off. The gate high voltage VGH is applied to the eighth resistor R8, and the gate high voltage VGH applied to the eighth resistor R8 is input to the base terminal of the eighth TR Q8. At this time, the eighth TR Q8 is turned on. When the eighth TR Q8 is turned on, the voltage of the ground voltage source GND is supplied to the output terminal Vout. On the other hand, since the third TR Q3 is turned on, the gate high voltage VGH is supplied to the base voltage source GND via the delay resistor RE. Accordingly, the sixth TR Q6 is turned off, so that the voltage of the ground voltage source GND is supplied to the output terminal Vout.

That is, the power module according to the embodiment of the present invention always outputs the voltage of the base voltage source GND to the output terminal Vout when the row control signal CS is input. Accordingly, the power module according to the embodiment of the present invention can minimize the amount of power consumed when the row control signal CS is input.

Next, an operation process when the high control signal CS and the high clock signal CLK are input will be described.

The high control signal CS is input to the base terminal of the second TR Q2 via the second resistor R2 and to the base terminal of the ninth TR Q9 via the fourth resistor R4. . The second TR Q2 and the ninth TR Q9 that receive the high control signal CS are turned on.

The high clock signal CLK is input to the base terminal of the first TR Q1 via the first resistor R1 and to the base terminal of the third TR Q3 via the third resistor R3. The first TR Q1 and the third TR Q3 receiving the high clock signal CLK are turned on.

As such, when the first TR Q1 and the second TR Q2 are turned on, a predetermined voltage is applied to the fifth resistor R5, and the fourth TR Q4 is turned on. In other words, a voltage difference greater than or equal to a threshold voltage is generated between the emitter and the base terminal of the fourth TR Q4, and thus the fourth TR Q4 is turned on. When the fourth TR Q4 is turned on, the gate high voltage VGH is applied to the base terminal of the fifth TR Q5, and accordingly, the fifth TR Q5 is turned on. When the fifth TR Q5 is turned on, the gate high voltage VGH is supplied to the output terminal Vout.

On the other hand, when the third TR Q3 is turned on, the sixth TR Q6 is turned off. Similarly, when the ninth TR Q9 is turned on, the eighth TR Q8 is turned off. Therefore, the gate high voltage VGH is stably supplied to the output terminal Vout.

Next, an operation process when the high control signal CS and the low clock signal CLK are input will be described.

The high control signal CS is input to the base terminal of the second TR Q2 via the second resistor R2 and to the base terminal of the ninth TR Q9 via the fourth resistor R4. . The second TR Q2 and the ninth TR Q9 that receive the high control signal CS are turned on.

The low clock signal CLK is input to the base terminal of the first TR Q1 via the first resistor R1 and to the base terminal of the third TR Q3 via the third resistor R3. The first TR Q1 and the third TR Q3 receiving the low clock signal CLK are turned off.

When the first TR Q1 is turned off, the fourth TR Q4 and the fifth TR Q5 are turned off. When the ninth TR Q9 is turned on, the eighth TR Q8 is turned off. On the other hand, when the third TR Q3 is turned off, the sixth TR Q6 is turned on. When the sixth TR Q6 is turned on, the gate high voltage VGH supplied to the output terminal is supplied to the emitter terminal of the seventh TR Q7. Therefore, the seventh TR Q7 is turned on so that the gate high voltage VGH is lowered to the voltage of the driving voltage VDD.

In other words, the seventh TR Q7 is turned on by the voltage difference between the gate high voltage VGH supplied to the collector terminal and the driving voltage VDD supplied to its base terminal. At this time, the gate high voltage VGH is supplied to the base voltage source GND. Thereafter, when the voltage difference between the voltage of the gate high voltage VGH and the driving voltage VDD supplied to the collector terminal does not exceed the threshold voltage, the seventh TR Q7 is turned off. At this time, a voltage (approximately the voltage value of the driving voltage VDD) to which the threshold voltage is added to the voltage value of the driving voltage VDD is applied to the collector terminal of the seventh TR Q7. Therefore, the voltage value of the driving voltage VDD is supplied to the output terminal Vout. (Actually, the output terminal Vout shows the driving voltage VDD + Q7 (Vce; threshold voltage).)

In the power module according to the embodiment of the present invention, the resistance affecting the operation is the seventh resistor R7, and the remaining resistors R1 to R6 and R8 are used to protect the TRs. Therefore, in the present invention, the error component of the resistors can be minimized and thus integrated. In addition, the power module of the present invention outputs a base voltage when the control signal is low, thereby preventing waste of power.

As described above, according to the power module for a liquid crystal display device according to the present invention, error components due to resistance can be minimized, thereby ensuring reliability of operation. In addition, the power module of the present invention can be integrated. In addition, the power module of the present invention outputs a base voltage when the control signal is low, thereby preventing waste of power. In addition, in the present invention, the delay time of the power module may be set as desired by providing a resistor and a capacitor for a delay externally.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a circuit diagram showing a conventional power module.

FIG. 2 is a waveform diagram illustrating control signals input to the power module shown in FIG. 1 and output signals of the power module.

3 is a circuit diagram showing a power module according to an embodiment of the present invention.

4 is a waveform diagram illustrating control signals input to the power module shown in FIG. 3 and output signals of the power module;

<Description of Symbols for Main Parts of Drawings>

2: Gate High Input Terminal 4: Clock Input Terminal

6: control input terminal 8: drive input terminal

10: integration unit 12: output control unit

14: input control unit

Claims (9)

An input controller configured to receive a (correction) gate high voltage, a clock signal, and a control signal; And, The gate high voltage and the control signal input to the input controller and the driving voltage from the outside are input together, and when the control signal of the input controller is low, the base potential is always output regardless of the low and high of the clock signal. And an output control unit configured to output the driving voltage when the clock signal is low while the control signal of the input control unit is high. (Correction) The method of claim 1, The input control unit; A first transistor which receives the clock signal at its base terminal and is turned on when the clock signal is high; A second transistor receiving the control signal at its base terminal and having its emitter terminal connected to a ground potential and being turned on when the control signal is high; A second resistor connected between the emitter terminal of the first transistor and the collector terminal of the second transistor; A third resistor connected between the collector terminal of the first transistor and the gate high voltage; The clock signal is input to its base terminal, the gate high voltage is input to its collector terminal, and a first resistor is connected, and its emitter terminal includes a third transistor connected to a ground potential. Power module for a liquid crystal display device characterized in that. (Correction) The method of claim 2, The output control unit; A fourth transistor having its base terminal connected to the collector terminal of the first transistor and an emitter terminal connected to the gate high voltage; A fifth transistor having its base terminal connected to the collector terminal of the fourth transistor and a collector terminal connected to the gate high voltage; A sixth transistor through which the collector terminal of the third transistor and its base terminal are connected via the first resistor, and the collector terminal of the third transistor is connected to the emitter terminal of the fifth transistor; A seventh transistor having its own emitter terminal connected to the emitter terminal of the sixth transistor, a collector terminal connected to a base potential, and a base terminal connected to an external driving voltage; An eighth transistor having a collector terminal connected to an emitter terminal of the fifth transistor, an emitter terminal connected to a base potential, and a base terminal connected to the gate high voltage; A ninth transistor connected to a base terminal of the eighth transistor, an emitter terminal connected to a base potential, and receiving a control signal from a base terminal to be turned on when the control signal is high; And an output terminal connected to the collector terminal of the eighth transistor. The method of claim 3, wherein When the control signal is a low signal, the second transistor is turned off, and the fourth and fifth transistors controlled by the second transistor are turned off so that a gate high voltage is not supplied to the output terminal. The ninth transistor is turned off when the control signal is a low signal, and the eighth transistor controlled by the ninth transistor is turned on so that a ground potential is supplied to the output terminal. Power module. The method of claim 3, wherein The fourth and fifth transistors are turned on and controlled by the first and second transistors when the control signal is supplied as a high signal and the clock signal is supplied as a high state. The transistor is turned on so that the gate high voltage is supplied to the output terminal. The method of claim 3, wherein And the sixth and seventh transistors are turned on when the control signal is supplied as a high signal and the clock signal is supplied as a low state, thereby supplying a voltage value of a driving voltage to the output terminal. Power module for display device. 2. The power module of claim 1, wherein the output control unit outputs the gate high voltage when the clock signal is high while the control signal is high. The method of claim 3, wherein A delay resistor provided between the collector terminal of the third transistor and the gate high voltage; And a delay capacitor provided between the base terminal of the sixth transistor and the base potential. The method of claim 8, And controlling the magnitude of the delay resistor and the capacitance of the delay capacitor to set a delay time of the power module.