KR100484249B1 - Pipe latch Circuit for output data with high speed in Sychronous Memory device and Synchronous Memory device using the same - Google Patents

Abstract

The present invention provides a pipe latch circuit of a digital synchronous memory device capable of outputting data at high speed by simplifying an operation of prefetching and outputting data in a synchronous memory device. And a pipe latch circuit of a synchronous memory device for prefetching, storing and outputting second data, comprising: a storage unit having first and second latches; An input unit enabled by a pipe input enable signal to selectively store the first and second data in the first and second latches by a path selection signal generated each time an address is applied; And an output unit for outputting the first and second data stored in the storage unit in response to the first and second pipe output enable signals, respectively.

Description

Pipe latch circuit for output data with high speed in Sychronous Memory device and Synchronous Memory device using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous memory device, and more particularly, to efficiently perform multiplexing of pre-fetched 2-bit data during a read operation in a double data rate (DDR) synchronous memory device. The present invention relates to a pipe latch circuit of a synchronous memory device capable of outputting data, and a synchronous memory device using the same.

In general, a digital synchronous memory device is a conventional single data rate (SDR) synchronous memory device that outputs data only on the rising edge (Edge) of the clock (Clock), the data outputs on the rising and falling edge of the clock The memory device using the method.

Fig. 1 is a block diagram of a data output unit for outputting data in a conventional digital synchronous memory device.

Referring to FIG. 1, conventionally, a block structure for outputting data from a digital synchronous memory device includes a buffer 021 that receives an external clock CLK, buffers it, and outputs the buffer to an internal clock CLK_IN. Counter 0 (22) outputting pipe input enable signals (pin <0: n>) and various control signals (/ CS, / RAS, / CAS, / WE) are synchronized with the internal clock (CLK_IN). A buffer 12 for buffering, a decoder 12 for outputting a control signal cas_rd for detecting a read state by receiving and decoding an output signal of the buffer 1 11, and an address signal AN Buffer 2 (31) for receiving and buffering in synchronization with the clock (CLK_IN), latch 0 (32) for latching the output of the buffer (2 31) in response to the control signal cas_rd, and latch 1 for relatching it. And a plurality of path selection scenes to the pipe latch 50 using the output of the latch, enabled by a read command (33). The counter 1 34 which outputs (ian0 <0: n>) and the DLL 42 which generate the first and second delay lock clocks dllclk_r and dllclk_f to synchronize the output data to the external clock CLK. Counters 43 and 43 'that output a plurality of first and second enable signals pout_f <0: n> and pout_r <0: n> to output data from the pipe latch 50; It consists of a pipe latch 50 that receives the first and second data (even data, odd data) output from the cell block 60 and stores it and outputs the output data (dout_r, dout_f).

FIG. 2 is an internal circuit diagram of the pipe latch 50 shown in FIG.

Referring to FIG. 2, the pipe latch 50 may include first and second data output from the cell block 60 according to a pipe input enable signal (eg, pin <k>) output from the clock signal controller 20. (L1, L2) are input through the input unit 51 for receiving (even data, odd data) and the input unit 51 according to the path selection signal (for example, ian0 <k>) output from the counter 1 (34). The storage unit 52 which transfers and stores the data (even data, odd data) stored in the latches L3 and L4, and the data stored in the latches L3 and L4 of the storage unit 52 to the first and second. The output unit 53 outputs the first and second output data dout_r and dout_f according to the pipe output enable signal (for example, pout_r <k> and pout_f <k>).

Hereinafter, an operation of outputting data in a conventional digital memory device will be described with reference to FIGS. 1 and 2.

First, buffers 0 and 3 (21, 41) are devices for buffering the potential levels of the external clock signals CLK, / CLK to a CMOS level suitable for internal operation of the digital synchronous memory device. A device for buffering a plurality of control signals (/ CS, / RAS, / CAS, / WE) at a CMOS level suitable for internal operation of a digital synchronous memory device. In addition, the buffer 2 31 is a device for buffering the external input potential level of the address signal AN to a CMOS level suitable for the internal operation of the digital synchronous memory device and for synchronizing the internal clock signal CLK_IN.

Meanwhile, the decoder 12 is a device for decoding the buffered control signals / CS, / RAS, / CAS and / WE, and the control signal / CS at the rising edge timing of the external clock signal CLK. , / CAS) is at low level and the control signal (/ RAS, / WE) is at high level, when the lead command is input from this part, the internal control signal (cas_rd) and the read signal (read) are enabled. It is a device for letting.

The DLL 42 is a device for outputting delayed internal clock signals dllclk_r and dllclk_f for synchronizing external clock signals CLK and / CLK to output data when the digital synchronous memory device outputs data to the outside. .

The pipe latch 50 receives the first and second data output from the cell block 60 in response to the pipe input enable signal pin <k> and receives the path selection signal ian0. <k>), and then outputs data to the outside according to the first and second pipe output enable signals pout_r and pout_f. That is, the pipe latch 50 has a plurality of inputs, storages and outputs to pre-fetch data (even data, odd data) output from the cell block 60.

Here, the pipe latch 50 is configured to prefetch and output two bits of data, but in general, a digital synchronous memory device prefetches a plurality of data according to a burst length (BL) and then synchronizes to a clock. In order to output them sequentially, a plurality of pipe latches are provided. At this time, in order to output the data sequentially in synchronization with the clock, the counters 22, 34, 43, and 43 'are sequentially enabled with a plurality of output signals (pin <0: n>, ian0 <0). : n>, pout_r <0: n>, pout_f <0: f>). The four counters 22, 34, 43, and 43 'are enabled for read signals read, respectively, so as to continuously output when the data is output at high speed from the digital synchronous memory device.

For example, when the burst length BL is 3, three pipe latches are provided, and the first and second data (even data and odd data) are respectively applied to the pipe input enable signals (for example, pin0, pin1, and pin2). Are respectively received by the path selection signals (eg, ian0, ian1, and ian2) and sequentially stored by the first and second pipe output enable signals (eg, pout_r0, pout_r1, pout_r2, pout_f0, pout_f1, and pout_f2). Will print. Here, the external clock CLK outputs the output data dour_r0, dout_r1, and dout_r2 by the first pipe output enable signals pout_r0, pout_r1, and pout_r2 at the rising edge timing, and the external clock CLK at the falling edge timing. The output data dour_r0, dout_r1, and dout_r2 are output by the second pipe output enable signals pout_f0, pout_f1, and pout_f2.

FIG. 2 is a circuit diagram of a pipe latch for prefetching and outputting two bits of data, as described above. The transmission gate T1 of the input unit 51 according to the pipe input enable signal pin <k>. T2 is turned on and the data (even data and odd data) output from the cell block 60 are stored in the latches L1 and L2, respectively. Subsequently, the transfer gates T3 and T4 and the transfer gates T5 and T6 are selectively turned on according to the path selection signal ian0 <k> to store the data even data and odd data in the latches L3 and L4, respectively. do.

Subsequently, the transfer gate T7 is turned on according to the first pipe output enable signal pout_r <k> to output the data stored in the latch L3 as output data dout_r, and the second pipe output enable signal pout_f. The transfer gate T8 is turned on to output the data stored in the latch L4 as output data dout_f. In addition, the data stored in the latches L1 and L2 according to the path selection signal ian0 <k> may be exchanged and stored in the latches L4 and L3 and output as output data dout_r and dour_f, respectively.

Accordingly, the data is sequentially output by the burst length BL in synchronization with the rising edge and the falling edge of the external clocks CLK and / CLK.

However, when the digital synchronous memory device prefetches data and then multiplexes and outputs the data, the circuit is complicated because there are many steps for synchronizing the data, which results in the data output from the cell block 60 (even data, High speed data output is difficult because odd data is finally output after a large delay time.

An object of the present invention is to provide a pipe latch circuit of a digital synchronous memory device capable of outputting data at high speed by simplifying the operation of prefetching and outputting data in the synchronous memory device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous memory device in which the entire area is reduced by simplifying the configuration of the data output circuit by using the pipe latch circuit in the synchronous memory device.

In order to achieve the above object, the present invention is a pipe latch circuit of a synchronous memory device for prefetching, storing and outputting first and second data output from a cell block, the storage unit including first and second latches ; An input unit enabled by a pipe input enable signal to selectively store the first and second data in the first and second latches by a path selection signal generated each time an address is applied; And an output unit for outputting the first and second data stored in the storage unit in response to the first and second pipe output enable signals, respectively.

The present invention also provides a synchronous memory device having a pipe latch circuit for prefetching, storing, and outputting first and second data output from a cell block, comprising: a storage unit having first and second latches; An input unit enabled by a pipe input enable signal to selectively store the first and second data in the first and second latches by a path selection signal generated each time an address is applied; An output unit configured to output first and second data stored in the storage unit in response to first and second pipe output enable signals, respectively; And a path selection signal generation unit configured to receive and latch an address signal, delay a predetermined time, and generate the path selection signal, wherein the path selection signal generation unit generates the buffered address signal by a cas signal in a read state. Latch means for latching in response to the generated pulse; And a delay for generating the path selection signal according to the timing of the pipe input enable signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 3 is a block diagram illustrating a data output unit of a digital synchronous memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the synchronous memory device according to the present invention includes a first buffer 210 for buffering the external clock CLK to an operation potential level inside the memory device and outputting the internal clock CLK_IN, and an internal clock. Internal operation of receiving a counter 220 and an address signal AN for converting and outputting the CLK_IN into a plurality of pipe input enable signals pin <0: n> in response to a read command read. The second buffer 310 for buffering at the potential level, the latch 320 for latching the output of the second buffer 310, and the latch in accordance with the timing of the pipe input enable signal pin <0: n>. A delay 330 for outputting the output of the 320 as a path selection signal ian0, and control signals (/ CS, / RAS, / CAS, / WE) related to the read state from the outside to the internal clock CLK_IN. Enable signal for synchronously receiving the input, decoding the latch, and enabling the latch means 320 of the address latch unit 300. a decoder 100 for outputting cas_rd and activating the read command signal read, a third buffer 410 for buffering the external clock CLK to an internal operating potential level, and an external clock ( For outputting the first and second delay lock clocks dllclk_r and dllclk_f which have fixed the rising edge and the falling edge of the clock signal output from the third buffer 410 in synchronization with CLK). A second counter 430 'for outputting the plurality of first pipe output enable signals pout_r <0: n> using the delay locked loop 420 and the first delay locked clocks dllclk_r and dllclk_f. And a third counter 430 for outputting the plurality of second pipe output enable signals dllclk_r using the second delay lock clock dllclk_f and an enable signal pin <0: n>. Receives data from the cell block 600 by the path selection signal ian0 and enables first and second pipe outputs. A pipe latch 500 for outputting data by a signal is provided.

In addition, the pipe latch 500 according to the present invention is enabled by a storage unit 520 including the first and second latches L1 and L2 and a pipe input enable signal (for example, pin <0>). An input unit 510 and a storage unit 520 for selectively storing the first and second data (even data and odd data) in the first and second latches L1 and L2 by a path selection signal ian0. ) To the output data (dout_r, dout_f) in synchronization with the first and second pipe output enable signals (e.g., pout_r <0>, pout_f <0>). An output unit 530 for outputting is provided.

4 is an internal circuit diagram of the pipe latch shown in FIG.

Referring to FIG. 4, the input unit 520 may include a first end gate ND1 and I1 for receiving a pipe input enable signal pin <k> and a path selection signal ian0, and a pipe input enable signal ( pin <k> is input to one side and the other end is turned on at the outputs of the second AND gates ND2 and I2 and the first AND gate ND1 and I1 that receive the inverted path selection signal ian0. A first transfer gate T1 for transmitting first data and a second transfer gate for transferring second data by being turned on at an output of the first end gates ND1 and I1. T2, the third transfer gate T3 for turning on the outputs of the second AND gates ND2 and I2 and outputting the first data, and the outputs of the second AND gates ND2 and I2. A fourth transmission gate T4 is turned on to output second data.

The storage unit 520 includes a first latch L1 for storing first data and a second latch L2 for storing second data.

The output unit 530 is turned on by the first pipe output enable signal pout_r <k> and is fifth transfer gate T5 for outputting first data (even data) stored in the first latch L1 to the outside. And a sixth transfer gate T6 for turning on the second pipe output enable signal pout_f <k> to output second data (odd data) stored in the second latch L2 to the outside (dout_r, dout_f). ).

3 and 4, the operation of the dial-synchronized memory device according to the present invention will be described.

First, buffers 0 and 3 (210 and 410) are devices for buffering potential levels of externally input clock signals CLK and CLK to a CMOS level suitable for internal operation of a digital synchronous memory device. Is a device for buffering a plurality of input control signals (/ CS, / RAS, / CAS, / WE) at a CMOS level suitable for internal operation, and buffer 2 310 is suitable for internal operation of the address signal AN. The device is designed to synchronize to the internal clock (CLK) while buffering at the CMOS level.

Meanwhile, the decoder 120 is a device for decoding the buffered control signals / CS, / RAS, / CAS and / WE. When the external clock CLK is a rising edge, the control signal / CS, / CAS is low level and control signal (/ RAS, / WE) is high level, it is to decode to read state. If a read command is input from the outside at this time, the internal control signal (cas_rd) and read signal (read) Enable).

The DLL 420 is a device for outputting the first and second delayed adjusted clock signals dllclk_r and dllclk_f delayed-adjusted to the external clock CLK, / CLK to synchronize and output data.

In addition, the three counters 220, 430, and 430 'shown are enabled for read signals, and sequentially enable the pipe latches 500 provided in order to output data at high speed in the digital synchronous memory device. do.

On the other hand, the input unit 510 of the pipe latch 500 is enabled by the pipe input enable signal pin <k>, and the first and second outputs from the cell block 600 in synchronization with the path selection signal ian0. Second data (even data, odd data) are input. Subsequently, the output unit 530 of the pipe latch 500 according to the first and second pipe output enable signals (for example, pout_r <k> and pout_f <k>) output from the counters 430 and 430 'of the data output control unit 400. ) Will output the data to the outside.

FIG. 2 is a circuit diagram of a pipe latch for prefetching and outputting 2 bits of data. The path selection signal ian0 is input when the pipe input enable signal pin outputted from the counter 0 220 is input high. When high is input, the transmission gates T1 and T2 of the input unit 510 are turned on, and the data (even data and odd data) output from the cell block 600 are stored in the latches L1 and L2, respectively. Subsequently, the first data even data is output as the first output data dout_r by the first and second pipe output enable signals pout_r <k> and pout_f <k>, and the second data odd data. ) Is output as the second output data dout_f.

On the other hand, when the path selection signal ian0 is input low, the transmission gates T3 and T4 of the input unit 510 are turned on so that the data (even data and odd data) output from the cell block 600 is latched (L2, Are stored in L1). Subsequently, the first data even data is output as the second output data dout_f by the first and second pipe output enable signals pout_r <k> and pout_f <k>, and the second data odd data. ) Is output as the first output data dout_r.

Therefore, according to the present invention, the data output from the cell block according to the external clock CLK is multiplexed and output from the pipe latch 500 in the dial synchronizing memory device. You can output to the outside.

In addition, according to the present invention, since the path selection signal ian <0: n>, which is conventionally enabled and sequentially input to a plurality of pipe latches, is used as one path selection signal ian, the timing and control part is used. Simpler than This is because in the input unit 510 of the pipe latch 500 used in the present invention, the multiplexing signal ian is input only when the pipe input enable signal pin <k> is enabled.

In addition, since the entire circuit is simplified, the area of the circuit can be reduced.

FIG. 5 is a block diagram showing a data output unit of the digital synchronous memory device according to the second embodiment of the present invention.

Referring to FIG. 5, the data output unit of the digital synchronous memory device according to the second embodiment has two delays 340 and 350 and a latch on an output portion of the latch 320 for latching an address signal in the block configuration as shown in FIG. 3. 360 is further provided. The two delays 340 and 350 and the latch 360 are for further optimizing the timing of the pipe input enable signal pin <k> and the path selection signal ian0 input to the pipe latch 500.

The first delay 340 delays the latch enable signal cas_rd output from the decoder 120 by a predetermined time, and then outputs it as a clock signal of the latch 360 provided, and the second delay 350 latches the latch. The output of the 320 is delayed and then transferred to the latch 360. Subsequently, the latch 360 outputs the path selection signal ian0 to the input unit 510 of the pipe latch 500 as before.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the detailed description of the present invention, a dial synchronous memory device has been described, but it can be used in a general synchronous memory device.

When the pipe latch circuit according to the present invention is applied to a synchronous memory device, unnecessary delay time during data output is eliminated, and data can be output at high speed.

1 is a block diagram of a conventional digital synchronous memory device.

2 is an internal circuit diagram of the pipe latch shown in FIG.

3 is a block diagram showing a dial-synchronized memory device according to a preferred embodiment of the present invention.

4 is an internal circuit diagram of the pipe latch shown in FIG.

Fig. 5 is a block diagram showing a dial synchronizing memory device according to a second embodiment of the present invention.

* Explanation of Signs of Major Parts of Drawings *

I1 ~ I16: Inverter

T1 ~ T8: Transmission Gate

Claims (4)

A pipe latch circuit of a synchronous memory device for prefetching, storing, and outputting first and second data output from a cell block, A storage unit having first and second latches; An input unit enabled by a pipe input enable signal to selectively store the first and second data in the first and second latches by a path selection signal generated each time an address is applied; And An output unit for outputting first and second data stored in the storage unit in response to first and second pipe output enable signals, respectively Pipe latch circuit of the synchronous memory device having a. The method of claim 1, The input unit A first AND gate configured to receive the pipe input enable signal and the path selection signal; A second AND gate receiving the pipe input enable signal to one side and the other path selection signal inverted to the other side; A first transfer gate turned on at an output of the first AND gate to transfer the first data to the first latch; A second transfer gate turned on at an output of the first AND gate to transfer the second data to the second latch; A third transfer gate turned on at an output of the second AND gate to transfer the first data to the second latch; And And a fourth transfer gate turned on at an output of the second AND gate to transfer the second data to the first latch. The method of claim 2, The output unit A fifth transfer gate turned on by the first pipe output enable signal and outputting data stored in the first latch as first output data; And And a sixth transfer gate for turning on the second pipe output enable signal and outputting data stored in the second latch as second output data. A synchronous memory device having a pipe latch circuit for prefetching, storing, and outputting first and second data output from a cell block. A storage unit having first and second latches; An input unit enabled by a pipe input enable signal to selectively store the first and second data in the first and second latches by a path selection signal generated each time an address signal is applied; An output unit configured to output first and second data stored in the storage unit in response to first and second pipe output enable signals, respectively; And A path selection signal generation unit for receiving an address signal, latching the same, delaying a predetermined time, and generating the path selection signal; The path selection signal generator, Latch means for latching the buffered address signal in response to a cascade pulse generated by the cas signal; And Delay for generating the path selection signal by matching the output of the latch means to the timing of the pipe input enable signal Synchronous memory device having a.