KR100479969B1 - Method for manufacturing a flash memory device - Google Patents
Method for manufacturing a flash memory device Download PDFInfo
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- KR100479969B1 KR100479969B1 KR10-2002-0024150A KR20020024150A KR100479969B1 KR 100479969 B1 KR100479969 B1 KR 100479969B1 KR 20020024150 A KR20020024150 A KR 20020024150A KR 100479969 B1 KR100479969 B1 KR 100479969B1
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- nitride film
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 27
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000005641 tunneling Effects 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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Abstract
본 발명은 반도체 플래시 메모리 소자 제조 기술에 관한 것으로, 실리콘 기판 상에 터널링 산화막과 부유 게이트용 폴리실리콘을 증착한 후, 폴리실리콘 상부에 실리콘 질화막과 TEOS층을 증착하는 단계와, 패터닝 공정을 수행하여 TEOS층과 실리콘 질화막을 식각하는 단계와, 식각 공정 수행 후, H3PO4 및 BOE 처리 공정을 수행하여 실리콘 질화막 및 TEOS 측벽의 스트라이프를 제거하는 단계와, H3PO4 및 BOE 처리 공정이 완료되면, 부유 게이트용 폴리실리콘, 터널링 산화막, 실리콘 기판을 식각하여 부유 게이트를 위한 액티브 영역을 형성하는 단계를 포함한다. 본 발명에 의하면, 반응성 이온 식각 공정 이후에 H3PO4와 BOE 처리 공정을 추가하여 실리콘 질화막과 TEOS층 측면에 발생하는 스트라이프를 제거함으로써 정션에서의 누설 전류를 줄여 반도체 플래시 메모리 소자의 고유 특성을 향상시킬 수 있을 뿐만 아니라, 기존에 사용되는 H3PO4와 BOE를 적용한 바, 새로운 장비 투자에 따른 제조 비용을 줄일 수 있는 효과가 있다.The present invention relates to a semiconductor flash memory device manufacturing technology, after depositing a tunneling oxide film and a floating gate polysilicon on a silicon substrate, by depositing a silicon nitride film and TEOS layer on the polysilicon, and performing a patterning process Etching the TEOS layer and the silicon nitride film, removing the stripe of the silicon nitride film and the TEOS sidewall by performing an H 3 PO 4 and BOE process after performing the etching process, and completing the H 3 PO 4 and BOE process And etching the polysilicon for the floating gate, the tunneling oxide film, and the silicon substrate to form an active region for the floating gate. According to the present invention, after the reactive ion etching process, H 3 PO 4 and BOE treatment process are added to remove the stripe generated on the side of the silicon nitride film and the TEOS layer, thereby reducing leakage current at the junction, thereby reducing the intrinsic characteristics of the semiconductor flash memory device. As well as improving, the existing H 3 PO 4 and BOE are applied, which reduces the manufacturing cost of new equipment investment.
Description
본 발명은 반도체 플래시 메모리 소자 제조 기술에 관한 것으로, 특히, 폴리실리콘을 이용하여 패터닝시 난반사에 의한 스트라이프(stripe) 제거가 용이한 반도체 플래시 메모리 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor flash memory device fabrication technology, and more particularly, to a method for fabricating a semiconductor flash memory device in which stripe is easily removed by diffuse reflection when patterning using polysilicon.
일반적인 플래시 메모리는 도 1a 내지 도 1c에 도시한 바와 같이, 부유 게이트를 위하여 터널링 산화막(102)과 폴리실리콘(104)을 증착하고, 질화막(106)과 산화막(108)을 입혀서 패터닝 및 식각하여 필드 영역과 액티브 영역이 분리된 구조를 갖는다.A typical flash memory, as shown in Figs. 1A to 1C, deposits a tunneling oxide film 102 and a polysilicon 104 for floating gates, and is patterned and etched by coating a nitride film 106 and an oxide film 108. The region and the active region are separated.
이러한 구조를 갖는 전형적인 플래시 메모리 소자 제조 과정을 살펴보기로 한다.A typical flash memory device manufacturing process having such a structure will be described.
먼저, 도 1a에 도시한 바와 같이, 실리콘 기판(100) 상에 터널링 산화막(102)과 부유 게이트용 폴리실리콘(104)을 증착한 후, 실리콘 질화막(106)과 TEOS(Tetraethylorthosilicate)층(108)을 증착한 다음 패터닝을 수행하여 TEOS층(108)과 실리콘 질화막(106)을 식각한다.First, as shown in FIG. 1A, after the tunneling oxide film 102 and the floating gate polysilicon 104 are deposited on the silicon substrate 100, the silicon nitride film 106 and the TEOS (Tetraethylorthosilicate) layer 108 are deposited. After deposition, the TEOS layer 108 and the silicon nitride film 106 are etched by performing patterning.
그런 다음, 도 1b 및 도 1c에 도시한 바와 같이, 부유 게이트용 폴리실리콘(104), 터널링 산화막(102), 실리콘 기판(100)을 식각하여 부유 게이트를 위한 액티브 영역을 형성한다.1B and 1C, the floating gate polysilicon 104, the tunneling oxide film 102, and the silicon substrate 100 are etched to form an active region for the floating gate.
이때, 도 1a 내지 도 1c에 도시한 바와 같이, 하부막이 폴리실리콘(104)일 경우에는 패터닝을 수행할 시, 난반사에 의하여 스트라이프(10)가 발생하게 된다.In this case, as shown in FIGS. 1A to 1C, when the lower layer is polysilicon 104, the stripe 10 is generated by diffuse reflection when patterning is performed.
이러한 스트라이프(10)를 방치할 경우, 정션(12)에 다량의 누설 전류가 발생하는 바, 플래시 메모리의 고유 특성이 저하될 수 있다는 문제가 제기되었다.When the stripe 10 is left, a large amount of leakage current is generated in the junction 12, which poses a problem that the inherent characteristics of the flash memory may be degraded.
본 발명은 상술한 문제를 해결하기 위해 안출한 것으로, 반응성 이온 식각 공정 이후에 H3PO4와 BOE(Buffer Oxide Etchant) 처리 공정을 추가하여 실리콘 질화막과 TEOS층 측면에 발생하는 스트라이프를 제거함으로써 정션에서의 누설 전류 발생을 억제하도록 한 반도체 플래시 메모리 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, by adding a H 3 PO 4 and BOE (Buffer Oxide Etchant) treatment process after the reactive ion etching process to remove the stripes generated on the side of the silicon nitride film and TEOS layer SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor flash memory device capable of suppressing leakage current in the semiconductor device.
이러한 목적을 달성하기 위하여 본 발명은, 반도체 플래시 메모리 소자 제조 방법에 있어서, 실리콘 기판 상에 터널링 산화막과 부유 게이트용 폴리실리콘을 증착한 후, 폴리실리콘 상부에 실리콘 질화막과 TEOS층을 증착하는 단계와, 패터닝 공정을 수행하여 TEOS층과 실리콘 질화막을 식각하는 단계와, 식각 공정 수행 후, H3PO4 및 BOE 처리 공정을 수행하여 실리콘 질화막 및 TEOS 측벽의 스트라이프를 제거하는 단계와, H3PO4 및 BOE 처리 공정이 완료되면, 부유 게이트용 폴리실리콘, 터널링 산화막, 실리콘 기판을 식각하여 부유 게이트를 위한 액티브 영역을 형성하는 단계를 포함하는 반도체 플래시 메모리 소자 제조 방법을 제공한다.In order to achieve the above object, the present invention provides a method for fabricating a semiconductor flash memory device, comprising depositing a tunneling oxide film and a polysilicon for floating gate on a silicon substrate, and then depositing a silicon nitride film and a TEOS layer on the polysilicon. , Etching the TEOS layer and the silicon nitride film by performing a patterning process, removing the stripes of the silicon nitride film and the TEOS sidewall by performing an H 3 PO 4 and BOE process after performing the etching process, and H 3 PO 4 And etching the polysilicon for the floating gate, the tunneling oxide layer, and the silicon substrate to form an active region for the floating gate when the BOE treatment process is completed.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
설명에 앞서, 본 발명의 핵심 기술 요지는 반도체 플래시 메모리 소자 제조 과정에서 반응성 이온 식각 공정 이후에 H3PO4와 BOE 처리 공정을 추가하여 실리콘 질화막 및 TEOS층을 소정 조건하에서 식각하여 실리콘 질화막과 TEOS층 측면에 발생하는 스트라이프를 제거한다는 것으로, 이러한 기술 사상으로부터 본 발명에서 목적으로 하는 바를 용이하게 달성할 수 있을 것이다.Prior to the description, a key technical aspect of the present invention is to add a H 3 PO 4 and BOE treatment process after the reactive ion etching process in the semiconductor flash memory device manufacturing process to etch the silicon nitride film and TEOS layer under a predetermined condition to the silicon nitride film and TEOS By removing the stripe generated on the side of the layer, it is possible to easily achieve the object of the present invention from this technical idea.
도 2는 본 발명의 바람직한 실시예에 따른 반도체 플래시 메모리 소자 제조 과정의 흐름도이다.2 is a flowchart illustrating a process of fabricating a semiconductor flash memory device according to a preferred embodiment of the present invention.
본 과정은 H3PO4와 BOE 처리 공정을 제외하고 앞서 기술한 도 1의 플래시 메모리 소자 제조 과정과 동일한 바, 중복되는 설명에서는 동일한 도면 및 부호를 인용하기로 한다.This process is the same as the flash memory device fabrication process of FIG. 1 except for the H 3 PO 4 and BOE treatment process, the same reference numerals will be referred to in the overlapping description.
먼저, 단계(S200)(S202)에서는 실리콘 기판(100) 상에 터널링 산화막(102)과 부유 게이트용 폴리실리콘(104)을 증착하고, 그 상부에 실리콘 질화막(106)과 TEOS층(108)을 증착한다.First, in step S200 and S202, the tunneling oxide film 102 and the floating gate polysilicon 104 are deposited on the silicon substrate 100, and the silicon nitride film 106 and the TEOS layer 108 are deposited on the silicon substrate 100. Deposit.
이후, 단계(S204)에서는 패터닝 공정을 수행하여 TEOS층(108)과 실리콘 질화막(106)을 식각한다.Thereafter, in step S204, a patterning process is performed to etch the TEOS layer 108 and the silicon nitride film 106.
이러한 식각 공정이 완료되면 단계(S206)(S208)로 진행한다. 단계(S206)(S208)에서는 본 발명에 따른 H3PO4 및 BOE 처리 공정을 수행하여 실리콘 질화막(106) 및 TEOS(108)층을 제거한다.When the etching process is completed, the process proceeds to step S206 and step S208. In step S206 and step S208, the H 3 PO 4 and BOE treatment processes according to the present invention are performed to remove the silicon nitride film 106 and the TEOS 108 layer.
이러한 H3PO4 및 BOE 처리 공정은 실리콘 질화막(106) 및 TEOS층(108)을 소정 조건에서 식각하여 실리콘 질화막(106)과 TEOS층(108) 측면에 발생하는 스트라이프(10)를 제거하기 위한 공정이다.This H 3 PO 4 and BOE treatment process is to remove the stripe 10 generated on the silicon nitride film 106 and TEOS layer 108 side by etching the silicon nitride film 106 and TEOS layer 108 under a predetermined condition. It is a process.
여기서, 실리콘 질화막(106)을 식각하기 위한 H3PO4의 처리 조건은 다음과 같다.Here, processing conditions of H 3 PO 4 for etching the silicon nitride film 106 are as follows.
먼저, 온도는 150℃ 내지 160℃로 설정되는 것이 바람직한데, 그 이유는 실리콘 질화막(106)이 150℃ 이상의 온도에서만 식각되기 때문이다.First, the temperature is preferably set to 150 ° C to 160 ° C, because the silicon nitride film 106 is etched only at a temperature of 150 ° C or higher.
그리고, H3PO4의 농도는 85 내지 93%가 바람직한데, 그 이유는 적당량의 DI가 존재하지 않으면 실리콘 질화막(106)이 식각되지 않을 뿐만 아니라 온도 또한 150℃ 이상 상승하지 않기 때문이다.In addition, the concentration of H 3 PO 4 is preferably 85 to 93% because the silicon nitride film 106 is not etched unless the appropriate amount of DI is present, and the temperature does not rise by more than 150 ° C.
이때, 이러한 H3PO4에 의한 실리콘 질화막(106)의 식각 범위는 150 내지 220Å으로 설정하는 것이 바람직하다. 이러한 식각 범위는 액티브 영역이 과도하게 손실되지 않으면서 스트라이프(10)를 효과적으로 제거하기 위한 적정 범위이다.At this time, the etching range of the silicon nitride film 106 by the H 3 PO 4 is preferably set to 150 to 220 kPa. This etching range is an appropriate range for effectively removing the stripe 10 without excessively losing the active region.
한편, TEOS층(108)을 식각하기 위한 BOE의 처리 조건은 상술한 실리콘 질화막(106)의 식각 조건, 즉, 150 내지 220Å의 식각 범위와 동일하게 설정한다.Meanwhile, the processing conditions of the BOE for etching the TEOS layer 108 are set to be equal to the etching conditions of the silicon nitride film 106 described above, that is, the etching range of 150 to 220 kV.
본 실시예에서는 H3PO4 및 BOE를 순차적으로 처리하는 것과 BOE를 먼저 처리한 후에 H3PO4를 처리하는 것의 두 가지 경우가 모두 적용 가능하다.In this embodiment, both cases of sequentially treating H 3 PO 4 and BOE and treating H 3 PO 4 after treating BOE are applicable.
이러한 H3PO4 및 BOE 처리 공정이 완료되면, 단계(S210)로 진행하여 부유 게이트용 폴리실리콘(104), 터널링 산화막(102), 실리콘 기판(100)을 식각하여 부유 게이트를 위한 액티브 영역을 형성하고 본 과정을 종료한다.When the H 3 PO 4 and BOE treatment processes are completed, the process proceeds to step S210 to etch the floating gate polysilicon 104, the tunneling oxide layer 102, and the silicon substrate 100 to form an active region for the floating gate. Form and terminate this process.
이상, 본 발명을 실시예에 근거하여 구체적으로 설명하였지만, 본 발명은 이러한 실시예에 한정되는 것이 아니라, 그 요지를 벗어나지 않는 범위내에서 여러 가지 변형이 가능한 것은 물론이다.As mentioned above, although this invention was concretely demonstrated based on the Example, this invention is not limited to this Example, Of course, various changes are possible within the range which does not deviate from the summary.
이상 설명한 바와 같이, 본 발명은 정션 누설 전류를 줄여 반도체 플래시 메모리 소자의 고유 특성을 향상시킬 수 있으며, 기존에 사용되는 H3PO4와 BOE를 적용한 바, 새로운 장비 투자에 따른 제조 비용을 줄일 수 있는 효과가 있다.As described above, the present invention can improve the inherent characteristics of the semiconductor flash memory device by reducing the junction leakage current, and can reduce the manufacturing cost of the new equipment investment by applying the existing H 3 PO 4 and BOE It has an effect.
10 : 스트라이프 12 : 정션10: stripe 12: junction
100 : 실리콘 기판 102 : 터널링 산화막100 silicon substrate 102 tunneling oxide film
104 : 부유 게이트용 폴리실리콘 106 : 실리콘 질화막104: polysilicon for floating gate 106: silicon nitride film
108 : TEOS층108: TEOS layer
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