KR100475318B1 - Multiplex bucket brigade circuit - Google Patents

Abstract

Sensor chip assembly time delay integration circuits useful with image sensing arrays include duplex bucket brigade circuits 120 having two or more charge transfer paths, a plurality of capacitors 130, 133, and 136 common to the charge transfer paths, and A plurality of capacitors 131, 132, 134, 135 specified in each charge transfer path is used. Each charge transfer path has a plurality of MOSFET transfer gates 122, 124, 126, 128; 123, 125, 127, 129 coupled in series, with a common capacitor and path specific capacitors alternately coupled to the path. have. Each common capacitor is controllably coupled to unit cell input circuits 113, 116, 119, reset nodes 111, 114, 117, or open circuits 112, 115, 118. The circuit operates by storing the image sensor charge accumulated from the alternating sensor lines in the path specific capacitor. The common capacitor is reset and then acquires a first set of image sensor charges that are coupled to the unit cell input circuitry. For example, charge stored in a capacitor in a particular path is then transferred through a transfer gate to a common capacitor, substantially accumulating charge in the common capacitor. Thereafter, charge is transferred from the common capacitor to the capacitor of the same specific path to store the charge again. The sequence of reset, charge acquisition, summation transfer, and store transfer is repeated for each charge transfer path.

Description

Multiplex Bucket Brigade Circuit {MULTIPLEX BUCKET BRIGADE CIRCUIT}

The present invention relates to circuitry useful for processing the output of an image sensing array. In particular, the present invention relates to a time delay integration (TDI) circuit useful for processing the output of an image sensing array.

Time Delay Integration (TDI) architectures are typically mounted in high-speed digital image sensing devices such as charge coupled device (CCD) image sensors to achieve good sensitivity, but can vary in wavelengths of infrared, visible and x-ray wavelengths, for example. It is also useful for many different types of image sensing arrays. In a TDI architecture, an image sensing array is optically scanned such that each portion of the image is sensed in a synchronous and delayed manner by different portions (typically lines) of the array. The plurality of outputs of the image sensing array over time for each portion of the image are summed up to improve the sensitivity and spatial resolution of the image sensing device. One measure of image sensing device performance is the Modulation Transfer Function (MTF), which is defined as the spatial frequency-to-modulation ratio (ratio of modulation of the output signal to modulation of the input signal).

Typically, TDI circuits are implemented within a type of silicon-based integrated circuit known as a read-out integrated circuit (ROIC), which is combined with a sensing array to form a sensor chip assembly (SCA). SCA is used in a variety of digital imaging systems, including, for example, night vision cameras, surveillance cameras, remote imaging cameras, and manufacturing line inspection cameras, as well as standard army dewar assembly (SADA) type applications and three color activities. It can also be used as appropriate. Tricolor activity is a scanning system that implements one or more spectral bands (ie, colors) in an SCA. Each color is defined by a bank of sensing elements into which a single spectral color is incident. SCA is particularly useful when the sensing array consists of non-silicon semiconductor material, which is typically used because it is inherently sensitive to various useful portions of the electromagnetic spectrum. Image information is generated in the imaging array in the form of charge. Charge is collected and processed by a typical silicon-based ROIC. SCA manufactures sensing arrays separately from ROICs and mounts the sensing arrays and ROICs on ordinary or ordinary printed circuit boards, mounting the sensing array substrates on ROIC substrates, and then manufacturing the sensing arrays. It is manufactured using a variety of known techniques.

Time delay integration can be performed in an SCA TDI architecture using a CCD array in a side rider configuration. Unfortunately, the design rules for this integrated circuit do not allow large storage wells and other circuit elements to be placed in a unit cell in a small unit cell area, thereby limiting the maximum resolution of the CCD sensing device. Throw it away. In addition, the time delay integration can be performed using a standard bucket brigade (BBD) circuit instead of the CCD, but is a useful TDI circuit for processing the output of an image sensing array, which is useful for implementing side rider CCDs while maintaining or improving the MTF. There is a need for a TDI circuit with a reduced ROIC circuit compared to the required ROIC circuit.

1 is a schematic block diagram of a CCD based side rider SCA architecture.

2 is a circuit diagram of a bucket brigade circuit.

3 is a circuit diagram of a duplex bucket brigade circuit for two samples of SCA TDI per dwell in accordance with the present invention.

4 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how unit cell charge is transferred into the circuit.

5 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how unit cell charge is added to previous even samples.

6 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 illustrating how common capacitor charge is transferred to an even path capacitor.

7 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how the common capacitor is reset.

8 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how unit cell charge is transferred into the circuit.

9 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how unit cell charge is added to previous odd samples.

10 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how common capacitor charge is transferred to an odd path capacitor.

11 is a waveform diagram of various clock and control signals used in a transfer up process.

12 is a waveform diagram of various clock and control signals used in a transfer down process.

[Overview of invention]

The foregoing need in the art is addressed by the present invention, and one embodiment of the present invention is a time delay integration circuit that obtains n samples per dwell. The time delay integration circuit includes a plurality of first capacitors; A plurality of imaging sensor unit cell inputs controllably coupled to the first capacitor, respectively; a plurality of groups of n second capacitors; And a plurality of charge transfer paths including a transfer gate coupled in series through a path segment that is alternately coupled to each second capacitor in one of the first and second groups of capacitors in series. do.

Another embodiment of the present invention, a plurality of first capacitors; A plurality of imaging sensor unit cell inputs controllably coupled to the first capacitor, respectively; A plurality of reset inputs controllably coupled to the first capacitor, respectively; A plurality of second capacitors; A plurality of third capacitors; A first charge transfer path comprising a plurality of first transfer paths coupled in series through a plurality of first path segments alternately coupled to each one of the first and second capacitors; And a second charge transfer path comprising a plurality of second transfer gates coupled in series through a plurality of second path segments alternately coupled to each one of the first and third capacitors. Circuit.

Yet another embodiment of the present invention is a sensor chip assembly time delay integration circuit comprising a plurality of consecutively coupled circuit groups. Each circuit group comprises a first phase clock node; A second phase clock node; Reset node; Unit cell input circuits; A first capacitor having a first plate and a second plate coupled to a second phase clock node; A switch having a first terminal coupled to the reset node, a second terminal coupled to the unit cell input circuit, and a pole terminal coupled to the second plate of the first capacitor; A first transfer gate having a first terminal and a second terminal coupled to a second plate of the first capacitor; A second transfer gate having a first terminal and a second terminal coupled to a second plate of the first capacitor; A third transfer gate having a first terminal and a second terminal coupled to the second plate of the first capacitor; A fourth transfer gate having a first terminal and a second terminal coupled to the second plate of the first capacitor; A second capacitor having a first plate coupled to a first phase clock node and a second plate coupled to a second terminal of a fourth transfer gate; And a third capacitor having a first plate coupled to the first phase clock node and a second plate coupled to the second terminal of the third transfer gate. The second terminal of the first transfer gate of each neighboring group of the circuit group and the second terminal of the third transfer gate are connected together, the second terminal of the second transfer gate of each neighboring group of the circuit group, and The second terminal of the fourth transfer gate is connected together.

Still another embodiment of the present invention provides a method of time delay integration of an image sensor charge, the method comprising: storing image sensor charge accumulated from sensor lines alternately in each of a plurality of first capacitors and a plurality of second capacitors; Resetting a plurality of third capacitors; Receiving a first set of image sensor charges to a third capacitor; Transferring charge from the first capacitor to each third capacitor through a set of first transfer gates to accumulate in the third capacitors; Transferring charge from the third capacitor to the first capacitor through the set of second transfer gates, respectively; Resetting the third capacitor; Receiving a second set of image sensor charges to a third capacitor; Transferring charge from the second capacitor to each third capacitor through a set of third transfer gates to accumulate in the third capacitors; And transferring charge from the third capacitor to the second capacitor through the set of fourth transfer gates, respectively.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments and typical applications will be described with reference to the accompanying drawings in order to teach the present invention.

1 illustrates an SCA TDI architecture in which time delay integration is performed using a CCD array in a side rider configuration (Ref., High Performance InSb Scanning Sensor Chip with 26 In TDI, IRIS Bulletin, August 1992). Side rider CCD implementations work by injecting charge into every other bucket of the CCD circuit from the multiplexed unit cell output. Due to the size of the storage well required for the CCD circuit of FIG. 1 for reducing noise, the area of the storage well is typically large. Unfortunately, the design rules for integrated circuits do not allow large storage wells and other elements of the BBD circuit 10 to be placed in the unit cell for a unit cell area smaller than about 32 μm × 64 μm, thus providing CCD sensing. It will limit the maximum resolution of the device.

2 is an example of one type of bucket brigade (BBD) circuit useful for performing time delay integration.

3 shows a representative segment of a duplex BBD circuit 120 that performs SCA TDI with a reduced ROIC circuit, allowing the TDI function to be placed in a unit cell. In the conventional layout technology and manufacturing process alone, the maximum reduction of the ROIC area by about 70% can be achieved as compared to the side rider CCD implementation, and thus the duplex BBD circuit 120 can be disposed in the area of about 10 μm × 64 μm. TDI can still be performed in the unit cell with the margin available for input circuitry. Accordingly, the ROIC yield, the ROIC cost, and the resolution can be improved compared to the side rider CCD implementation. Moreover, the specific process used for the two-level polysilicon structures used to implement side rider CCDs is eliminated.

Size reduction in the duplex BBD circuit 120 is feasible for many reasons. For example, the duplex BBD circuit 120 reduces the number of transmissions required to perform TDI by more than two times, thereby reducing the capacitor size by two square roots (reducing the number of transmissions) for the same noise performance compared to a standard BBD implementation. Square root of The charge transfer efficiency required is reduced by 2 times compared to CCD or standard BBD implementations. Another example is the use of parallel signal paths implemented at the unit cell level, which allows for the sharing of storage capacitors (only three storage capacitors are needed to store two samples of information), in fact about two sample systems per dwell. A 25% reduction in the number of capacitors and a reduction in the overall capacitor area can be obtained. Thus, performance is improved with lower ROIC complexity. In addition, common capacitors are easily reset before charge is added, improving overall transfer efficiency and reducing crosstalk in the scan direction, which is useful for achieving good MTF in scanning SCA. do. In general, the multiplex BBD structure used in TDI circuits reduces the number of transmissions of TDI samples to the number of sensing elements, regardless of the number of samples per dwell, and increases the MTF through the reset of some of the BBD capacitors. Reducing the number of transmissions reduces the number of capacitors and capacitor size, and also improves the MTF.

Bidirectional, for example, US patent application (inventive name: Bi-directional Bucket Brigade Circuit, inventor: Chen et al., US Representative Case No. PDR98190, hereby incorporated by reference in its entirety) It can be realized using the technique described in the).

3 exemplarily shows three representative unit cells of a partial cell 140, a full cell 150, and a partial cell 160 with respective unit cell inputs 113, 116, 119. The even path of the duplex BBD circuit 120 has the same transfer gate as the MOSFET transistors 122, 124, 126, 128 connected in series, and the odd path of the duplex BBD circuit 120 is connected in series with the MOSFET. And a transfer gate such as transistors 123, 125, 127, 129. Suitable MOSFET transistors are known in the art. Clock phase Common capacitors 130, 133, 136, and clock phase controlled by _{two The} even-odd capacitor pairs 132-131 and 134-135 controlled by ₁ are alternately coupled between the even and odd paths of the duplex BBD circuit 120. Suitable semiconductor capacitors are known in the art. Transistor switch 112 controllably couples common capacitor 130 to unit cell input 113, reset 111, or open circuit. Similarly, transistor switch 115 controllably couples common capacitor 133 to unit cell input 116, reset 114, or open circuit, and transistor switch 118 unites common capacitor 136. Controllably couple to cell input 119, reset 117, or open circuit. Suitable MOSFET transistor switches are known in the art.

Although circuit 120 is illustratively shown as a duplex circuit with two charge transfer paths designated odd and even, circuit 120 has two, three, or more charge transfer paths at two, per dwell. It will be appreciated that it should be considered to represent a multiplex BBD circuit that obtains three or more samples. 'Dwell' is the time when the charge is effectively integrated. Although more circuitry is needed, systems that require higher multiples of samples per dwell are desirable to improve sensitivity while reducing their size.

The operation of the duplex BBD circuit 120 will be described with reference to FIGS. 4 to 10. In these figures, the potential at one node is represented by a box containing a letter indicating the ground position at which the detector starts, and a numeric subscript indicating the TDI number. Various clock and control signals used in the uplink transmission process and the downlink transmission process are shown in FIGS. 11 and 12, respectively.

4 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 illustrating how unit cell charge is transferred into duplex BBD circuit 120 and propagated along an even path. It is assumed that common capacitors 130, 133, and 136 start in the reset state. Capacitors 131, 132, 134, 135 each contain charges D _{1 + 2} , C _{1 + 2} , A _{1 + 2 + 3} , B _{1 + 2 + 3} . Switches 112, 115, and 118 are clock phase By selecting unit cell inputs 113, 116, 119 in synchronization with ₂ , charges E ₂ are common capacitors 130, charges C ₃ are common capacitors 133, and charges A ₄ are common capacitors 136. send.

5 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how unit cell charge is added to a previous even sample. Even path transistors 124 and 128 have a clock phase ₁ and ₂ in synchronism with the enable thereby, to move the charge C _{1 + 2} through the even-numbered channel transistor 124 adds to the charge C ₃ of the common capacitor 133, through the even-numbered channel transistor 128 charges A _{1 + 2 +} Move ₃ to add to charge A ₄ of common capacitor 136. The charges D _{1 + 2} and B _{1 + 2 + 3} of the even path capacitors 131, 135 are not disturbed.

6 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 illustrating how common capacitor charge is moved from a common capacitor to an even path capacitor so that the common capacitor is free for subsequent odd path operation. Even path transistors 122 and 126 have a clock phase ₁ and ₂ in synchronism with the enable thereby, the even path transistor 122, a charge E _{1 + 2} by moving the sikimyeo position to the even-path capacitor 132, the charge from the even-numbered channel transistor _{(126) C 1 + 2 +} 3 through Move to an even path capacitor 134. The charges D _{1 + 2} and B _{1 + 2 + 3} of the odd path capacitors 131, 135 are not disturbed.

7 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 illustrating how the common capacitor is reset. Switches 112, 115, and 118 are clock phase By selecting the resets 111, 114, and 117 in synchronization with ₂ , the common capacitors 130, 133, and 136 are reset. Transistors (122, 123, 124, 125, 126, 127, 128, 129) are both OFF, the charge E _{1 + 2,} in the odd-numbered paths capacitor charge D _{1 + 2,} the even path capacitor 132 of the 131 even- C _{1 + 2 + 3 of the} path capacitor 134 and the charge B _{1 + 2 + 3} of the odd path capacitor 135 are not disturbed.

8 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 illustrating how unit cell charge is transferred into the circuit and propagated along an odd path. Common capacitors 130, 133, 136 are in a reset state. Capacitors 131, 132, 134, 135 respectively include charges D _{1 + 2} , E _{1 + 2} , C _{1 + 2 + 3} , and B _{1 + 2 + 3} . Switches 112, 115, and 118 are clock phase By selecting unit cell inputs 113, 116, and 119 in synchronization with ₂ , charge F ₂ to common capacitor 130, charge D ₃ to common capacitor 133, and charge B ₄ to common capacitor 136. send.

9 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 showing how unit cell charge is added to a previous odd sample. Odd-path transistors 125 and 129 have a clock phase ₁ and ₂ in synchronism with the enable thereby, to move the charge D _{1 + 2} through the odd path, transistor 125 adds to the charge D ₃ of the common capacitor 133, through the odd path transistor 129, a charge B _{1 + 2 +} Move ₃ to add to charge B ₄ of common capacitor 136. The charges E _{1 + 2} and C _{1 + 2 + 3} of the even path capacitors 132, 134 are not disturbed.

10 is a circuit diagram of the duplex bucket brigade circuit of FIG. 3 illustrating how common capacitor charge is moved from a common capacitor to an odd path capacitor so that the common capacitor is free for subsequent even path operation. Odd-path transistors 123 and 127 have a clock phase ₁ and ₂ in synchronism with the is enabled, thereby through the odd path transistor 123, moving the charge F _{1 + 2} sikimyeo position in the odd path capacitor 131, the charge D _{1 + 2 + 3} via the odd path transistor 127, Move to position the odd path capacitor 135. The charges E _{1 + 2} and C _{1 + 2 + 3} of the even path capacitors 132, 134 are not disturbed.

Although the invention has been described with reference to exemplary embodiments for a particular application, the invention is not so limited. Those skilled in the art will recognize further modifications, applications, and implementations within the scope of the present invention, as well as additional fields in which the present invention has significant utility.

Thus, the present invention has been described herein with reference to specific embodiments for particular applications. Those skilled in the art will recognize additional variations, applications, and implementations within the scope of the present invention.

Accordingly, the appended claims are intended to cover all such applications, modifications, and implementations within the scope of this invention.

Claims (10)

A time delay integration circuit that obtains n samples per dwell, A plurality of first capacitors 130, 133, 136; A plurality of imaging sensor unit cell inputs (113, 116, 119) controllably coupled to the first capacitor, respectively; a plurality of groups of n second capacitors (131, 132; 134, 135); And A plurality of transfer gates 122, 124, 126 coupled in series through a plurality of path segments that are alternately successively coupled to each second capacitor of one of the first and one group of second capacitors 128, a plurality of charge transfer paths including 123, 125, 127, and 129; A time delay integrating circuit comprising: The method of claim 1, A plurality of reset inputs (111, 114, 117) are respectively controlably coupled to the first capacitor. Time delay integration circuit, characterized in that. The method according to claim 1 or 2, First phase clock node ( ₁ ) and the second phase clock node ( ₂ ) more, Each of the first capacitors is coupled to the second phase clock node Each of the second capacitors is coupled to the first phase clock node. Time delay integration circuit, characterized in that. The method according to claim 1 or 2, Multiple n path control signal nodes ( _EB , _OB ), the first transmission control signal node ( _{C1 / SW} , _{SW / C1} ), and the second transmission control signal node ( _{C2 / SW} , _{SW / C2} ), A transfer gate of each of the charge transfer paths is coupled to each one of the path control signal nodes, Neighboring transfer gates of the charge transfer path are coupled to the first transfer control signal node and a second transfer control signal node, respectively. Time delay integration circuit, characterized in that. The method according to claim 1 or 2, N is 2, One of the charge transfer paths is an odd path and the other of the charge transfer paths is an even path Time delay integration circuit, characterized in that. The method according to claim 1 or 2, And said transfer gate is a MOSFET transistor. delete delete delete delete