KR100465298B1 - Apparatus and Method for Selecting Input Signal of Private branch exchange - Google Patents

Abstract

The present invention provides a method of selecting one input signal from among a plurality of input signals input to a private exchange having an oscillator and a PLL, wherein each of the plurality of input signals is counted with an output signal frequency of the oscillator to reference the PLL. Comparing with the frequency, and extracting the counted value of the input signal having a higher priority from the counted value, and confirms whether the extracted counted value is out of a predetermined reference range for a predetermined time or more, the extraction If the counted value does not deviate from the predetermined reference range for more than a predetermined time, the input signal corresponding to the extracted count value is selected and transmitted to the PLL, thereby making frequency correction easier and simplifying the structure of the PLL. can do.

Description

Apparatus and Method for Selecting Input Signal of Private branch exchange}

The present invention relates to an input signal selection method and apparatus of a private exchange that can simultaneously select one input signal from a plurality of input signals and detect a frequency difference between the signals in order to synchronize the private exchange.

A phase locked loop (PLL) is a technique of transmitting speed adjustment information in a data stream and transmitting the signal together. The receiver extracts signal elements by fixing its local clock to the received speed adjustment information.

1 is a diagram schematically illustrating a PLL.

Referring to FIG. 1, the PLL includes a phase detector 100, a frequency corrector 110, a loop filter 120, and an oscillator (VCO) 130.

The phase detector 100 detects a phase difference between the input signal and the synchronized output signal. The phase difference detection method includes an XOR gate and a JK flip-flop. The method of using the XOR gate has the advantage that the structure is simple and the speed is small, but the detection range is small.

The method of using the JK flip-flop has the advantage that the detection range is doubled than using the XOR gate, but the speed is slower than that of the XOR gateway and the structure is complicated.

The frequency correction unit 110 detects a frequency difference between the input signal and the oscillator 130 output signal. The frequency corrector 110 corrects a frequency difference caused by interference between symbols, noise caused by temperature and external factors, and jitter. The frequency corrector 110 loads the frequency and phase detected by the phase detector 100 in one signal and transmits the same to the loop filter 120.

The loop filter 120 serves to bring the reference phase forward or backward according to the phase difference detected by the phase detection unit 100 to make it into a positive phase.

The loop filter 120 may be at least one of a passive delay-lead filter, an active delay-lead filter, and an active PI filter. The difference between the delay filter and the lead filter depends on the number of poles and zeros of the transfer function. The delay filter is used when the order of the denominator is greater than the order of the numerator in the transfer function, and the lead filter is the order of the denominator. Used when greater than The difference between a passive filter and an active filter is distinguished by a change in bandwidth due to a difference in time constant value. The bandwidth of the active filter is wider than that of the passive filter. The active PI filter is an ideal filter form that is theoretically possible but practically impossible in practical terms.

The oscillator 130 adjusts the voltage, multiplies the output signal of the loop filter 120 by a constant coefficient, and then generates a voltage capable of producing the same signal as the input signal by using Laplace transform. Outputs the same signal as the signal.

Hereinafter, the operation of the PLL having the configuration as shown in FIG. 1 will be described.

The input signal transmitted from the trunk of T1 (1.544 Mbps) or E1 (2.048 Mbps) is slightly out of the reference range defined at the reference frequency. This phenomenon occurs because the period of the signal is unstable due to noise, jitter, and intersymbol interference.

The phase difference of the input signal is detected through the phase detector 100, and the frequency corrector 110 detects a frequency difference between the input signal and the output signal of the oscillator 130. The detected frequency and phase are transmitted to the loop filter 120 in one signal. The loop filter 120 adjusts phase and frequency by applying an adaptive filter theory to obtain an appropriate transfer function through a filter implemented with an algorithm suitable for a system.

With proper filtering, the signal is converted into an analog signal through a digital-to-analog converter. The reason for this process is that the signal input to the oscillator 130 has to change the analog signal to the appropriate voltage value. The oscillator 130 receives a voltage corresponding to the input analog signal and outputs a signal having the same frequency and phase as the input signal.

However, since the frequency correction is performed in the conventional PLL, the structure of the PLL has a complicated inconvenience.

In addition, there are problems that it is difficult to find the most stable signal when several kinds of clock signals are input.

Accordingly, an object of the present invention is to provide an input signal selection method and apparatus of a private exchange capable of simultaneously selecting a method for selecting an input signal input to a PLL and a method for detecting a frequency difference between signals in a frequency correction block.

Another object of the present invention is to provide a method and apparatus for selecting an input signal of a private exchange that can determine whether the input signal falls within a predetermined reference range and select the input signal frequency according to a predetermined reference.

It is still another object of the present invention to provide a method and apparatus for selecting an input signal of a private exchange that can make frequency correction easier and simplify the structure of a PLL.

It is still another object of the present invention to provide a method and apparatus for selecting an input signal of a private exchange that can easily find a most stable signal and maintain a more stable system even when various types of clock signals are introduced.

1 is a schematic representation of a PLL.

2 is a diagram illustrating a selection of clocks according to priorities according to a preferred embodiment of the present invention.

3 shows an apparatus for selecting an input signal in a private exchange according to a preferred embodiment of the present invention.

4 is a flow diagram illustrating a method for selecting an input signal of a private exchange in accordance with one preferred embodiment of the present invention.

5A illustrates the operation of a mux for selecting an input signal in accordance with one preferred embodiment of the present invention.

FIG. 5B is a flow chart briefly showing the operation of a mux by priority of the input signal of FIG. 5A in accordance with another preferred embodiment of the present invention. FIG.

6 is a flowchart illustrating a frequency detection method required for frequency correction according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: phase detection unit 110: frequency correction unit

120: loop filter 130, 330: oscillator

300: calculator 301: CKM

302: DTC 303: UTP

310: mux 320: PLL

According to an aspect of the present invention to achieve the above object, in the method for selecting one input signal from among a plurality of input signals input to an oscillator, a PLL equipped private exchange, the plurality of input signals of the oscillator Count each of the output signal frequency and compare with the reference frequency of the PLL, extract the counted value of the input signal having the highest priority among the counted values, and extract the counted value from a predetermined reference range for a predetermined time. If it is determined that the error is out of the error, and the extracted counted value does not deviate from a predetermined reference range for a predetermined time or more, the input signal of the private exchange which selects and transmits the input signal corresponding to the extracted count value to the PLL. It may provide a method of selection.

Determining whether or not the extracted counted value deviates from the predetermined reference range for a predetermined time or more includes: counting an input signal having a next priority when the extracted counted value deviates from the predetermined reference range for a predetermined time or more The extracted count value, and determine whether the extracted counted value is out of a predetermined reference range for a predetermined time or more, and if the extracted counted value does not deviate from a predetermined reference range for a predetermined time or more, the extracted count. An input signal corresponding to the value can be transmitted.

The average value may be a frequency required for frequency correction.

According to another aspect of the present invention, an apparatus for selecting one input signal from among a plurality of input signals input to a PLL and a private exchange having an oscillator, wherein the plurality of input signals are counted with an output signal frequency of the oscillator, respectively. An operation unit for comparing time with the reference frequency of the PLL, checking whether the counted value exceeds a predetermined reference range, and calculating time information over the reference range, and counting an input signal having a higher priority among the counted values. It is possible to provide an input signal selection device of a private exchange including a mux for extracting a value, checking whether the extracted value is out of a predetermined reference range for a predetermined time, and selecting an input signal according to the result. .

The mux extracts a counted value of an input signal having a next priority when the extracted counted value is out of a predetermined reference range for a predetermined time, and extracts the counted value of the input signal having a predetermined reference range for a predetermined time. If the error is not corrected, an input signal corresponding to the extracted count value is transmitted to the PLL.

The reference frequency of the PLL is obtained by counting a signal transmitted from the mux, and then averaging the collected value for a predetermined time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a clock selection according to priority according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the input to the private exchange is an 8KHz synchronous clock (hereinafter referred to as DTC8K) received from T1 or E1, an 8KHz clock (hereinafter referred to as UTP8K) received from UTP (Unshield Twist Pair), and CKM (Clock). 2MHz synchronization clock (hereinafter referred to as CKM2M) received from the module, and 8KHz (hereinafter referred to as ACT8K) received from the Local Switch Module (LSM) which is ACTOWN.

The private exchange selects at least one of the input signals to produce a base clock synchronized with the input signal at the PLL.

Looking at the priority of the signal input to the private exchange, it may be the order of CKM2M, DTC 8K, UTP 8K, ACT8K, master clock. Accordingly, the private exchange receives an input of the next priority when a signal having a high priority does not come in corresponding to the above priority.

If the signal with the highest priority comes into an unstable state over a predetermined reference range, the whole system becomes unstable. Therefore, a signal of the next priority is selected to check and input whether the selected signal exceeds the reference range. By selecting a signal using the above method at each signal input end, an accurate input signal can be obtained and a more stable system can be maintained.

3 is a diagram illustrating an apparatus for selecting an input signal in a private exchange according to an exemplary embodiment of the present invention.

Referring to FIG. 3, an apparatus for selecting an input signal in a private exchange includes an operation unit 300, a mux 310, a PLL 320, and an oscillator 330.

The calculator 300 counts an input signal and an output signal frequency of the oscillator 330, and then compares the counted value with a reference frequency of the PLL 320.

The operation unit 300 may include a CKM 301, a DTC 302, and a UTP 303.

That is, the CKM 301 receives the input CKM8K and counts the output signal frequency of the oscillator 330. Then, the CKM 301 compares the counted value with the reference frequency of the PLL 320, and then selects at least one of the plurality of output lines and transmits the result of the comparison operation to the mux 310.

For example, suppose that the reference time over which the counted value exceeds a predetermined reference range is one hour. The CKM 301 checks whether the counted value exceeds a predetermined reference range. If the counted value exceeds the reference range, the CKM 301 extracts time information beyond the reference range and transmits the time information to the MUX 310.

That is, if the counted value does not deviate from the reference range, the counted value is transmitted to 301a, and if the reference range deviates from 1 hour to 2 hours, the counted value is transmitted to 301b and the reference range is 2 If out of time-3 hours, the counted value is sent to 301c. Further, if the counted value is out of the reference range for 3 hours to 4 hours, the counted value is transmitted to 301d, and if the counted value is out of the reference range for 4 hours or more, the counted value is transmitted to 301e.

The DTC 302 and the UTP 303 also transmit a signal to the mux 310 in the same manner as the CKM 301.

The MUX 310 extracts a counted value of the input signal having a high priority from the signal transmitted from the operation unit 300. Then, the MUX 310 checks whether the extracted counted value is out of a predetermined reference range for a predetermined time or more, and if the extracted counted value does not deviate from the reference range for a predetermined time or more, the extracted count value. Transmits an input signal corresponding to the PLL 320.

If the extracted counted value is out of a reference range for a predetermined time or more, the MUX 310 extracts a counted value of an input signal having a next priority.

The PLL 320 counts and stores a signal transmitted from the mux 320 every cycle. Then, the PLL 320 collects the stored counted values for a predetermined time, averages them, and extracts the averaged values as frequencies required for frequency correction.

4 is a flowchart illustrating a method for selecting an input signal of a private exchange according to a preferred embodiment of the present invention.

Referring to FIG. 4, a plurality of input signals are respectively counted with an output signal frequency of an oscillator (S400). Thereafter, the counted value is compared with the reference frequency of the PLL (S401). After the execution of the step 401, the counted value of the highest priority is extracted (S402). After performing step 402, it is determined whether the extracted counted value is out of a predetermined reference range for a predetermined time or more (S403).

If it is determined in step 403 that the extracted counted value does not deviate from a predetermined reference range for a predetermined time or more, an input signal corresponding to the extracted counted value is transmitted to the PLL (S404).

If it is determined in step 403 that the extracted counted value is out of a predetermined reference range for a predetermined time or more, the counted value of the input signal having the next priority is extracted (S405).

After performing step 405, step 403 is performed to extract an input signal to be transmitted to the PLL.

5A is a diagram illustrating the operation of a mux for selecting an input signal according to an exemplary embodiment of the present invention.

First, in order to supply a stable clock in a private exchange, a predetermined reference range is selected. When a signal comes within the reference range, it is called a normal mode, and when it comes out of this range, it is called a holdover mode.

CKL_D is a clock detection indication signal and is a signal for determining whether a CKM clock source is input. CKM_P is a signal that determines whether the CKM clock source is within a predetermined reference range at the reference frequency.

DTC_D is a clock sensing indication signal and is a signal for determining whether a DTC clock source is input. DTC_P is a signal that determines whether the DTC clock source is within a predetermined reference range at the reference frequency.

UTP_D is a clock detection instruction signal that determines whether or not a UTP clock signal is received. UTP_P is a signal that determines whether the UTP clock source is within a predetermined reference range at the reference frequency.

Here, it is assumed that the CKM_D, CKM_P, DTC_D, DTC_P, UTP_D, and UTP_P are signals operated when Low or 0, and will be described with reference to the CKM general mode and the CKM residual mode.

Timer 1 is a timer that starts to operate when the clock detection indication signal goes high. Timer 2 is a timer that starts to operate when at least one of CKM_P, DTC_P, and UTP_P becomes High because the clock source is out of a predetermined reference range.

Timer 3 is a stability compensation timer that is a timer that is different from the response time and prevents sudden transitions due to timing differences.

Referring to FIG. 5A, when the CKM clock source is input in the CKM normal mode (CKM_D = 0), and the CKM clock source is within a predetermined allowable range at the reference frequency (CKM_P = 0), the CKM normal mode is left as it is. Accordingly, the signal transmitted to the PLL may be a CKM clock source in the CKM normal mode.

If the CKM clock source is input in the CKM normal mode (CKM_D = 0), and the CKM clock source exceeds a predetermined allowable range at the reference frequency (CKM_P = 1), the CKM normal mode is converted to the CKM residual mode. When the CKM residual mode is converted as described above, it is checked whether the CKM clock source is out of a predetermined reference range for a predetermined time.

If the CKM clock source does not deviate from a predetermined reference range for a predetermined time or more, the CKM clock source is transmitted to the PLL.

If the CKM clock source is out of a predetermined reference range for a predetermined time or more, a signal having a value within a reference range having a next priority is transmitted to the PLL. That is, the DTC clock having the next priority of the CKM clock source is inspected, and if the DTC clock has a value within the reference range, the DTC clock is transmitted to the PLL.

If the value of the DTC clock exceeds the reference range when the value of the DTC clock is out of the reference range for a predetermined time or more, the UTP clock is inspected. If the UTP clock has a value within the reference range, the UTP clock is transmitted to the PLL.

If the value of the DTC clock exceeding a reference range deviates by a predetermined time or more as a result of the inspection of the UTP clock, the CKM clock is transmitted to the PLL by priority.

When the CKM clock source enters the CKM residual mode (CKM_D = 0) and the CKM clock source falls within the allowable range defined at the reference frequency (CKM_P = 0), the CKM residual mode is converted to the CKM normal mode. At this time, the CKM clock is transmitted to the PLL.

In CKM residual mode, the time when the CKM clock source is out of the tolerance range is less than the maximum (C timer 2 <mAx), or the time when CKM_D is high is more than the maximum (C timer 1> = Max), or the CKM clock source is allowed. The time outside the threshold of the range is greater than or equal to the maximum (CTimer2> = mAx), the DTC clock source comes in beyond the specified tolerance at the reference frequency (DTC_P = 1), and the UTP clock source exceeds the tolerance specified in the reference frequency. When it enters (UTP_P = 1), it goes into the remaining mode. At this time, the CKM clock source of the CKM residual mode having the highest priority according to the priority is transmitted to the PLL. Herein, the Max, mAx, and maX may have different values.

When C timer 1> = Max, or C timer 2> = mAx and D timer 3> = maX in the CKM residual mode, the CKM residual mode is converted to the DTC normal mode. At this time, the DTC clock source of the DTC normal mode is transmitted to the PLL.

In the CKM residual mode, if C timer 1> = Max, C timer 2> = mAx, U timer 3> = maX, DTC_P = 1, UTP_P = 0, the CKM residual mode is converted to the UTP normal mode. At this time, the UTP clock source of the UTP normal mode is transmitted to the PLL.

When the CKM clock source deviates from the predetermined reference range for a predetermined time or more, the DTC clock source enters the DTC normal mode (DTC_D = 0), and the DTC clock source falls within the allowable range defined at the reference frequency (DTC_P = 0). DTC normal mode is the same as DTC normal mode. Accordingly, the signal transmitted to the PLL may be a DTC clock source of the DTC normal mode.

If the CKM clock source is out of a predetermined reference range for a predetermined time, the DTC clock source comes in in the DTC normal mode (CKM_D = 0), and the DTC clock source exceeds the allowable range defined at the reference frequency (DTC_P = 1). DTC normal mode is converted to DTC residual mode. When the DTC residual mode is converted as described above, it is checked whether the DTC clock source is out of a predetermined reference range for a predetermined time.

If the DTC clock source does not deviate from a predetermined reference range for a predetermined time or more, the DTC clock source is transmitted to the PLL.

If the DTC clock source is out of a predetermined reference range for a predetermined time or more, a signal having a value within a reference range having a next priority is transmitted to the PLL. That is, the UTP clock having the next priority of the DTC clock source is examined and the UTP clock is transmitted to the PLL when the UTP clock has a value within a reference range.

If, as a result of the inspection of the UTP clock, a value exceeding a reference range of the UTP clock is out of a predetermined time or more, the CKM clock is transmitted to the PLL by priority.

If the CKM clock source is out of the predetermined reference range for a predetermined time, the DTC clock source is entered in the DTC residual mode (DTC_D = 0), and the DTC clock source is within the allowable range defined at the reference frequency (DTC_P = 0). The DTC residual mode is converted to the DTC normal mode. At this time, the DTC clock is transmitted to the PLL.

In DTC residual mode, the time when the DTC clock source deviates from the tolerance range is less than the maximum (D timer 2 <mAx), or the time when DTC_D is high is greater than the maximum (D timer 1> = Max), or the DTC clock source is allowed If the time out of range is greater than the maximum value (Dtimer2> = mAx), and the UTP clock source enters the allowable range from the reference frequency (UTP_P = 1), it remains in DTC residual mode. At this time, the DTC clock source of the DTC residual mode is transmitted to the PLL.

If D timer 1> = Max or D timer 2> = mAx, U timer 3> = maX and UTP_P = 0 in the DTC residual mode, the DTC residual mode is converted to the UTP normal mode. At this time, the UTP clock source of the UTP normal mode is transmitted to the PLL.

When the CKM clock source and the DTC clock source are out of a predetermined reference range for a predetermined time, the UTP clock source is entered in UTP normal mode (UTP_D = 0), and the UTP clock source is within the allowable range defined at the reference frequency (UTP_P). = 0), the UTP normal mode is the UTP normal mode as it is. Accordingly, the signal transmitted to the PLL may be a UTP clock source of the UTP normal mode.

If the CKM clock source and the DTC clock source are out of the predetermined reference range for more than a predetermined time, the UTP clock source enters in UTP normal mode (UTP_D = 0), and the UTP clock source exceeds the allowable range defined at the reference frequency (UTP_P = 1), the UTP normal mode is converted to the UTP residual mode. When the UTP residual mode is converted as described above, it is determined whether the UTP clock source is out of a predetermined reference range for a predetermined time.

If the UTP clock source does not deviate from a predetermined reference range for more than a predetermined time, the UTP clock source is transmitted to the PLL.

If, as a result of the inspection of the UTP clock, a value exceeding a reference range of the UTP clock is out of a predetermined time or more, the CKM clock is transmitted to the PLL by priority.

When the CKM clock source and the DTC clock source deviate from the predetermined reference range for a predetermined time or more, the UTP clock source enters the UTP residual mode (UTP_D = 0), and the UTP clock source falls within the allowable range defined at the reference frequency (UTP_P). = 0), the UTP residual mode is converted to the UTP normal mode. At this time, the UTP clock is transmitted to the PLL.

In the UTP residual mode, if the UTP clock source deviates from the allowable range of the reference value is less than the maximum value (Utimer 2 <mAx), the UTP residual mode remains as it is. At this time, the UTP clock source of the UTP residual mode is transmitted to the PLL.

FIG. 5B is a flow chart briefly showing the operation of the mux by the priority of the input signal of FIG. 5A according to another preferred embodiment of the present invention.

The CKM normal mode signal value, CKM residual mode signal value, DTC general mode signal value, DTC residual mode signal value, UTP normal mode signal value, and UTP residual mode signal value correspond to the input signal of each mode with the output signal frequency of the oscillator. This will be described as a counted value.

Referring to FIG. 5B, it is determined whether the CKM normal mode signal value is out of a predetermined reference range for a predetermined time or more (S500).

If it is determined in step 500 that the CKM normal mode signal value does not deviate from the predetermined reference range for a predetermined time or more, the CKM normal mode signal is transmitted to the PLL (S501).

If it is determined in step 500 that the CKM general mode signal value deviates from the predetermined reference range for a predetermined time or more, it is determined whether the CKM residual mode signal value deviates from the predetermined reference range for a predetermined time or longer (S502).

If it is determined in step 500 that the CKM residual mode signal value does not deviate from the predetermined reference range for a predetermined time or more, the CKM residual mode signal is transmitted to the PLL (S503).

If it is determined in step 502 that the CKM residual mode signal value deviates from the predetermined reference range for a predetermined time or more, it is determined whether the DTC general mode signal value deviates from the predetermined reference range for a predetermined time or longer (S504).

If it is determined in step 504 that the DTC normal mode signal value does not deviate from the predetermined reference range for a predetermined time or more, the DTC normal mode signal is transmitted to the PLL (S505).

If it is determined in step 504 that the DTC general mode signal value deviates from the predetermined reference range for a predetermined time or more, it is determined whether the DTC residual mode signal value deviates from the predetermined reference range for a predetermined time or longer (S506).

If it is determined in step 506 that the DTC residual mode signal value does not deviate from the predetermined reference range for a predetermined time or more, the DTC residual mode signal is transmitted to the PLL (S507).

If it is determined in step 506 that the DTC residual mode signal value is out of a predetermined reference range for a predetermined time or more, it is determined whether the UTP normal mode signal value is out of a predetermined time or more (S508).

If it is determined in step 508 that the UTP normal mode signal value does not deviate from the predetermined reference range for a predetermined time or more, the UTP normal mode signal is transmitted to the PLL (S509).

If it is determined in step 508 that the UTP normal mode signal value deviates from the predetermined reference range for a predetermined time or more, it is determined whether the UTP residual mode signal value deviates from the predetermined reference range for a predetermined time or longer (S510).

As a result of the determination in step 510, if the UTP residual mode signal value does not deviate from the predetermined reference range for a predetermined time or more, the UTP residual mode signal is transmitted to the PLL (S511).

If it is determined in step 510 that the UTP residual mode signal value does not deviate from a predetermined reference range for a predetermined time or more, the CMK normal mode signal is transmitted to the PLL according to priority.

6 is a view showing a frequency detection method required for frequency correction according to an embodiment of the present invention.

Referring to FIG. 6, a signal input through a mux is counted every cycle (S600).

Then, after storing the counted value (S601), the stored counted value is collected and averaged for a predetermined time (S602).

After performing step 602, the average value is extracted as a frequency necessary for frequency correction (S603).

According to the present invention as described above, it is possible to provide an input signal selection method and apparatus of a private exchange which can simultaneously perform a method of selecting an input signal and a method of detecting a frequency difference between signals in a frequency correction block.

In addition, it is possible to provide a method and apparatus for selecting an input signal of a private exchange that can determine whether the input signal falls within a predetermined reference range when selecting an input signal and at the same time determine the input signal frequency according to a predetermined reference.

In addition, it is possible to provide a method and apparatus for selecting an input signal of a private exchange which can make frequency correction easier and simplify the structure of a PLL.

In addition, it is possible to provide a method and apparatus for selecting an input signal of a private exchange that can easily find the most stable signal even when various types of clock signals are input and maintain a more stable system.

Claims (8)

A method for selecting one input signal from a plurality of input signals input to an oscillator and a PLL-equipped private exchange, Counting the plurality of input signals with the output signal frequency of the oscillator and comparing the result with the reference frequency of the PLL; Extracting a counted value of a high priority input signal from the counted values; Checking whether the extracted counted value is out of a predetermined reference range for a predetermined time or more; and If the extracted counted value does not deviate from a predetermined reference range for more than a predetermined time, selecting and transmitting an input signal corresponding to the extracted counted value to the PLL Input signal selection method of a private exchange comprising a. The method of claim 1, Extracting a counted value of an input signal having a next priority when the extracted counted value is out of a predetermined reference range for a predetermined time or more; Checking whether the extracted counted value is out of a predetermined reference range for a predetermined time or more; and If the extracted counted value does not deviate from a predetermined reference range for a predetermined time or more, selecting an input signal corresponding to the extracted counted value and transmitting the selected input signal to the PLL. The method of claim 1, Computing the plurality of input signals with the output signal frequency of the oscillator and comparing with the reference frequency of the PLL Counting the plurality of input signals with an output signal frequency of the oscillator, and then comparing them with a reference frequency of the PLL; And calculating time information exceeding a reference range by checking whether the counted value has exceeded a predetermined reference range. The method of claim 1, And counting the transmitted input signal every period in the PLL and collecting the counted values for a predetermined time to average the input signals. The method of claim 4, wherein And the average value is a frequency required for frequency correction. An apparatus for selecting one input signal among a plurality of input signals input to a PLL and an oscillator, An operation unit for counting the plurality of input signals with the output signal frequency of the oscillator, comparing the PLL with a reference frequency of the PLL, and checking whether the counted value exceeds a predetermined reference range and calculating time information that exceeds the reference range. ; A mux extracts a counted value of the input signal having a higher priority from the counted values, checks whether the extracted value is out of a predetermined reference range for a predetermined time, and selects an input signal according to the result. Input signal selection device of a private exchange comprising a. The method of claim 6, The mux selects an input signal corresponding to the extracted count value if the extracted counted value does not deviate from the predetermined reference range for a predetermined time or more, and extracts the counted value for the predetermined reference range for a predetermined time or more. If it is, the input of the private exchange which extracts the counted value of the input signal having the next priority, checks whether the predetermined reference range is out of a predetermined time or more, and selects the input signal according to the result. Signal selector. The method of claim 6, The reference frequency of the PLL is input signal selection device of the private exchange, characterized in that the average of the counted value after a predetermined time after the signal transmitted from the mux.