KR100449623B1 - Method For Manufacturing Multilayer Ceramic Capacitor - Google Patents
Method For Manufacturing Multilayer Ceramic Capacitor Download PDFInfo
- Publication number
- KR100449623B1 KR100449623B1 KR10-2001-0067854A KR20010067854A KR100449623B1 KR 100449623 B1 KR100449623 B1 KR 100449623B1 KR 20010067854 A KR20010067854 A KR 20010067854A KR 100449623 B1 KR100449623 B1 KR 100449623B1
- Authority
- KR
- South Korea
- Prior art keywords
- ceramic capacitor
- external electrode
- multilayer ceramic
- calcining
- binder
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title abstract description 14
- 238000010304 firing Methods 0.000 claims abstract description 29
- 239000011230 binding agent Substances 0.000 claims abstract description 20
- 239000002003 electrode paste Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000012298 atmosphere Substances 0.000 claims abstract description 8
- 239000002904 solvent Substances 0.000 claims abstract description 8
- 238000005520 cutting process Methods 0.000 claims abstract description 5
- 238000003825 pressing Methods 0.000 claims abstract description 3
- 238000001354 calcination Methods 0.000 claims description 12
- 239000001913 cellulose Substances 0.000 claims description 4
- 229920002678 cellulose Polymers 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- 239000001856 Ethyl cellulose Substances 0.000 claims description 2
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical group CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 claims description 2
- 229920001249 ethyl cellulose Polymers 0.000 claims description 2
- 235000019325 ethyl cellulose Nutrition 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 abstract description 9
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 230000000052 comparative effect Effects 0.000 description 14
- 238000007747 plating Methods 0.000 description 13
- 239000000843 powder Substances 0.000 description 10
- 238000007796 conventional method Methods 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 6
- 239000002002 slurry Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 238000010030 laminating Methods 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005245 sintering Methods 0.000 description 3
- 229910018125 Al-Si Inorganic materials 0.000 description 2
- 229910018520 Al—Si Inorganic materials 0.000 description 2
- 238000002788 crimping Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001027 hydrothermal synthesis Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229920005822 acrylic binder Polymers 0.000 description 1
- -1 and various oxides Substances 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
- H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/008—Selection of materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
본 발명은 적층세라믹 캐패시터를 제조하는 방법에 관한 것으로서, Cu 내부전극을 사용하는 저온소성 MLCC의 세라믹 소체, 내부전극 및 외부전극을 동시에 소성함으로써 공정을 단순화시키고, 외부전극의 접착강도 및 접촉성을 향상시킬 수 있는 MLCC의 제조방법을 제공하고자 하는데, 그 목적이 있는 것이다.The present invention relates to a method for manufacturing a laminated ceramic capacitor, which simplifies the process by simultaneously firing a ceramic body, an internal electrode and an external electrode of a low-temperature calcined MLCC using a Cu internal electrode, and thus the adhesive strength and contactability of the external electrode. It is to provide a method of manufacturing MLCC that can be improved, which is the purpose.
본 발명은 Cu 내부전극이 인쇄된 유전체 시트를 적층, 압착, 및 절단하여 제조된 그린 칩의 양단에 Cu 금속: 40∼70wt%, 공재: 5∼20wt% , 결합제: 1.6 ∼5.6wt% 및 나머지 솔벤트로 이루어지는 외부전극 페이스트를 도포하고, 가소한 다음, 환원분위기하에서 870∼1000℃의 온도에서 내부전극 및 외부전극을 위한 소성을 행하는 적층세라믹 캐패시터의 제조방법을 그 요지로 한다.According to the present invention, Cu metal: 40 to 70 wt%, common material: 5 to 20 wt%, binder: 1.6 to 5.6 wt%, and the rest of the green chip manufactured by stacking, pressing, and cutting a dielectric sheet printed with Cu internal electrodes. The main point is a method for producing a laminated ceramic capacitor which is coated with an external electrode paste made of solvent, calcined, and then calcined for the internal electrode and the external electrode at a temperature of 870 to 1000 ° C. under a reducing atmosphere.
Description
본 발명은 적층세라믹 캐패시터를 제조하는 방법에 관한 것으로서, 보다 상세하게는 내외부전극을 동시에 소성하여 적층세라믹을 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a laminated ceramic capacitor, and more particularly, to a method of manufacturing a laminated ceramic by simultaneously firing internal and external electrodes.
적층 세라믹 캐패시터(MLCC; 이하, 단순히 "MLCC"라고도 칭함)는 DC 신호 차단, 바이패싱(bypassing), 주파수 공진 등의 기능으로 활용되고 있으며, 온도 특성 별로분류되고 있다.Multilayer ceramic capacitors (MLCCs, hereinafter simply referred to as "MLCCs") are used as functions such as DC signal blocking, bypassing, and frequency resonance, and are classified according to temperature characteristics.
상기 MLCC는 전자제품의 소형화, 경량화의 요구에 따라 사용량이 증가되어 왔으며, 최근 전자제품의 디지탈화와 이동통신 시장의 확대에 따라 폭발적인 수요가 창출되고 있다.The use of MLCC has been increased in accordance with the demand for miniaturization and light weight of electronic products, and explosive demand has been created due to the digitalization of electronic products and the expansion of the mobile communication market.
상기 MLCC는 그린 시트(green sheet)에 전극 페이스트(paste)를 인쇄, 다층으로 적층하고 절단(cutting)한 후 고온으로 소결한 다음, 외부전극을 도포, 소결하여 도금하는 공정으로 제조된다.The MLCC is manufactured by printing an electrode paste on a green sheet, laminating it in multiple layers, cutting and sintering at a high temperature, and then applying, sintering and plating an external electrode.
종래에는 내환원성 유전체 조성물로 된 유전체층과 Cu내부 전극층을 교대로 적층한 세라믹 캐패시터 본체를 소성한 후, 그 양단부에 Glass Frit과 Cu금속을 주성분으로 하는 외부전극을 도포한 후, 다시 소성을 행하므로써 적층세라믹 캐패시터를 제조하였다.Conventionally, after firing a ceramic capacitor body in which a dielectric layer made of a reducing-resistant dielectric composition and a Cu inner electrode layer are alternately laminated, an outer electrode mainly composed of Glass Frit and Cu metal is applied to both ends thereof, and then fired again. A laminated ceramic capacitor was prepared.
MLCC를 제조하는 종래방법의 대표적인 예를 제시한 도 1을 통해 MLCC를 제조하는 방법에 대하여 설명하면 다음과 같다.Referring to Figure 1 showing a representative example of a conventional method for manufacturing MLCC will be described with respect to the method for manufacturing MLCC.
즉, 종래의 MLCC 제조방법은 도 1에 나타난 바와 같이, Ca(TixZr1-x)O3, MnO, 및 Glass Frit의 분말을 준비하는 단계, 준비된 분말을 슬러리화 하는 단계, 상기 슬러리를 유전체 시트로 성형하는 단계, 유전체 시트에 Cu내부전극을 인쇄하는 단계, 내부전극이 인쇄된 시트를 적층하는 단계, 및 적층된 시트를 500 ∼ 1300kgf/cm2의 압력으로 압착하는 단계, 압착된 적층시트를 절단하여 그린 칩을 제조하는 단계,상기와 같이 제조된 그린 칩을 230 ∼ 350℃의 온도 및 PO2=10-6∼Air의 압력조건에서 20∼40시간동안 가소(burn-out)시키는 단계, 900∼ 950℃의 온도 및 PO2=10-15∼10-10의 압력조건에서 10시간동안 소성시키는 단계, 및 외부전극을 도포한 후, 750∼ 950℃의 온도 및 PO2=10-15∼10-6의 압력조건에서 0.5 ∼ 2시간동안 소성한 후, 도금하는 단계를 포함하여 구성된다.That is, in the conventional MLCC manufacturing method, as shown in FIG. 1, preparing a powder of Ca (Ti x Zr 1-x ) O 3 , MnO, and Glass Frit, slurrying the prepared powder, and preparing the slurry Molding into a dielectric sheet, printing a Cu internal electrode on the dielectric sheet, laminating a sheet with an internal electrode printed thereon, and compressing the laminated sheet at a pressure of 500 to 1300 kgf / cm 2 , compressing the lamination A method of manufacturing a green chip by cutting a sheet, burn-out of the green chip manufactured as described above for 20 to 40 hours at a temperature of 230 to 350 ° C. and a pressure condition of P O 2 = 10 −6 to Air. Firing at a temperature of 900 to 950 ° C. and a pressure condition of P O 2 = 10 −15 to 10 −10 for 10 hours, and after applying the external electrode, a temperature of 750 to 950 ° C. and a P O 2 = 10 − After baking for 0.5 to 2 hours at a pressure of 15 ~ 10 -6 , it comprises a step of plating.
상기한 바와 같이, 종래에는 내부전극을 위한 소성과 외부전극을 위한 소성이 별도로 행하여졌다.As described above, the firing for the internal electrode and the firing for the external electrode have been conventionally performed separately.
즉, 도 2(a)에 나타난 바와 같이, 세라믹 소체(1)에 내부전극(2)을 인쇄한 후 내부전극을 위한 1차 소성을 행한 다음, 도 2(b)에 나타난 바와 같이, 내부전극(2)이 형성된 세라믹 소체(1)의 양 단부에 외부전극(3)을 형성한 후, 2차소성을 행하였다.That is, as shown in Fig. 2 (a), after the internal electrode (2) is printed on the ceramic body (1) and subjected to the primary firing for the internal electrode, as shown in Fig. 2 (b), the internal electrode After the external electrodes 3 were formed at both ends of the ceramic body 1 on which (2) was formed, secondary firing was performed.
그러나, 종래와 같이, 내부전극을 위한 1차 소성후에 외부전극을 부착하는 경우에는 소성이 1, 2차로 행해지므로, 소성시간이 길어 생산성이 떨어질 뿐만 아니라 이미 소성된 것에 전극을 부착하게 되므로, 반응성이 떨어지고 이로 인하여 접촉성 및 접착강도가 저하되는 문제점이 있다.However, in the case of attaching the external electrode after the primary firing for the internal electrode as in the related art, since the firing is performed first and second, the firing time is long, the productivity is lowered, and the electrode is attached to the already fired. There is a problem that falls and thereby the contact and adhesive strength is lowered.
본 발명자들은 상기한 종래방법의 제반 문제점을 해결하기 위하여 연구 및 실험을행하고, 그 결과에 근거하여 본 발명을 제안하게 된 것으로서, 본 발명은 Cu 내부전극을 사용하는 저온소성 MLCC의 세라믹 소체, 내부전극 및 외부전극을 동시에 소성함으로써 공정을 단순화시키고, 외부전극의 접착강도 및 접촉성을 향상시킬 수 있는 MLCC의 제조방법을 제공하고자 하는데, 그 목적이 있는 것이다.The present inventors have conducted research and experiments to solve the above-mentioned problems of the conventional method, and based on the results, the present invention proposes a ceramic body of a low-temperature calcined MLCC using Cu internal electrodes. It is an object of the present invention to simplify a process by simultaneously firing an electrode and an external electrode, and to provide a method for manufacturing an MLCC that can improve adhesion strength and contactability of an external electrode.
도 1은 종래방법에 따라 적층세라믹 캐패시터를 제조하는 공정을 나타내는 공정 순서도1 is a process flowchart showing a process of manufacturing a laminated ceramic capacitor according to a conventional method.
도 2는 종래방법에 따르는 소성공정을 설명하기 위한 적층세라믹 캐패시터의 개략도로서, (a)는 1차 소성전의 상태를 나타내고, (b)는 2차 소성전의 상태를 나타냄.도 3은 본 발명에 따르는 동시소성공정을 설명하기 위한 적층세라믹 캐패시터의 개략도Fig. 2 is a schematic diagram of a laminated ceramic capacitor for explaining the firing process according to the conventional method, in which (a) shows the state before the primary firing, and (b) shows the state before the secondary firing. Schematic diagram of laminated ceramic capacitors to illustrate the simultaneous firing process
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 . . . 세라믹 소체 2 . . . 내부전극 3 . . . 외부전극One . . . Ceramic body 2. . . Internal electrode 3. . . External electrode
이하, 본 발명에 대하여 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated.
본 발명은 성형된 유전체 시트에 Cu 내부전극을 인쇄하고, 내부전극이 인쇄된 유전체 시트를 적층, 압착, 및 절단하여 그린 칩을 제조하는 단계;The present invention includes the steps of printing a Cu internal electrode on a molded dielectric sheet, laminating, pressing, and cutting a dielectric sheet on which the internal electrode is printed to manufacture a green chip;
Cu 금속: 40∼70wt%, 공재: 5∼20wt% , 결합제: 1.6 ∼5.6wt% 및 나머지 솔벤트로 이루어지는 외부전극 페이스트를 제조하는 단계;Preparing an external electrode paste composed of 40 to 70 wt% of Cu metal, 5 to 20 wt% of common material, 1.6 to 5.6 wt% of binder, and remaining solvent;
상기 그린 칩을 가소하기 전에 상기 그린 칩의 양단에 상기와 같이 제조된 외부전극 페이스트를 도포하는 단계; 및Applying the external electrode paste prepared as described above to both ends of the green chip before calcining the green chip; And
상기와 같이 외부전극 페이스트를 도포한 후에 가소한 다음, 환원분위기하에서 870∼1000℃의 온도에서 내부전극 및 외부전극을 위한 소성을 행하는 단계를 포함하여 구성되는 적층세라믹 캐패시터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a multilayer ceramic capacitor, comprising the step of calcining after applying the external electrode paste as described above, and then firing the internal electrode and the external electrode at a temperature of 870 to 1000 ° C. under a reducing atmosphere.
이하, 본 발명에 대하여 상세히 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail.
본 발명에 따라 적층세라믹 캐패시터를 제조하기 위해서는 우선 Ca(TixZr1-x)O3, MnO, 및 Glass Frit의 유전체 분말을 준비한다.In order to manufacture a multilayer ceramic capacitor according to the present invention, first , dielectric powders of Ca (Ti x Zr 1-x ) O 3 , MnO, and Glass Frit are prepared.
상기 Ca(TixZr1-x)O3로는 수열합성법등으로 합성한 CaZrO3, CaTiO3등을 사용하는 것이바람직하며, 상기 Ca(TixZr1-x)O3에서 x는 0.01≤x≤0.1로 설정하는 것이 바람직하다.As Ca (Ti x Zr 1-x ) O 3 , CaZrO 3 or CaTiO 3 synthesized by hydrothermal synthesis or the like is preferably used. In Ca (Ti x Zr 1-x ) O 3 , x is 0.01 ≦ x. It is preferable to set ≤ 0.1.
상기 MnO의 첨가량은 1.0-5.0wt%가 되도록 설정하는 것이 바람직하다.The amount of MnO added is preferably set to 1.0-5.0 wt%.
상기 Glass Frit는 Ca-Li-B-Al-Si계 산화물이 바람직하며, 그 첨가량은 1.0 - 5.0wt%로 설정하는 것이 바람직하다.The glass frit is preferably a Ca-Li-B-Al-Si-based oxide, and the amount of the glass frit is preferably set to 1.0 to 5.0 wt%.
다음에, 상기와 같이 준비된 유전체 분말을 배치공정에서 슬러리화 한다.Next, the dielectric powder prepared as described above is slurried in a batch process.
상기 유전체 슬러리는 유전체 분말과 유기바인더, 용제를 혼합한 것으로서, 유기바인더는 PVB, 아크릴등의 각종 바인더로부터 적절히 선택할 수 있다.The dielectric slurry is a mixture of a dielectric powder, an organic binder, and a solvent, and the organic binder can be appropriately selected from various binders such as PVB and acrylic.
다음에, 상기 유전체 슬러리를 유전체 시트로 성형한다.Next, the dielectric slurry is molded into a dielectric sheet.
다음에, 상기 유전체 시트에 Cu 내부전극을 인쇄하고, 내부전극이 인쇄된 시트를 적층한 다음, 적층된 시트를 압착한 후, 압착된 적층시트를 정해진 형상에 따라 절단하여 그린칩을 제조한다.Next, a Cu internal electrode is printed on the dielectric sheet, a sheet on which the internal electrode is printed is laminated, and the laminated sheet is compressed, and then the compressed laminated sheet is cut according to a predetermined shape to manufacture a green chip.
상기 Cu 내부전극용 페이스트는 도전성 금속인 Cu와 각종산화물, 바인더, 용제를 혼합하여 제조한다The Cu internal electrode paste is prepared by mixing Cu, a conductive metal, and various oxides, binders, and solvents.
상기 압착시, 압착압력은 500 ∼ 1300kgf/cm2로 설정하는 것이 바람직하다.In the crimping, the crimping pressure is preferably set to 500 to 1300 kgf / cm 2 .
다음에, 상기와 같이 제조된 그린칩을 그린연마하여 모서리부분을 곡면으로 만든 후 양단에 외부전극페이스트를 도포한다.Next, the green chip manufactured as described above is green polished to make the corner portion curved, and then external electrode paste is applied to both ends.
상기 외부전극 페이스트는 Cu 금속: 40∼70wt%, 공재: 5∼20wt% , 결합제: 1.6∼5.6wt% 및 나머지 솔벤트로 이루어진다.The external electrode paste is composed of 40 to 70 wt% of Cu metal, 5 to 20 wt% of common material, 1.6 to 5.6 wt% of binder, and the remaining solvent.
상기 Cu 금속은 구형과 플레이크형을 단독 또는 혼합하여 사용할 수 있지만, 혼합하여 사용하는 것이 바람직하며, 보다 바람직하게는 구형/플레이크 ≥1가 되도록 구형과 플레이크형을 혼합하여 사용하는 것이다.The Cu metal may be used alone or mixed with a spherical form and a flake form, but it is preferable to use a mixture, and more preferably, a mixture of a spherical form and a flake form is used so that spherical / flakes ≧ 1.
그리고, 상기 Cu 금속은 40∼70wt%로 선정하는 것이 바람직하다.The Cu metal is preferably selected from 40 to 70 wt%.
종래방법에서와 같이 Glass Frit을 사용하는 경우에는 동시소성시간이 길어 외부전극의 소결밀도가 매우 높기 때문에 유전체와 외부전극의 수축율차이에 의해 소성후 냉각시에 유전체와 외부전극 접착부에 크랙이 발생하거나, 외부전극이 떨어지는 현상이 발생하므로, 이러한 현상을 방지하기 위하여 본 발명에서는 Glass Frit대신에 공재를 사용하게 된 것이다.In case of using glass frit as in the conventional method, the sintering density of the external electrode is very high due to the long simultaneous firing time. In order to prevent this phenomenon, the common electrode is used instead of the glass frit in order to prevent the phenomenon.
상기 공재는 세라믹과 메탈과의 수축율 차이로 인한 크랙발생등을 방지하기 위해 유전체조성과 동일 또는 유사한 조성 및 물성을 갖는 성분으로서 특성에 영향을 주지 않는 것을 선택한다.The common material is selected to not affect the properties as a component having the same or similar composition and physical properties as the dielectric composition to prevent cracking due to the difference in shrinkage between the ceramic and the metal.
상기 공재의 함량이 너무 적을 경우에는 외부전극과 세라믹의 수축율 차이에 의해 외부 전극의 들뜸이 발생하거나, 소체에 미세크랙이 발생하고, 공재의 함량이 너무 많을 경우에는 외부전극 전체표면에 공재가 차지하는 부분이 너무 많아 도금 끊김 현상이 발생하므로, 그 함량은 5∼20wt%로 선정하는 것이 바람직하다.When the content of the common material is too small, the external electrode is lifted due to the difference in shrinkage between the external electrode and the ceramic, or microcracks occur in the body, and when the content of the common material is too high, the common material occupies the entire surface of the external electrode. Since there are too many portions and plating bleeding occurs, the content thereof is preferably selected from 5 to 20 wt%.
한편, 상기 결합제로서 종래방법에서와 같이 아크릴 바인더를 사용할 경우 전단 스트레스(shear stress)변화에 따른 점도비가 커 외부전극의 도포두께가 건조후에 40-50㎛ 정도로 두꺼우므로 가소공정에서 내부전극과 유전체사이에 디라미네이션(delamination)이 발생하게 되는 것을 확인하였다.On the other hand, when the acrylic binder is used as the binder as in the conventional method, the viscosity ratio according to the change of shear stress is large and the coating thickness of the external electrode is about 40-50 μm thick after drying, so that the internal electrode and the dielectric are interposed in the plasticizing process. It was confirmed that delamination occurred in the.
이와 관련된 추가연구를 통하여 본 발명에서는 결합제로서 셀롤로오스계 바인더를 사용하는 것이 바람직하다는 것을 확인하였다..Further studies in this regard confirmed that in the present invention, it is preferable to use a cellulose binder as a binder.
즉, 셀롤로오스계 바인더를 사용할 경우 전단 스트레스의 변화에 따른 점도비가 낮아 외부전극이 얇고 균일하게 도포되어 가소가 용이하다.That is, in the case of using a cellulose-based binder, the viscosity ratio according to the change of the shear stress is low, so that the external electrode is thin and uniformly applied, so that it is easy to plasticize.
상기와 같이 셀롤로오스계 바인더를 사용할 경우 외부전극의 두께는 20-30㎛정도 이다.When using a cellulose-based binder as described above, the thickness of the external electrode is about 20-30㎛.
종래방법에서는 외부전극의 두께가 얇으면 도금시에 도금액의 침투에 의한 특성의 열화가 발생하여 외부전극의 두께가 두께워야 하나, 본 발명에서는 동시소성을 실시하므로 소성밀도가 높아 전극두께가 두꺼울 필요가 없다.In the conventional method, when the thickness of the external electrode is thin, deterioration of characteristics due to penetration of the plating solution occurs during plating, but the thickness of the external electrode should be thick. There is no.
상기 결합제로는 에칠 셀룰로오스를 사용하는 것이 바람직하다.It is preferable to use ethyl cellulose as the binder.
상기 결합제의 함량은 1.6 ∼5.6wt%로 선정하는 것이 바람직하다.The content of the binder is preferably selected to 1.6 ~ 5.6wt%.
그리고 상기 외부전극페이스트는 15,000∼40,000cps(10rpm)의 점도를 갖도록 하는 것이 바람직하다.In addition, the external electrode paste may have a viscosity of 15,000 to 40,000 cps (10 rpm).
다음에, 상기와 같이 내부전극이 인쇄되고 외부 전극이 도포된 그린 칩을 가소하여탈바인더처리한 후, 소성을 실시하여 적층세라믹 캐패시터를 제조한다.Next, as described above, the green chip on which the inner electrode is printed and the outer electrode is coated is calcined and debindered, followed by firing to manufacture a laminated ceramic capacitor.
즉, 도 3에 나타난 바와 같이, 세라믹 소체(1)에 내부전극(2) 및 외부전극(3)을 형성한 후 이들을 동시에 가소 및 소성한다.That is, as shown in FIG. 3, the internal electrode 2 and the external electrode 3 are formed in the ceramic body 1, and then they are calcined and fired simultaneously.
상기 가소는 환원성분위기하에서 200 ∼ 600℃, 바람직하게는 230 ∼ 350℃의 온도에서 5시간 이상, 바람직하게는 20 ∼ 40시간정도 행하는 것이다.The calcining is carried out at a temperature of 200 to 600 ° C., preferably 230 to 350 ° C., for at least 5 hours, preferably about 20 to 40 hours, under a reducing component atmosphere.
상기 그린 칩의 탈바인더 처리(가소)는 내부전극 및 외부전극의 산화를 막기 위하여 환원성분위기에서 행하는 것이 바람직하며, 보다 바람직한 분위기로는 질소분위기를 들수 있다.The binder removal process (calcination) of the green chip is preferably performed in a reducing component atmosphere to prevent oxidation of the internal electrode and the external electrode, and a nitrogen atmosphere is more preferable.
상기 소성시 분위기는 환원성분위기로 하고, 소성온도는 870 ∼1000℃, 바람직하게는 900∼950℃로 선정하고, 그리고 소성시간은 5시간 이상, 바람직하게는 5 ∼ 20시간, 보다 바람직하게는 9 ∼ 12시간으로 선정한다.At the time of firing, the atmosphere is a reducing component crisis, the firing temperature is selected from 870 ~ 1000 ℃, preferably 900 ~ 950 ℃, and the firing time is 5 hours or more, preferably 5 to 20 hours, more preferably 9 Select from 12 hours.
상기와 같이 소성된 후에는 Ni도금 및 Sn/Pb도금을 차례로 행하게 된다.After firing as described above, Ni plating and Sn / Pb plating are sequentially performed.
이하, 실시예를 통하여 본 발명을 보다 구체적으로 설명한다.Hereinafter, the present invention will be described in more detail with reference to Examples.
실시예Example
수열합성법등으로 합성한 CaZrO3, CaTiO3를 사용하여 Ca(Ti0.03Zr0.97)O3분말을 제조하였다.Ca (Ti 0.03 Zr 0.97 ) O 3 powder was prepared using CaZrO 3 and CaTiO 3 synthesized by hydrothermal synthesis.
상기와 같이 제조된 Ca(Ti0.03Zr0.97)O3와 Ca(Ti0.03Zr0.97)O3100중량부에 대하여 MnO 3.0wt%와 Ca-Li-B-Al-Si계 산화물인 Glass Frit 3.5wt%를 혼합하여 유전체 분말을 준비하였다.MWO 3.0wt% and Ca-Li-B-Al-Si oxide, Glass Frit 3.5wt, based on 100 parts by weight of Ca (Ti 0.03 Zr 0.97 ) O 3 and Ca (Ti 0.03 Zr 0.97 ) O 3 prepared as described above The dielectric powder was prepared by mixing%.
상기와 같이 준비된 유전체 분말과 이 유전체 분말 100중량부에 대하여 10wt%의 수지와 이 수지 대비 40wt%의 가소제와 수지 대비 8배의 솔벤트를 혼합하여 유전체 분말 슬러리를 제조하였다.The dielectric powder slurry was prepared by mixing 10 wt% of the resin, 40 wt% of the plasticizer, and 8 times the solvent of the resin with respect to the dielectric powder prepared as described above and 100 parts by weight of the dielectric powder.
상기와 같이 제조된 슬러리를 이용하여 유전체 시트를 제조하고 Cu 내부전극을 인쇄하였다.Using the slurry prepared as described above to prepare a dielectric sheet and printed Cu internal electrode.
상기와 같이 내부전극이 인쇄된 유전체 시트를 5층 적층한 후, 1000kg/mm2의 압력으로 압착한 다음, 절단하여 그린 칩을 제조하였다.After stacking five layers of dielectric sheets printed with internal electrodes as described above, the sheets were pressed at a pressure of 1000 kg / mm 2 and then cut to prepare a green chip.
상기와 같이 제조된 그린 칩의 양단에 하기 표 1과 같이 조성되는 외부전극 페이스트를 도포한 후, 질소분위기하에서 300℃에서 25시간 가소한 다음, 하기 표 1과 같은 소성온도조건으로 10시간 행하였다.After applying the external electrode paste prepared as shown in Table 1 on both ends of the green chip prepared as described above, and calcined at 300 ℃ for 25 hours under a nitrogen atmosphere, it was performed for 10 hours under the firing temperature conditions shown in Table 1 .
상기와 같이 제조된 칩의 전기적 특성을 Agilent 사의 4278A LCR meter와 4339B High resistance meter를 이용하여 품질계수(Quality Factor; Q)와 IR값을 측정하고, 테이프 시험(tape test)를 이용하여 외부전극의 접착강도를 측정하고, 그리고 도금검사를 통해 Ni도금층의 끊김을 검사하고, 그 결과를 하기 표 2에 나타내었다.The electrical characteristics of the chip manufactured as described above were measured using Agilent's 4278A LCR meter and 4339B High resistance meter to measure the quality factor (Q) and IR value, and the tape test was used to measure the external electrode. The adhesive strength was measured, and the breakage of the Ni plated layer was examined by plating test, and the results are shown in Table 2 below.
테이프 테스트는 외부전극의 접착강도를 평가하는 방법으로 본 실시예에서는 도금이 완료된 칩을 테이프에 부착한 후 떼어내어 외부전극이 떨어지는 개수로 평가하였다.The tape test is a method of evaluating the adhesive strength of the external electrode. In this embodiment, the plated chip was attached to the tape, and then peeled off, and then the number of external electrodes fell.
또한, 도금검사로는 도금이 끝난 칩을 폴리싱(polishing)하여 Ni도금의 끊김정도를 확인하는 방법을 이용하였다.In addition, the plating test was used to check the degree of breakage of Ni plating by polishing the finished chip.
상기 표 2에 나타난 바와 같이, 본 발명에 따라 제조된 발명예(1) 내지 (4)의 경우에는 Q값 및 IR값이 우수할 뿐만 아니라 도금 불량도 발생되지 않았으며, 테이프 테스트도 양호하게 나타남을 알 수 있다.As shown in Table 2, in the case of Inventive Examples (1) to (4) manufactured according to the present invention, not only the Q value and the IR value were excellent, but also no plating defect was generated, and the tape test also appeared well. It can be seen.
한편, 공재가 본 발명의 범위보다 적게 첨가된 비교예(1),(2),(4)및(5)의 경우에는 테이프테스트결과가 불량한 것들이 나타났으며, 공재가 본 발명의 범위보다 많이 첨가된 비교예(3) 및 (6)의 경우에는 도금불량이 발생함을 알 수 있다.On the other hand, in the case of Comparative Examples (1), (2), (4) and (5) in which the common material was added less than the scope of the present invention, tape test results were poor, and the common material was more than the scope of the present invention. In the case of the added Comparative Examples (3) and (6) it can be seen that the plating failure occurs.
상기에서는 내부 전극이 Cu인 경우에 대하여 설명하였지만, 본 발명은 Ni를 내부전극으로 사용하는 경우도 적용됨은 물론이다.In the above, the case where the internal electrode is Cu has been described, but the present invention is also applied to the case where Ni is used as the internal electrode.
상술한 바와 같이, 본 발명은 내외부전극의 소성이 동시에 진행되므로 외부전극을 소성하는 공정이 따로 필요가 없으므로, 외부전극소성에 의한 비용 및 리드 타임을 단축할 수 있는 효과가 있는 것이다.As described above, since the firing of the internal and external electrodes proceeds at the same time, the process of firing the external electrodes does not need to be performed separately, thereby reducing the cost and lead time due to external electrode firing.
또한, 본 발명은 특성상으로도 외부전극의 접착강도 및 내외부전극의 접촉성이 개선된 적층세라믹 캐패시터를 제공할 수 있는 효과가 있는 것이다.In addition, the present invention has an effect that can provide a laminated ceramic capacitor with improved adhesive strength of the external electrode and the contact between the internal and external electrodes.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0067854A KR100449623B1 (en) | 2001-11-01 | 2001-11-01 | Method For Manufacturing Multilayer Ceramic Capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2001-0067854A KR100449623B1 (en) | 2001-11-01 | 2001-11-01 | Method For Manufacturing Multilayer Ceramic Capacitor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030037351A KR20030037351A (en) | 2003-05-14 |
| KR100449623B1 true KR100449623B1 (en) | 2004-09-22 |
Family
ID=29567511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2001-0067854A KR100449623B1 (en) | 2001-11-01 | 2001-11-01 | Method For Manufacturing Multilayer Ceramic Capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100449623B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160071177A (en) | 2014-12-11 | 2016-06-21 | 삼성전기주식회사 | Strucutre of electrode for capacitor, electrolytic capacitor and manufacturing method thereof |
| US20220319777A1 (en) * | 2021-03-31 | 2022-10-06 | Tdk Corporation | Laminated electronic component |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102089697B1 (en) | 2014-04-30 | 2020-04-14 | 삼성전기주식회사 | paste for external electrode, multilayer ceramic electronic component and method of manufacturing the same |
| KR102392247B1 (en) | 2018-10-11 | 2022-04-29 | 가부시키가이샤 무라타 세이사쿠쇼 | Electronic component |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03145111A (en) * | 1989-10-31 | 1991-06-20 | Matsushita Electric Ind Co Ltd | Manufacture of chip component |
| JPH053131A (en) * | 1991-04-17 | 1993-01-08 | Matsushita Electric Ind Co Ltd | Multilayer ceramic capacitor and manufacture thereof |
| JP2000243650A (en) * | 1999-02-22 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Multilayer ceramic capacitor and its manufacture |
| JP2001044060A (en) * | 1999-07-30 | 2001-02-16 | Kyocera Corp | Multilayer ceramic capacitor |
-
2001
- 2001-11-01 KR KR10-2001-0067854A patent/KR100449623B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03145111A (en) * | 1989-10-31 | 1991-06-20 | Matsushita Electric Ind Co Ltd | Manufacture of chip component |
| JPH053131A (en) * | 1991-04-17 | 1993-01-08 | Matsushita Electric Ind Co Ltd | Multilayer ceramic capacitor and manufacture thereof |
| JP2000243650A (en) * | 1999-02-22 | 2000-09-08 | Matsushita Electric Ind Co Ltd | Multilayer ceramic capacitor and its manufacture |
| JP2001044060A (en) * | 1999-07-30 | 2001-02-16 | Kyocera Corp | Multilayer ceramic capacitor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160071177A (en) | 2014-12-11 | 2016-06-21 | 삼성전기주식회사 | Strucutre of electrode for capacitor, electrolytic capacitor and manufacturing method thereof |
| US20220319777A1 (en) * | 2021-03-31 | 2022-10-06 | Tdk Corporation | Laminated electronic component |
| US11935700B2 (en) * | 2021-03-31 | 2024-03-19 | Tdk Corporation | Laminated electronic component with differing glass content electrodes |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030037351A (en) | 2003-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109326442B (en) | Multilayer ceramic capacitor and method for manufacturing the same | |
| KR100463776B1 (en) | Electroconductive paste, method of producing monolithic ceramic electronic part, and monolithic ceramic electronic part | |
| KR100888020B1 (en) | Dielectric ceramics and multi layer ceramic capacitor | |
| KR102029468B1 (en) | Multi-layered ceramic electronic parts and method of manufacturing the same | |
| CN107452504B (en) | Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor | |
| JP4744609B2 (en) | Ceramic component element, ceramic component and manufacturing method thereof | |
| JP4786604B2 (en) | Dielectric porcelain and multilayer ceramic capacitor using the same | |
| KR101912266B1 (en) | Laminated ceramic electronic parts and fabricating method thereof | |
| KR20060105585A (en) | Multilayer ceramic electronic components and method of manufacturing the same | |
| US11062847B2 (en) | Capacitor component and method for manufacturing the same | |
| JP2017059820A (en) | Laminated electronic component | |
| JP2012169620A (en) | Multilayer ceramic electronic component and method for manufacturing the same | |
| JP3642282B2 (en) | Dielectric ceramic composition and multilayer ceramic capacitor using the same | |
| US20170345568A1 (en) | Multilayer ceramic capacitor | |
| JP5349807B2 (en) | Multilayer ceramic capacitor and manufacturing method thereof | |
| KR19980070404A (en) | Monolithic ceramic capacitors | |
| JP2943380B2 (en) | Multilayer ceramic capacitor and manufacturing method thereof | |
| KR20080077321A (en) | Dielectric ceramics and multi-layer ceramic capacitor | |
| JP5498973B2 (en) | Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor | |
| KR100449623B1 (en) | Method For Manufacturing Multilayer Ceramic Capacitor | |
| JP3064659B2 (en) | Manufacturing method of multilayer ceramic element | |
| WO2007100621A2 (en) | Process of manufacturing a multi-layer device and device manufactured thereby | |
| JPH06340472A (en) | Ceramic composition, laminated ceramic capacitor provided with varistor function and its production | |
| JP2001006964A (en) | Manufacture of laminated ceramic electronic parts | |
| JPH11214240A (en) | Laminated ceramic electronic component and their manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130624 Year of fee payment: 10 |
|
| FPAY | Annual fee payment |
Payment date: 20140701 Year of fee payment: 11 |
|
| FPAY | Annual fee payment |
Payment date: 20150707 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |