KR100421678B1 - Plasma Display Panel - Google Patents

Abstract

The present invention relates to a plasma display panel capable of lowering an address voltage during address discharge.

The plasma display panel according to the present invention comprises: a scan / hold electrode 64Y and a sustain electrode 64Z for causing sustain discharge; A first trigger electrode 66Y and a second trigger electrode 66Z formed between the scan / hold electrode 64Y and the sustain electrode 64Z; At least one pad electrode formed between the scan / sustain electrode 64Y and the first trigger electrode 66Y, and at least one pad electrode formed between the sustain electrode 64Z and the second trigger electrode 66Z; ; Is formed on the lower substrate of the first and second trigger electrodes (66Y, 66Z) and formed in the cross direction to the first and second trigger electrodes (66Y, 66Z) of the address discharge this at the intersection of electrode area other takes place And an address electrode formed wider than the portion.

Accordingly, the plasma display according to the present invention can lower the address voltage by increasing the amount of wall charges generated during address discharge by increasing the electrode area of the address electrode and the trigger electrode.

Description

Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display, and more particularly, to a plasma display panel designed to lower an address voltage and to improve brightness.

Recently, a plasma display panel (hereinafter referred to as "PDP"), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. The PDP normally displays an image by adjusting the discharge period of each pixel according to the digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 is a perspective view illustrating a cell structure typically arranged in an alternating current PDP in a matrix form, and FIG. 2 is a cross-sectional view of the PDP shown in FIG. 1.

1 and 2, the PDP cell includes an upper plate having sustain electrode pairs 14 and 16, an upper dielectric layer 18, and a passivation layer 20 sequentially formed on the upper substrate 10, and a lower substrate ( 12, a lower plate having an address electrode 22, a lower dielectric layer 24, a partition wall 26, and a phosphor layer 28, which are sequentially formed on the substrate 12, is provided. The upper substrate 10 and the lower substrate 12 are spaced in parallel by the partition wall. Each of the sustain electrode pairs 14 and 16 has a relatively wide width and transparent electrodes 14A and 16A made of transparent electrode material (ITO) for transmitting visible light, and a relatively narrow width and transparent electrodes 14A and 16A. In order to compensate for the resistive components of the metal electrodes 14B and 16B. The sustain electrode pairs 14 and 16 are composed of scan / sustain electrodes and sustain electrodes. The scan signal for panel scanning and the sustain signal for discharging sustain are mainly supplied to the scan / hold electrode 14, and the sustain signal is mainly supplied to the sustain electrode 16. Charges accumulate in the upper dielectric layer 18 and the lower dielectric layer 24. The protective film 20 prevents damage to the upper dielectric layer 18 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 20, magnesium oxide (MgO) is usually used. The address electrode 22 is formed to cross the sustain electrode pairs 14 and 16. The address electrode 22 is supplied with a data signal for selecting cells to be displayed. The partition wall 26 is formed in parallel with the address electrode 22 to prevent ultraviolet rays generated by the discharge from leaking to adjacent cells. The phosphor layer 28 is applied to the surfaces of the lower dielectric layer 24 and the partition wall 26 to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

The PDP cell of this structure is selected by the counter discharge between the address electrode 22 and the scan / hold electrode 14, and then maintains the discharge by the surface discharge between the sustain electrode pairs 14 and 16. In the PDP cell, the fluorescent substance 28 emits light by ultraviolet rays generated during sustain discharge, so that visible light is emitted outside the cell. As a result, the PDP having cells displays an image. In this case, the PDP implements a gray scale required for displaying an image by adjusting the discharge sustain period of the cell, that is, the number of sustain discharges, according to the video data.

The AC surface discharge type PDP is driven by being divided into a plurality of subfields to express the gray level of the image. In each subfield period, gray scale display is performed by performing light emission in a number of times proportional to the weight of video data. do. For example, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell is divided into eight subfields SF1 to SF1. SF8). Each subfield SF1 to SF8 is further divided into a reset period, an address period and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is such that discharge is maintained in the discharge cells in which the address discharge has occurred. It is a period. The reset period and the address period are equally assigned to each subfield period.

FIG. 3 is a driving waveform diagram for driving the PDP shown in FIG. 1 during one subfield period, in which Y, Z, and X are scan / sustain electrodes 14, sustain electrodes 16, and address electrodes 22, respectively. The drive waveform supplied to each is shown.

In the reset period RPD, the reset pulse RP is supplied to the scan / hold electrode 14. The reset pulse RP has a form of ramp wave in which the voltage increases when set-up and the voltage decreases when set-down. During setup, a reset discharge is generated between the scan / hold electrode 14 and the sustain electrode 16 to form wall charges in the upper dielectric layer 18. Subsequently, unnecessary charged particles are partially erased by the decreasing voltage during set down, and the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, the positive DC voltage Vs is supplied to the sustain electrode 16 in the set-down period of the reset pulse RP. The reset pulse RP is supplied in a gradually decreasing form to the positive DC voltage Vs so that the scan / hold electrode 14 is relatively negative to the sustain electrode 16 during set down. This reduces the wall charges generated during the setup period, i.e. by inverting the polarity. In this way, the reset discharge is generated by the supply of the reset pulse RP, and the wall charges necessary for the address discharge are formed in the cells of all the screens.

In the address period APD, the scan pulse SP is supplied to the scan / sustain electrode 14 and the data pulse DP is supplied to the address electrode 22 to generate an address discharge. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

The triggering pulse TP is supplied to the scan / hold electrode 14 at the beginning of the sustain period SPD to start the sustain discharge in the discharge cells 11 in which wall charges are sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy are alternately supplied to the sustain electrode 16 and the scan / sustain electrode 14 to maintain the sustain discharge during the sustain period SPD.

The erase period EPD supplies the erase pulse EP to the sustain electrode 16 after the sustain period SPD to stop the discharge that was held. In this case, the erasing pulse EP has a lamp wave shape in which the light emission size is small, and has a short pulse width of about 1 ms for erasing the discharge. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

The three-electrode PDP forms a wide width of the scan / sustain electrode 14 and sustain electrode 16 to increase the capacitance of the liquid crystal panel. Accordingly, the interval between the scan / sustain electrode 14 and the sustain electrode 16 is narrow, so that the discharge path is short during the sustain discharge and the light emitting area is limited, thereby reducing the amount of ultraviolet rays emitted, thereby decreasing the luminance. In addition, as the scan / hold electrode 14 and the sustain electrode 16 have a wide electrode width, leakage current increases and power consumption increases.

In order to solve this problem, a 5-electrode AC surface discharge type PDP as shown in FIG. 4 has been proposed.

4 and 5, the five-electrode PDP is disposed on the upper substrate 40 so as to be positioned at the center of the discharge cell, and the upper portion is positioned at the edge of the discharge cell. The lower substrate in a direction orthogonal to the scan / hold electrode 30Y and the sustain electrode 30Z formed on the substrate 40 and the trigger electrodes 32Y and 32Z, the scan / hold electrode and the sustain electrode 30Y and 30Z. An address electrode 44X formed in the center portion of the 42 is provided.

An upper dielectric layer 36 and a protective layer 38 are stacked on the upper substrate 40 on which the first and second trigger electrodes 32Y and 32Z, the scan / sustain electrodes, and the sustain electrodes 30Y and 30Z are formed side by side.

The lower dielectric layer 46 and the partition wall 48 are formed on the lower substrate 42 on which the address electrode 44X is formed, and phosphors (not shown) are applied to the surfaces of the lower dielectric layer 46 and the partition wall 48.

The first and second trigger electrodes 32Y and 32Z are formed at a narrow interval N in the center of the discharge cell to receive an AC pulse during the sustain discharge period to start sustain discharge.

The scan / suspension electrode 30Y and the sustain electrode 30Z are formed at a wide interval W at the edge of the discharge cell. The scan / hold electrode 30Y and the sustain electrode 30Z are supplied with an alternating pulse during the sustain discharge period so that the plasma discharge is maintained after the discharge is initiated between the first and second trigger electrodes 32Y and 32Z.

The five-electrode PDP has a smaller electrode area than the conventional three-electrode PDP electrode structure, and thus the distance between the electrodes becomes farther. Accordingly, the discharge path of the charged particles generated by the trigger electrodes is increased, thereby increasing the discharge efficiency. However, since the widths of the scan / sustain electrodes and sustain electrodes are small, the amount of wall charges and space charges generated during address discharge is small. As a result, the voltage for causing the address discharge becomes high and a miswriting phenomenon occurs.

In order to solve this problem, a PDP in which a pad electrode 54 is formed between the trigger electrodes 52Y and 52Z and the sustain electrodes 50Y and 50Z of the conventional 5-electrode PDP has been proposed.

6 and 7, the 5-electrode PDP to which the pad electrode 54 is applied includes a pad electrode 54 between the trigger electrodes 52Y and 52Z and the sustain electrodes 50Y and 50Z. The sustain electrodes 50Y and 50Z and the trigger electrodes 52Y and 52Z have a narrow electrode width. As the width of the electrode is narrow, the distance between the sustain electrodes 50Y and 50Z and the trigger electrodes 52Y and 52Z is increased.

The pad electrode 54 intersects the sustain electrodes 50Y and 50Z and the trigger electrodes 52Y and 52Z formed on the upper substrate 40 and overlaps the address electrode 44X on the lower substrate 42. The pad electrode 54 is formed to have the same thickness or narrow to the sustain electrodes 50Y and 50Z and the trigger electrodes 52Y and 52Z. At this time, the pad electrode 34 improves the opening ratio as the width of the electrode is narrowed.

When voltage is applied to the sustain electrodes 50Y and 50Z, a discharge occurs between the trigger electrodes 52Y and 52Z that are formed close to each other, thereby generating charged particles. The charged particles formed between the trigger electrodes 52Y and 52Z move toward the sustain electrodes 50Y and 50Z. At this time, the pad electrode 54 is formed for smooth movement of the charged particles between the sustain electrodes 50Y and 50Z and the trigger electrodes 52Y and 52Z. The pad electrode 54 compensates for insufficient charged particles so that charged particles generated between the trigger electrodes 52Y and 52Z can be moved toward the sustain electrodes 50Y and 50Z. Accordingly, since the small discharge continues to be generated by the pad electrode 54 and sufficient charged particles are supplied to the discharge space, the sustain discharge voltage required for the sustain discharge does not increase significantly. However, since the widths of the trigger electrodes 52Y and 52Z are narrow, a problem arises in that the address discharge voltage becomes high during address discharge.

Accordingly, an object of the present invention is to provide a plasma display panel capable of lowering an address voltage.

1 is a perspective view showing a discharge cell of a conventional three-electrode AC surface discharge PDP.

FIG. 2 is a sectional view of the PDP shown in FIG. 1. FIG.

3 is a driving waveform diagram of the discharge cell shown in FIG.

4 is a plan view showing a discharge cell of a conventional 5-electrode AC surface discharge PDP.

FIG. 5 is a sectional view of the PDP shown in FIG. 4; FIG.

FIG. 6 is a plan view illustrating a PDP including a pad electrode to improve the five-electrode PDP shown in FIG. 4;

FIG. 7 is a sectional view of the PDP shown in FIG. 6; FIG.

8 is a perspective view showing a discharge cell of the PDP according to an embodiment of the present invention.

FIG. 9 is a sectional view of the PDP shown in FIG. 8; FIG.

FIG. 10 is a plan view showing the address electrode shown in FIG. 8; FIG.

<Description of Symbols for Main Parts of Drawings>

10,40,60: Upper board 12,42,62: Lower board

14,30Y, 50Y, 64Y: scan / hold electrode 16,30Z, 50Z, 64Z: sustain electrode

18,36,70: upper dielectric layer 20,38,72: protective film

22,44X, 80X: address electrode 24,46,74: lower dielectric layer

26,48,76 Bulkhead 28,78 Phosphor layer

32Y, 32Z, 52Y, 52Z, 66Y, 66Z: Trigger electrode 54, 68: Pad electrode

In order to achieve the above object, the plasma display panel according to the present invention includes a scan / hold electrode 64Y and a sustain electrode 64Z for causing sustain discharge; A first trigger electrode 66Y and a second trigger electrode 66Z formed between the scan / hold electrode 64Y and the sustain electrode 64Z; At least one pad electrode formed between the scan / sustain electrode 64Y and the first trigger electrode 66Y, and at least one pad electrode formed between the sustain electrode 64Z and the second trigger electrode 66Z; ; Is formed on the lower substrate of the first and second trigger electrodes (66Y, 66Z) and formed in the cross direction to the first and second trigger electrodes (66Y, 66Z) of the address discharge this at the intersection of electrode area other takes place In addition to the above object, other objects and advantages of the present invention will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8 to 10.

8 is a perspective view illustrating a PDP according to an embodiment of the present invention, and FIG. 9 is a plan view illustrating the PDP illustrated in FIG. 8.

8 and 9, the PDP according to the present invention is formed on the lower substrate 62 and formed on the upper substrate 60 and the address electrode 80X having the wider electrode at the center of the discharge cell. Sustain electrodes 64Y and 64Z and trigger electrodes 66Y and 66Z, and pad electrodes 68 for connecting the sustain electrodes 64Y and 64Z and trigger electrodes 66Y and 66Z, respectively. do.

Here, the sustain electrodes 64Y and 64Z include scan / hold electrodes and sustain electrodes 64Y and 64Z, and the trigger electrodes 66Y and 66Z include first and second trigger electrodes 66Y and 66Z. The upper dielectric layer 70 and the passivation layer 72 are stacked on the upper substrate 60 on which the scan / hold and sustain electrodes 64Y and 64Z and the first and second trigger electrodes 66Y and 66Z are formed. The lower dielectric layer 74 and the partition wall 76 are formed on the lower substrate 62 on which the address electrode 80X is formed, and the phosphor 78 is coated on the surfaces of the lower dielectric layer 74 and the partition wall 76.

The scan / sustain electrodes and sustain electrodes 64Y and 64Z are located at the edges of the discharge cells and are formed of a metallic material. The first and second trigger electrodes 66Y and 66Z are located at the center of the discharge cell. The first trigger electrode 66Y is formed to have a wide width 66A at one side overlapping the address electrode 80X. The scan / sustain electrodes and sustain electrodes 64Y and 64Z are formed side by side on both sides of the first and second trigger electrodes 66Y and 66Z, respectively. Thus, the scan / sustain electrodes and sustain electrodes 64Y and 64Z positioned at the edges of the discharge cells have a narrow electrode width, so that the distance between the electrodes is far. Accordingly, since the scan / hold electrode and the sustain electrode 64Y and 64Z use initial discharge by the first and second trigger electrodes 66Y and 66Z during the reset discharge, the discharge path is increased without increasing the discharge voltage. The luminous efficiency is improved.

When the reset pulse is supplied to the sustain electrodes 64Y and 64Z during the reset period, the closest trigger electrodes 66Y and 66Z cause an initial discharge. Charged particles are generated around the trigger electrodes 66Y and 66Z by the initial discharge of the trigger electrodes 66Y and 66Z. The charged particles thus generated are diffused toward the sustain electrodes 64Y and 64Z.

The pad electrode 68 may be formed of a transparent conductive material, for example, indium tin oxide (ITO) or a metal material. The pad electrode 68 connects the sustain electrodes 64Y and 64Z and the trigger electrodes 66Y and 66Z and overlaps with the address electrode 80X where the address discharge is concentrated.

Charges are accumulated in the upper dielectric layer 70 and the lower dielectric layer 74. The passivation layer 72 prevents damage to the upper dielectric layer 70 by sputtering, thereby increasing the lifetime of the PDP and increasing the emission efficiency of secondary electrons. As the protective film 72, magnesium oxide (MgO) is usually used.

The partition wall 76 is formed in parallel with the address electrode 80X to prevent the ultraviolet rays generated by the discharge from leaking to the adjacent cells. The phosphor layer 78 is applied to the surfaces of the lower dielectric layer 74 and the partition wall 76 to generate visible light of any one of red, green, and blue. Then, an inert gas for gas discharge is injected into the discharge space therein.

The address electrode 80X formed on the lower substrate 62 is formed to cross the sustain electrodes 64Y and 64Z and the first and second trigger electrodes 66Y and 66Z. As shown in FIG. 10, the address electrode 80X is formed to have a wide width 80A at the portion crossing the first trigger electrode 66Y. The scan pulse is supplied to the scan / sustain electrode 64Y and the first trigger electrode 66Y during address discharge, and the data pulse is applied to the address electrode 80X in synchronization with the scan / sustain electrode 64Y and the first trigger. An address discharge occurs between the electrode 66Y and the address electrode 80X to form wall charges on the upper and lower dielectric layers 70 and 74. At this time, since the width of the electrode crossing the first trigger electrode 66Y is wider than the address electrode 80X, the wall charges formed on the lower dielectric layer 74 increase. As a result, the address voltage required for the address discharge is lowered. In addition, since the first trigger electrode 66Y has a structure in which the width of the electrode is widened at a portion crossing the address electrode 80X, wall charges are formed on the upper dielectric 70 during address discharge. Accordingly, the address voltage required for address discharge becomes low.

In the cells selected by the address discharge, sustain discharge occurs between the sustain electrodes 64Y and 64Z and the first and second trigger electrodes 66Y and 66Z. Here, since the first trigger electrode 66Y has a wider electrode structure than the related art, the amount of wall charges formed on the upper dielectric 70 is increased to lower the sustain discharge voltage. At this time, ultraviolet rays are generated in the process of transition after the discharge gas is excited in the discharge space. The generated ultraviolet rays excite the phosphor 78 to generate visible light, thereby realizing a PDP image.

As described above, in the plasma display panel according to the present invention, one side of the trigger electrode to which the scanning signal for address discharge is supplied protrudes to widen the electrode width, and the width of the address electrode at the portion crossing the trigger electrode is wide. Therefore, the plasma display panel according to the present invention increases the amount of wall charges generated by the trigger electrode and the address electrode, thereby lowering the address discharge voltage during address discharge.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

A scan / hold electrode 64Y and a sustain electrode 64Z for causing sustain discharge; A first trigger electrode 66Y and a second trigger electrode 66Z formed between the scan / hold electrode 64Y and the sustain electrode 64Z; At least one pad electrode formed between the scan / sustain electrode 64Y and the first trigger electrode 66Y, and at least one pad electrode formed between the sustain electrode 64Z and the second trigger electrode 66Z; ; Is formed on the lower substrate of the first and second trigger electrodes (66Y, 66Z) and formed in the cross direction to the first and second trigger electrodes (66Y, 66Z) of the address discharge this at the intersection of electrode area other takes place And an address electrode formed wider than the portion. The method of claim 1, And one of the first and second trigger electrodes further includes an address discharge portion having a larger electrode area than another portion at an intersection with the address electrode. The method of claim 2, And the address discharge unit has a protrusion projecting on one side of the trigger electrode. The method of claim 1, And the trigger electrode and the sustain electrode are formed of a metal material. The method of claim 1, The pad electrode is a plasma display panel, characterized in that the transparent conductive material. The method of claim 1, And the pad electrode is a metal material.