KR100429072B1 - System and Method of Transmitting Voice Traffics in the VoIP Gateway - Google Patents

Abstract

The present invention is to implement a voice transmission bus between an IP matching processor and a vocoding processor in a Voice over Internet Protocol (Gateway) as a time division multiplexer (TDM) bus using a memory. A voice traffic delivery system and method in a VoIP gateway.

The system of the present invention includes an IP matching processor for matching an IP network, a plurality of vocoding processors for vocoding voice data, and a PSTN matching unit for matching a PSTN, wherein the IP matching processor and each vocoding are performed. A memory provided in the processing unit, respectively, for storing voice data to be recorded or read; A CPU provided in the IP matching processing unit and each vocoding processing unit to perform IP protocol processing and access to the memory for VoIP voice traffic; And hardware logic respectively provided in the IP matching processor and each vocoding processor to sequentially read or write voice data stored in the memory in a circuit-switched manner by a shared synchronous clock of the IP matching processor and each vocoding processor. It is characterized by. In addition, the method includes the steps of: recording voice data in a memory after protocol processing of a VoIP packet; Sequentially reading voice data recorded in the memory in a circuit-switched manner by a synchronous clock; Demultiplexing the voice data read from the memory and transmitting the decoded voice data to a TDM bus by a synchronous clock; Sequentially writing voice data applied from the TDM bus to a memory in a circuit-switched manner by a synchronous clock; And vocoding by reading the voice data recorded in the memory at a predetermined timing according to each vocoding method.

Description

System and Method of Transmitting Voice Traffics in the VoIP Gateway}

The present invention relates to a voice traffic delivery system and method in a VoIP gateway, and more particularly, to implement a voice transmission bus between an IP matching processor and a vocoding processor as a time division multiplexer (TDM) bus using a memory in a VoIP gateway. A voice traffic delivery system and method in a VoIP gateway.

In general, a conventional VoIP gateway is a device for transferring voice traffic between an IP network and a PSTN, and is largely an IP matching processor 10, a vocoding processor 20, and a PSTN matching unit ( It consists of three configurations of 30). Here, the IP matching processor 10 includes a CPU 11, a memory 12, and a Compact Peripheral Component Interconnect (cPCI) bridge 13, and the vocoding processor 20 DSP 21, CPU 22, memory 23, and cPCI bridge 24 are included.

In general, since the vocoding processing unit 20 has a lower channel density than the IP matching processing unit 10, it is common that one IP matching processing unit 10 and a plurality of vocoding processing units 20 are matched. In this case, in order to transmit and receive voice traffic between the IP matching processor 10 and the vocoding processor 20, a plurality of hardware PBAs (Printed Board Assembly) are commonly used for voice traffic on the backplane. There is a task that must be matched to the bus.

In addition, in the current technology level, it is common to use a cPCI bus in terms of bus band and operation, and when the cPCI bus is used, the intervention of the CPUs 11 and 22 is required for the operation of the bus. Accordingly, the CPUs 11 and 22 must be used to carry voice traffic and also to operate a bus.

In addition, the CPU 11 of the IP matching processing unit 10 is a component used to operate the IP protocol processing and the cPCI bus, and the cPCI bridges 13 and 24 are configured to match the CPU bus and the cPCI bus. The DSP 21 of the vocoding processing unit 20 is an element necessary for implementing a vocoding function, and the CPU 22 of the vocoding processing unit 20 controls the cPCI bridge 24. In order to transmit and receive data processed by the CPUs 11 and 22 and the DSP 21, the memories 12 and 23 are essential components.

The cPCI bus is composed of one master and several targets. In the above-described conventional configuration, the IP matching processing unit 10 becomes a master and several vocoding processing units 20 target. Will perform the operation.

Next, the operation of reading data of the target by the master will be described with reference to the timing diagram of FIG. 2.

First, the clock CLK is a signal generated by the IP matching processor 10 serving as a master and used to synchronize the cPCI bus. Except for the target ready signal TRDY #, all of the signals are generated by the IP matching processing unit 10, which is the master of the cPCI bus, and the address data signal AD and AD are bidirectional signals.

Accordingly, when there is data to be read by accessing a target (ACCess), the master of the cPCI bus generates a frame signal FRAME # first to signal the start of the bus operation, and then the address data signal ( AD) is used to select the target, wherein the cPCI bus uses a memory mapped input and output method.

In addition, the type of the bus operation is informed by using a command and byte enable signal (C / BE #). In this case, the initiator ready signal (IRDY #) receives the data from the master. Play the role of reminding you that you are ready.

Therefore, after the bus operation is notified, the initiator preparation signal IRDY # and the target preparation signal TRDY # are combined to transmit data from the target to the master by the combined signal.

That is, when the initiator ready signal IRDY # and the target ready signal TRDY # interlock with each other and the initiator ready signal IRDY #, the target sends data onto the address data bus. When the target ready signal TRDY # is used, the master repeats the operation of reading data on the address data bus.

The device selection signal DEVSEL # informs the target that the bus is still occupied, and the other targets receive the corresponding device selection signal and do not request the bus occupancy.

Then, when the data transmission process is finished, the initiator ready signal IRDY # and the target ready signal TRDY # are no longer driven, and thus the master of the cPCI bus notifies that the data transmission process is finished. In order to remove the frame signal (FRAME #) and to indicate that the target and bus operation process has ended, the device selection signal should be removed.

As described above, in the conventional VoIP gateway, the voice traffic forwarding apparatus shares a cPCI bus with multiple sources, that is, an IP matching processor and a vocoding processor, and thus requires an arbitration process to occupy the cPCI bus, thereby increasing the CPU load. When using the cPCI bus, since multiple sources cannot occupy the cPCI bus at the same time, voice traffic from sources that do not occupy the cPCI bus will be delayed and degrade the voice quality. As a result, the delay of voice traffic results in loss of voice traffic, which degrades voice quality of service.

The present invention provides a memory bus for transmitting voice traffic inside a VoIP gateway to solve the above problems, that is, providing a memory bus for transmitting and receiving VoIP voice traffic without CPU intervention to reduce the CPU load. The purpose of the present invention is to increase voice processing capacity and to prevent delay and loss of voice data.

In addition, the present invention implements the voice transmission bus between the IP matching processing unit and the vocoding processing unit in the VoIP gateway as a TDM bus using a memory, thereby degrading service quality due to delay and loss of VoIP voice traffic, and CPU for delivering voice traffic. Aims to solve the problem of poor CPU performance that occurs when Windows intervenes.

1 is a block diagram showing a conventional Voice over Internet Protocol (VoIP) gateway (Gateway).

FIG. 2 is a diagram showing timing of reading data of a vocoding processing unit by the IP matching processing unit in FIG. 1; FIG.

3 is a block diagram showing a VoIP gateway according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating memory read and write operations of hardware logic in FIG. 3; FIG.

5 is a flowchart illustrating a voice traffic delivery method in a VoIP gateway according to an embodiment of the present invention.

6 is a diagram illustrating voice traffic delivery timing in FIG. 5;

Explanation of symbols on the main parts of the drawings

40: IP matching processing unit

41, 52-1 to 52-n: CPU (Central Processing Unit)

42, 53-1 to 53-n: Memory

43, 54-1 to 54-n: hardware logic

44: DMX (Demultiplexer)

45: MUX (Multiplexer)

46-1 to 46-4, 55: TDM bus interface

50-1 to 50-n: Vocoding processing part

51-1 ~ 51-n: DSP (Digital Signal Processor)

60: PSTN (Public Switched Telephone Network) matching unit

In the VoIP gateway according to an embodiment of the present invention for achieving the above object, a voice traffic delivery system includes an IP matching processor for matching to an IP network, a plurality of vocoding processors for vocoding voice data, and a matching to a PSTN. A VoIP gateway comprising a PSTN matching unit, comprising: a memory configured to store voice data to be recorded or read in the IP matching processing unit and each vocoding processing unit, respectively; A CPU provided in the IP matching processing unit and each vocoding processing unit to perform IP protocol processing and access to the memory for VoIP voice traffic; And hardware logic respectively provided in the IP matching processor and each vocoding processor to sequentially read or write voice data stored in the memory in a circuit-switched manner by a shared synchronous clock of the IP matching processor and each vocoding processor. It is characterized by.

In this case, the memory is independent of each direction, and the number of memory banks in the IP matching processor is proportional to the number of the vocoding processor and the vocoding capability. The hardware logic may further include: a plurality of TDM bus interfaces that match TDM buses between the IP matching processor and each vocoding processor to transmit and receive voice data in the memory by a synchronous clock; A DMX which demultiplexes and transmits the voice data of the memory to each of the vocoding processing units to be transmitted to each of the TDM bus interfaces; And MDX for multiplexing voice data applied from the respective TDM bus interfaces and storing them in the memory. In addition, the TDM bus is used as a synchronization clock of 8 (KHz) and the synchronization of the voice data is characterized by using a synchronization clock of 50 (Hz).

On the other hand, the voice traffic delivery method in the VoIP gateway according to an embodiment of the present invention for achieving the above object comprises the steps of: recording the voice data in the memory after the protocol processing of the VoIP packet; Sequentially reading voice data recorded in the memory in a circuit-switched manner by a synchronous clock; Demultiplexing the voice data read from the memory and transmitting the decoded voice data to a TDM bus by a synchronous clock; Sequentially writing voice data applied from the TDM bus to a memory in a circuit-switched manner by a synchronous clock; And vocoding by reading the voice data recorded in the memory at a predetermined timing according to each vocoding method.

Alternatively, the voice traffic delivery method in the VoIP gateway according to an embodiment of the present invention is characterized in that it further comprises the step of multiplexing the voice data applied from the TDM bus and writing to the memory for protocol processing. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the VoIP gateway according to the embodiment of the present invention has an IP matching processor 40, a plurality of vocoding processors 50-1 to 50-n, and a PSTN matching unit 60. It consists of three configurations. Here, the IP matching processing unit 40 includes a CPU 41, a memory 42, and hardware logic 43, and each of the vocoding processing units 50-1 to 50-n includes a DSP ( 51-1 to 51-n, CPUs 52-1 to 52-n, memories 53-1 to 53-n, and hardware logic 54-1 to 54-n.

In addition, the VoIP gateway according to an embodiment of the present invention may be configured by each of the memories 42, 53-1 through 53-n in the IP matching processor 40 and the plurality of vocoding processors 50-1 through 50-n. Is used as 'DPRAM (Dual Port RAM)', but in practice, single-port memory can be divided in time. Further, by using a TDM bus instead of the conventional cPCI bus, the CPUs 41, 52-1 to 52-n do not perform the conventional cPCI bus control function, and the hardware instead of the PCI bridge for the conventional cPCI bus. Use logic 43, 54-1 through 54-n. In addition, the TDM bus allows voice data to be transmitted and received by the hardware logic 43, 54-1 to 54-n without the intervention of the CPUs 41, 52-1 to 52-n.

The CPU 41 is a component that handles an IP protocol for VoIP voice traffic, and applies IP and Real Time Protocol (RTP) / Real Time Control Protocol (RTCP) to bidirectional traffic, from the IP network to the PSTN. When transmitting voice traffic, VoIP packets applied from the corresponding IP network are processed into IP data and RTP / RTCP to generate voice data such as G.723.1 and recorded in the memory 42, or vice versa. It reads it and processes it as VoIP packet and delivers it to IP network.

The memory 42 may be physically configured as DPRAM, or may be logically used as a dual port type SRAM. That is, since the port for writing and reading in the CPU 41 and the port for reading and writing in the hardware logic 43 are different from each other, only the protocol processing and the memory access need to be performed from the side of the CPU 41. .

The hardware logic 43 stores the memory in a circuit-switched manner by a synchronous clock shared by the IP matching processor 40 and each of the vocoding processors 50-1 to 50-n without the involvement of the CPU 41. Voice data stored in 42 is sequentially read and transmitted to each of the vocoding processing units 50-1 to 50-n or applied through the TDM bus from each of the vocoding processing units 50-1 to 50-n. Voice data is sequentially recorded in the memory 42.

The DSPs 51-1 to 51-n perform a vocoding process (i.e., converting G.723.1 to G.711) from the voice data applied from the CPUs 52-1 to 52-n. Later, the voice data transmitted to the PSTN matching unit 60 or vice versa is subjected to an inverse conversion process (that is, a process of converting G.711 to G.723.1) and then the CPU ( 52-1 to 52-n).

The CPUs 52-1 to 52-n read-process the voice data stored in the memories 53-1 to 53-n at a predetermined timing in accordance with the respective vocoding methods to read the DSPs 51-1 to 51-n. The audio data transmitted to or applied from the DSPs 51-1 to 51-n is recorded in the memories 53-1 to 53-n.

The memories 53-1 to 53-n are the same as the memory 42 of the IP matching processor 40.

The hardware logics 54-1 to 54-n are connected by a synchronous clock shared by the IP matching processor 40 and the vocoding processor 50 without the involvement of the CPUs 52-1 to 52-n. Voice data applied from the IP matching processor 40 through the TDM bus in a switching manner is sequentially recorded in the memories 53-1 to 53-n or stored in the memories 53-1 to 53-n. Are sequentially read and transmitted to the IP matching processor 40.

Meanwhile, the VoIP voice processing capacity of one IP matching processing unit 40 is 1,024 channels, the vocoding processing capacity of the four vocoding processing units 50-1 to 50-4 is 256 channels, and the speed of the TDM bus is 16. (Mbps) (that is, 64 (Kbps) * 256), and assuming that the IP matching processor 40 transmits voice traffic to the vocoding processors 50-1 to 50-4, the memory 42 As shown in FIG. 4, the hardware logic 43, 54-1 to 54-4 for reading or recording voice data to the IP matching processor 40 is provided on the IP matching processor 40 side. The DMX 44, the MUX 45, and four TDM bus interfaces 46-1 to 46-4 are included, and the vocoding processing unit 50-1 to 50-4 side includes a TDM bus interface ( 55).

Here, the IP matching processor 40 and the memories 42, 53-1 to 53-4 of each vocoding processor 50-1 to 50-4 are actually independent of directions. In addition, the number of banks Bank1 to Bank1024 and Bank1 to Bank256 of the memories 42 and 53-1 to 53-n is proportional to the number of vocoding processing units 50-1 to 50-4 and the vocoding processing capability. In the home, the IP matching processor 40 is 1,024 and the vocoding processors 50-1 to 50-4 are 256. In addition, since the size of each bank (Bank1 to Bank1024, Bank1 to Bank256) occurs once every 20 (msec) of VoIP voice traffic, a maximum of 320 (Byte) should be sufficient when considering double buffering. In consideration of delay difference of each packet, it is designed to be variable as' n * 160 (Byte).

The DMX 44 demultiplexes the voice data read from the memory 42 to the vocoding processing units 50-1 to 50-4 to decode each of the TDM bus interfaces 46-1 to 46-. 4) to pass.

Since the MDX 45 is allocated to each of the vocoding processing units 50-1 to 50-4 independently of each other, voice data applied from each of the TDM bus interfaces 46-1 to 46-4 for this purpose. Are multiplexed and stored in the memory 42.

The TDM bus interfaces 46-1 to 46-4 and 55 use a synchronization clock of 8 (KHz) to connect the 16 (between the IP matching processor 40 and the vocoding processor 50-1 to 50-4). Mbps) (that is, 64 (Kbps) * 256) after matching TDM buses, and after matching, transmits and receives voice data using 50 (Hz) synchronous clock.

A voice traffic delivery method in a VoIP gateway according to an embodiment of the present invention will be described with reference to the flowchart of FIG. 5.

First, when a VoIP call occurs in the IP network and the work to be routed to the PSTN side occurs, the CPU 41 of the IP matching processor 40 processes the VoIP packet and then processes the memory of the IP matching processor 40. 42, only voice data (e.g., G.723.1 voice data) is recorded (step S1).

In this case, since the voice data recording step of the first step S1 occurs every time a VoIP packet occurs in a VoIP call or one VoIP call, the voice data recording operation is randomly performed. The bank position in 42 is set to the channel number of available vocoding resources.

Thus, in order to prevent delay and loss of the voice data, the voice data is routed to the PSTN side in a circuit switched manner after the voice data is recorded in the memory 42.

In other words, the voice data recorded in the memory 42 are read out (ie, sequential read) in a circuit-switched manner by the hardware logic 43 of the IP matching processor 40, i.e., the IP 1,024 memory banks of the IP matching processor 40 by phase-aligning each other by the synchronous clocks shared by the matching processing unit 40 and the vocoding processing units 50-1 to 50-4 (that is, synchronized). Is read by the corresponding synchronous clock (step S2).

Thereafter, the DMX 44 demultiplexes the read voice data to the vocoding processing units 50-1 to 50-4. The 256th memory bank (Bank1) is demultiplexed. Bank256 is transferred to first vocoding processor 50-1, and from 256th memory bank Bank257 to 512th memory bank Bank512, it is transferred to second vocoding processor 50-2. The vocoding processing unit 50-1 to 50-4 stores as many memory banks as the number of banks Bank1 to Bank1024 of the memory 42 divided by the number of the vocoding processing units 50-1 to 50-4. ), The read voice data is demultiplexed and transmitted to each TDM bus interface 46-1 to 46-4 (step S3).

Accordingly, each of the TDM bus interfaces 46-1 to 46-4 is logic added for matching 16 (Mbps) (ie, 64 (Kbps) * 256) TDM buses used in the present invention. The received voice data is transmitted to the respective vocoding processing units 50-1 to 50-4 (step S4).

Accordingly, the IP matching processor 40 is routed to each of the vocoding processors 50-1 to 50-4 through a TDM bus, so that the TDM bus interface in each of the vocoding processors 50-1 to 50-4. The voice data inputted to 55 is circuit switched by each hardware logic 54-1 to 54-4 in the respective vocoding processing units 50-1 to 50-4 via the corresponding TDM bus interface 55. As a result, writes are sequentially made to the memories 53-1 to 53-4 (step S5).

Thereafter, the CPUs 52-1 to 52-4 in the respective vocoding processing units 50-1 to 50-4 perform the respective memory 53-1 to 53-4 at a constant timing according to each vocoding method. The voice data recorded in the readout is read and transferred to each of the DSPs 51-1 to 51-4 in the respective vocoding processing units 50-1 to 50-4 to perform the vocoding process (step S6).

In this case, in the case of VoIP voice data using G.723.1, the TDM bus cannot be used as it is, because a conventional technique such as voice compression is used. In addition to synchronizing with the signal of the signal and synchronizing with the 20 (msec) synchronization signal defined in G.723.1 at the same time, in the present invention, the memory read of the IP matching processor 40 and the vocoding processor ( Since the memory recording of 50-1 to 50-4 is set to a 20 (msec) signal, which is a synchronous clock, even if the voice data subjected to the voice compression process is input, it can be processed without loss or delay of voice.

The above operation will be described with reference to the timing diagram of FIG. 6.

First, the method of synchronizing the IP matching processing unit 40 and each of the vocoding processing units 50-1 to 50-4 uses a matching of the TDM bus as an 8 (KHz) synchronization clock, and synchronizes VoIP voice data. For this purpose, a synchronous clock of 50 Hz is used.

In addition, the voice data read by the synchronization clock of 50 (Hz) by the IP matching processing unit 40 is configured to obtain a synchronization clock of 8 (KHz) by the TDM bus interfaces 46-1 to 46-4 in the hardware logic 43. To match the TDM bus. That is, up to 160 (Byte) of voice data read from the memory 42 with a synchronous clock of 50 (Hz) is possible depending on the type of the corresponding voice data, and the corresponding TDM bus interface 46-1 to 46-4 The output audio data is arranged by 1 (Byte) every 8 (KHz) frame.

Similarly, the TDM bus interface 55 in each of the vocoding processing units 50-1 to 50-4 also matches the TDM bus using 8 (KHz), and then uses the 50 (Hz) synchronous clock to generate voice data. Is read by the CPUs 52-1 through 52-4 in the respective vocoding processing units 50-1 through 50-4, and the DSPs 51-1 through the respective vocoding processing units 50-1 through 50-4 are read. 51-4), and after vocoding process in the corresponding DSPs 51-1 to 51-4, are routed to the PSTN side via the PSTN matching unit.

Meanwhile, when the PSTN is routed to the IP network via each of the vocoding processing units 50-1 to 50-4 and the IP matching processing unit 40, the operation goes through the reverse process as described above. The difference is that the demultiplexing process of the IP matching processor 40 is changed to a multiplexing process.

That is, since four TDM buses are independently assigned to each of the four vocoding processing units 50-1 to 50-4, the MDX in the hardware logic 43 that is the front end of the memory 42 in the IP matching processing unit 40. At 45, four TDM buses must be multiplexed.

However, if there are four memories 42 in the IP matching processor 40, the MDX 45 in the hardware logic 43 may be omitted, and even if the MDX 45 is omitted, there is no serious problem in function. It only has a slight effect on the operation of the memory 42.

As described above, by implementing the bus between the IP matching processing unit and the vocoding processing unit as a memory bus using TDM, the CPU load generated from the cPCI bus or the like can be reduced, thereby enabling more voice processing. The quality of service of voice traffic can be increased by preventing delay and loss of voice data generated on the bus.

Claims (6)

A VoIP gateway comprising an IP matching processor for matching an IP network, a plurality of vocoding processors for vocoding voice data, and a PSTN matching unit for matching a PSTN. A memory provided in the IP matching processing unit and each vocoding processing unit to store voice data to be recorded or read; A CPU provided in the IP matching processing unit and each vocoding processing unit to perform IP protocol processing and access to the memory for VoIP voice traffic; And hardware logic respectively provided in the IP matching processor and each vocoding processor to sequentially read or write voice data stored in the memory in a circuit-switched manner by a shared synchronous clock of the IP matching processor and each vocoding processor. Voice traffic delivery system in the VIP gateway, characterized in that. The method of claim 1, The memory is independent of each direction, and the number of memory banks in the IP matching processor is proportional to the number of the vocoding processing unit and the vocoding processing capacity, characterized in that the voice traffic delivery system in the BIP gateway. The method of claim 1, The hardware logic includes: a plurality of TDM bus interfaces that match TDM buses between the IP matching processor and each vocoding processor to transmit and receive voice data in the memory by a synchronous clock; A DMX which demultiplexes and transmits the voice data of the memory to each of the vocoding processing units to be transmitted to each of the TDM bus interfaces; And a MDX for multiplexing the voice data applied from each TDM bus interface and storing the received voice data in the memory. The method of claim 3, The matching of the TDM bus uses a synchronization clock of 8 (KHz) and the synchronization of the voice data uses a synchronization clock of 50 (Hz). Recording voice data in memory after protocol processing of the VoIP packet; Sequentially reading voice data recorded in the memory in a circuit-switched manner by a synchronous clock; Demultiplexing the voice data read from the memory and transmitting the decoded voice data to a TDM bus by a synchronous clock; Sequentially writing voice data applied from the TDM bus to a memory in a circuit-switched manner by a synchronous clock; And vocoding the voice data recorded in the memory at a predetermined timing according to each vocoding method. The method of claim 5, And multiplexing the voice data applied from the TDM bus and writing them to the memory for protocol processing.