KR100428591B1 - Semiconductor device having pulse generation circuit - Google Patents

Abstract

PURPOSE: A semiconductor device having a pulse generation circuit is provided to generate a pulse signal having desired width regardless of a high level period and a low level period by changing a composition of a delay circuit. CONSTITUTION: A semiconductor device having a pulse generation circuit includes an inverter, a delay, and an output. The inverter(100) receives an external clock signal and inverts the received external clock signal. The delay(200) is formed with two or more even-numbered logic gates. The delay receives the external clock signal and outputs a delay signal to an output terminal. The output(300) receives the external clock signal and the delay signal and outputs the pulse signal.

Description

Semiconductor device with pulse generator

The present invention relates to a pulse generating circuit, and more particularly to a pulse generating circuit for a semiconductor device.

Since a semiconductor device is operated using several signals instead of one signal, it is necessary to make and use several signals necessary at that time. In a semiconductor device, an external clock signal is applied to a buffer to control various signals so that a clock signal is generated inside the semiconductor chip. Then, the generated clock signal is applied to a short pulse generator (SPG) to make a desired pulse signal randomly can be used in various ways in a semiconductor device.

1A is a circuit diagram showing the configuration of a pulse generating circuit according to a conventional embodiment.

Referring to FIG. 1A, the pulse generation circuit is composed of a delay circuit 10 and an output circuit 20. The delay circuit 10 includes n inverters 11, 12, ..., 1N connected in series, and the output circuit 20 is constituted by a NOR gate 21 (where n is odd).

1B is a circuit diagram showing the configuration of a pulse generating circuit according to a conventional embodiment.

Referring to FIG. 1B, the pulse generating circuit has the configuration as shown in FIG. 1 as the delay circuit 30 and the output circuit 40. The delay circuit 30 is provided with n inverters 31, 32,..., 3N connected in series. However, unlike the output circuit 20 of FIG. 1, the output circuit 40 includes the NAND gate 41 and the inverter 42.

2A shows an output waveform diagram of the pulse signal according to FIG. 1A.

The pulse generator circuit operates by receiving a clock signal XCK from the outside. The clock signal XCK is applied to the delay circuit 10, and a delay period is determined through the delays of the inverters 11, 12, ..., 1N. If the inverter delay of each stage is tD, the delay of n * tD occurs in the last n inverters. The output circuit 20, which receives the clock signal XCK and the delay signal and generates a pulse signal PULSE, outputs a pulse signal PULSE having a width corresponding to the delay period of the inverters.

Referring to FIG. 2A, when the clock signal XCX transitions from logic ″ 1 ″ to logic ″ 0 ″, the odd number of inverters of the delay circuit 10 output a delay signal of logic ″ 1 ″. Therefore, the delay period starts when the clock signal XCK is a logic ″ 0 ″, and immediately becomes a delay period until the clock signal XCK of the logic 0 applied to the inverter transitions to the logic ″ 1 ″. Subsequently, the NOR gate of the output circuit 20 receives a clock signal of logic ″ 0 ″ and a delay signal of logic ″ 0 ″, and combines them to output a signal of logic ″ 1 ″. Therefore, a pulse signal PULSE having a width equal to the delay period during the logic ″ 0 ″ can be obtained.

2B shows a pulse signal output waveform diagram according to FIG. 1B.

The delay circuit 30, which receives the clock signal XCK, delays and transfers the clock signal XCK, generates a delayed signal corresponding to the delay of the inverters. Then, the output circuit 40 receives the clock signal XCK and a delay signal and outputs a pulse signal PULSE having a width corresponding to the delay period.

Referring to FIG. 2B, while the clock signal XCX is at a high level, the odd number of inverters of the delay circuit 30 delays it and outputs a delay signal of logic ″ 0 ″. Therefore, the delay period starts when the clock signal XCK becomes the logic ″ 1 ″, and it is the delay period until the clock signal of the logic ″ 1 ″ applied to the inverter becomes the delay signal of the logic ″ 0 ″. .

Subsequently, the NAND gate of the output circuit receives a clock signal of logic ″ 1 ″ and a delay signal of logic ″ 1 ″, and combines them to output a signal of logic ″ 0 ″. The inverter 42 inverts the signal of logic ″ 0 ″ of the NAND gate to output a pulse signal PULSE of logic ″ 1 ″ of the same width but different levels.

3A and 3B are output waveform diagrams showing a problem that occurs when the high level time and the low level time of the clock signal are shorter than the delay period.

As shown in FIG. 3A, when the high level section (tCH, clock high time) of the internal clock signal is shorter than the delay section, the delay section is longer than the clock signal high level section to obtain a pulse signal. Rather, a problem occurs in that a pulse signal having a smaller width is generated. This results in a narrower SPEC range for the clock's high-level time as the chip gets higher frequencies.

In addition, as shown in FIG. 3B, when the low level time (tCL.clock low time) of the internal clock signal is shorter than the delay period, a pulse signal having a desired width is generated in the first clock, but is generated from the next period. The delayed clock is delayed and a small pulse signal is output. This is because the inverters of the delay circuit are connected in series, causing a delay across the inverter. Therefore, as the delay period becomes longer than a delay of a desired width, a problem occurs in that a pulse signal having a desired width is not generated.

Accordingly, an object of the present invention is to provide a pulse generator circuit for generating a pulse signal having a desired width regardless of whether the high level time of the internal clock signal is shorter than the delay period. Another object of the present invention is to provide a pulse generator circuit for generating a pulse signal having a desired width even if the low level time of the internal clock signal is not sufficient.

1A and 1B are circuit diagrams showing the configuration of a pulse generating circuit according to a conventional embodiment;

2A and 2B are output waveform diagrams according to the prior art embodiment;

3A and 3B are output waveform diagrams showing a problem that occurs when a conventional pulse high level and low level section is shorter than a delay section;

4 is a circuit diagram showing in detail the configuration of a pulse generating circuit according to the first embodiment of the present invention;

5 is an output waveform diagram when the high level time of the clock signal of FIG. 4 is shorter than a delay period;

6 is an output waveform diagram when a high level time of the clock signal of FIG. 4 is longer than a delay period;

7 is a circuit diagram showing details of a configuration of a pulse generating circuit according to a second embodiment of the present invention;

8 is an output waveform diagram when a low level time of the clock signal of FIG. 7 is shorter than a delay period;

FIG. 9 is an output waveform diagram when a low level time of the clock signal of FIG. 7 is longer than a delay period; FIG.

* Description of symbols on the main parts of the drawings *

100: inversion circuit 200: delay circuit

300: output circuit 400: inversion circuit

500: delay circuit 600: output circuit

(Configuration)

According to one aspect of the present invention, there is provided a semiconductor device having a circuit for receiving an external clock signal and generating a pulse signal, comprising: inverting means for receiving the external clock signal and inverting it; A delay means configured of at least two even-numbered logic gates, the external clock signal being applied as one input terminal, and a type force terminal connected to an output terminal of a previous stage to output a delay signal; And output means for receiving the external clock signal and the delay signal and outputting the pulse signal.

In a preferred embodiment of such a circuit, the logic gates of the delay means are NOR gates.

In a preferred embodiment of such a circuit, the logic gates of the delay means are NAND gates.

In a preferred embodiment of such a circuit, the output means includes one input terminal to which an external clock signal is applied, a type force terminal connected to an output terminal of the delay means, and an output terminal to which the pulse signal is output. And a NOR gate.

In a preferred embodiment of such a circuit, the output means comprises: a NAND gate having one input terminal to which an external clock signal is applied, a type force terminal connected to an output terminal of the delay means, and an output terminal; And an inverter having an input terminal connected to an output terminal of the NAND gate and an output terminal for outputting a pulse signal.

The circuit outputs a pulse signal having a width equal to the delay period even if the high level time and the low level time of the clock signal applied from the outside are shorter than the delay period.

(First embodiment)

The novel pulse generating circuit of the present invention provides a pulse signal having a width to be obtained even if the high level time or the low level time of the clock signal is short through a circuit which combines and delays a predetermined signal with a clock signal applied from the outside. .

Hereinafter, reference drawings according to a first preferred embodiment of the present invention will be described with reference to FIGS. 4 to 5 and 6.

4 is a circuit diagram showing in detail the configuration of the pulse generating circuit according to an embodiment of the present invention.

The pulse generating circuit is composed of an inverter 101, logic gates 201 202, 20N, and a NOR gate. The inverter receives a clock signal applied from the outside, inverts it, delays it, and outputs the same. In addition, the logic gates have a delay in each stage, and a predetermined delay period is generated after passing through the logic gate. The logic gates include a NOR gate 201 receiving the clock signal XCK and an inverted signal of an inverter, and the clock signal XCK is applied to one input terminal in common, and the output terminal and the other terminal of the front end. A plurality of NOR gates 201, 202, ..., 20N are connected to the input terminals. The NOR gates are gates for outputting a pulse signal, and a clock signal XCK is applied to one input terminal, and a type force terminal is applied to an output terminal A ′ of the last NOR gate 10N of the delay circuit 100. A NOR gate 301 to be connected is included.

Hereinafter, an operation in which the high level time of the clock signal is shorter than the delay period will be referred to as the first case, and the operation will be described as the second case where the high level time of the clock signal is longer than the delay period as follows.

5 shows an output waveform diagram of the pulse signal according to the first case where the high level time of the clock signal is shorter than the delay period.

As shown in FIG. 5, it can be seen that the high level time is short in the clock signal XCK generated inside the chip. When the clock signal XCK transitions from the low level to the high level, each NOR gate is very small, but delays and outputs the clock signal. The NOR gate has a characteristic of generating a low level signal when at least one of the input terminals is high level. Thus, the NOR gate combines the applied signals and causes them to fall directly to a low level.

When the next low level clock signal XCK is applied, the delay circuit 100 delays this by n * tD. When the delay period is determined by the inverter 101 and the NOR gates 201, 202,..., 20N, the NOR gate 301 outputs a pulse signal PULSE having a width equal to the delay period. Therefore, even when the clock signal XCK transitions from the low level to the high level, the level is changed after a slight delay due to the NOR gate 201.

6 shows an output waveform diagram of the pulse signal according to the second case where the high level time of the clock signal is longer than the delay period.

When the clock signal XCK transitions from the high level to the low level, the inverter 101 outputs a signal of logic ″ 1 ″, and the first NOR gate 201 is a clock signal of logic ″ 0 ″ and logic ″ 1. A delay signal of ″ is applied and a signal of logic ″ 0 ″ is output. Next, the second NOR gate 202 receives a signal of logic ″ 0 ″ and logic ″ 0 ″ and outputs a signal of logic ″ 1 ″. Since the number of NOR gates is an even number, a signal of logic " 1 " Therefore, it can be seen that the delay period is from the time when the clock signal XCK drops to the low level and before the A 'stage transitions to the high level. As a result, a pulse signal PULSE having a width corresponding to the delay period is generated by receiving the delay signal and the clock signal which are the low level of the delay period.

If the high level time of the clock signal is greater than the delay period caused by the inverter, a pulse signal having a width to be obtained may be output regardless of the high level period of the clock signal.

(Second embodiment)

Hereinafter, reference drawings according to a second preferred embodiment of the present invention will be described with reference to FIGS. 7 to 8 and 9.

7 is a circuit diagram showing in detail the configuration of the pulse generating circuit.

The pulse generating circuit is composed of an inverter 401, logic gates, and an output circuit 600. The inverter 401 receives an external clock signal XCK, inverts it, delays it, and outputs it. The logic gates are NAND gates, and are delayed and output for each gate. The logic gates include a first NAND gate 501 to which the clock signal is applied to one input terminal and an output terminal of the inverter is connected to a type force terminal. And NAND gates 502,..., 50N to which one input terminal is commonly applied with the clock signal XCK, and the output terminal of the preceding stage and the type force terminals are connected.

The output circuit 400 has a NAND gate 601 to which the clock signal XCK is applied to one input terminal, and a type force terminal is connected to an output terminal of the last NAND gate 50N among the logic gates. And an inverter 602 having an input terminal connected to an output terminal of the NAND gate 601. The delay of each stage of the inverter 401 and the NAND gates 501, 502,..., 50N is assumed to be tD, and the delay of the last n stages is n * tD (where n is odd). ) Is K = 1 stage, the next NAND gate 303 is K = 2 stages, ..., the final NOR gate 50N is composed of K = n stages.

Hereinafter, a case where the low level time of the clock signal is shorter than the delay period will be referred to as a first case, and a case where the low level time of the clock signal is longer than the delay period will be described as follows.

8 is an output waveform diagram of a pulse signal according to the first case.

Referring to FIG. 8, it can be seen that the low level time of the clock is very short. Assume that the output terminal of the delay circuit 300 is B and the output terminal of the NAND gate 401 of the output circuit 600 is C '. First, when the first high level clock signal XCK is applied, a delay signal delayed by n * tD through the inverter 401 and the NAND gates 501, 502, ..., 50N is output through B '. do. The NAND gate 601 receiving the delay signal and the high level clock signal XCK is combined with the signals and output through the C ′ terminal. Then, the inverter 602 of the output circuit 600 inverts the combined signal of the C 'stage and outputs a pulse signal PULSE having a width equal to n * tD in which the clock signal is delayed.

When the next clock signal XCK falls from a high level to a low level, a high level signal is generated directly from the NAND gate, thereby causing a slight delay. The NAND gate is capable of outputting a high level signal even when one input terminal is at a low level.

This has no effect on determining the pulse width, so a pulse signal (PULSE) having a width of n * tD delayed after 1 * tD and then across the NAND gates in the next clock signal. Is generated.

9 is an output timing diagram of the pulse signal according to the second case.

When the clock signal XCK transitions from the low level to the high level, the inverter 401 receiving the high level signal inverts it and transfers the low level signal to the type force terminal of the first NAND gate 501. Then, the second NAND gate 502 receives a high level clock signal XCK and a low level signal generated from the first NAND gate 501, and outputs a high level signal, and then a second NAND gate. In operation 502, the clock signal XCK of the high level and the output signal of the first NAND gate 301 of the high level are applied to output a signal falling to the low level. In this way, since there are even numbers of the NAND gates, a low level delay signal is generated in the B ′ stage.

Therefore, the delay period is a period from when the clock signal XCK transitions to a high level until a low level delay signal is generated at the final output terminal of the NAND gates receiving the high level clock signal. The output circuit 600 in the delay section receives the clock signal XCK and the delay signal, combines and inverts the clock signal XCK, and outputs a pulse signal having a width corresponding to the delay section.

As a result, even if the high level time and the low level time of the clock signal are shorter than the delay period, pulse signals having a width corresponding to the delay period are output regardless of this.

The pulse generation circuit as described above prevents the delay section from becoming longer than necessary by changing the configuration of the delay circuit even if the high level time and the low level time of the clock signal applied from the outside are shorter than the delay section. In addition, since the delay section generated from the delay circuit does not become long, there is an effect of outputting and using a pulse signal having a width equal to the required delay section.

Claims (5)

In a semiconductor device having a circuit that receives an external clock signal and generates a pulse signal, Inverting means for receiving the external clock signal and inverting it; A delay means configured of at least two even-numbered logic gates, the external clock signal being applied to one input terminal, and a type force terminal connected to an output terminal of a previous stage to output a delay signal; And output means for receiving the external clock signal and the delay signal and outputting the pulse signal. The method of claim 1, And the logic gates of said delay means are NOR gates. The method of claim 1, And the logic gates of the delay means are NAND gates. The method of claim 1, And the output means comprises a NOR gate having one input terminal to which an external clock signal is applied, a type force terminal connected to an output terminal of the delay means, and an output terminal to which the pulse signal is output. The method of claim 1, The output means includes: a NAND gate having one input terminal to which an external clock signal is applied, a type force terminal connected to an output terminal of the delay means, and an output terminal; And an inverter having an input terminal connected to an output terminal of the NAND gate and an output terminal for outputting a pulse signal.

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