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KR100410811B1 - METHOD FOR FORMING MULTI-LAYER METAL WIRING IN SEMICONDUCTOR - Google Patents

METHOD FOR FORMING MULTI-LAYER METAL WIRING IN SEMICONDUCTOR Download PDF

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Publication number
KR100410811B1
KR100410811B1 KR1019960023001A KR19960023001A KR100410811B1 KR 100410811 B1 KR100410811 B1 KR 100410811B1 KR 1019960023001 A KR1019960023001 A KR 1019960023001A KR 19960023001 A KR19960023001 A KR 19960023001A KR 100410811 B1 KR100410811 B1 KR 100410811B1
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Prior art keywords
insulating film
forming
metal wiring
metal
metal line
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KR980006147A (en
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김천수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a multilayer metal line of a semiconductor device is provided to be capable of relatively reducing resistance and improving the step coverage between metal lines. CONSTITUTION: The first metal line(20) is formed on an insulating layer(10). The first and second interlayer dielectric(30,40) are sequentially formed on the entire surface of the resultant structure. A via hole is formed by selectively etching the first and second interlayer dielectric for exposing the first metal line. An aluminum layer(50) is formed on the resultant structure by carrying out a selective CVD(Chemical Vapor Deposition) process. A CMP(Chemical Mechanical Polishing) process is performed on the aluminum layer until the second interlayer dielectric is exposed. An RF(Radio Frequency) etching process is performed on the resultant structure as a cleaning process by using Cl2 and Ar gas. The second metal line(60) is formed on the resultant structure.

Description

반도체 장치의 다층 금속배선 형성방법METHOD FOR FORMING MULTI-LAYER METAL WIRING IN SEMICONDUCTOR

본 발명은 반도체 소자의 제조 공정중 캐패시터 형성 이후의 공정으로 금속배선을 사용하여 인터-커넥션(Inter-Connection)을 형성하는 DLM(Double Layer Metalization) 공정에 관한 것으로, 특히 서브-쿼트 미크론(Sub-Quart Micron)의 미세한 크기를 고집적 소자의 다층 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DLM (Double Layer Metalization) process for forming an inter-connection using a metal wiring in a process after a capacitor is formed during a manufacturing process of a semiconductor device, Quart Micron), which is a highly integrated device.

일반적으로, 상ㆍ하부 금속배선간의 전기적 연결을 위한 비아홀을 형성한 다음, 금속배선간의 열악한 층덮힘(Step-Coverage)를 보안하기 위해 저압 화학 증착법(Low Pressure Chemical Vapor Deposition)에 의한 텅스텐을 선택 증착 방법에의해 플러그를 형성하였다.In general, a via hole is formed for electrical connection between upper and lower metal wirings, and then tungsten is selectively deposited by low pressure chemical vapor deposition (CVD) in order to secure poor step-coverage between metal wirings The plug was formed by the method.

그러나, 상기와 같은 선택적 증착법에 의한 텅스텐을 사용하여 플러그를 형성하게 될 경우 상ㆍ하부 금속배선간 상호연결(Interconnection)을 위한 비아홀의 저항이 너무 높아 서브-쿼트 미크론(Sub-Quart Micron)의 미세한 크기를 고집적 소자 제조가 어렵고, 또한 높은 전류에서도 전자이동이 용이하게 이루어지지 않는 등의 문제점이 있었다.However, when the plug is formed using tungsten by the selective deposition method as described above, the resistance of the via hole for interconnection between the upper and lower metal interconnection lines is too high, so that the sub-quart micron The size of the device is difficult to manufacture highly integrated devices, and electrons can not be easily moved even at a high current.

상기와 같은 문제점을 해결하기 위해 안출된 본 발명은 비교적 낮은 저항을 갖으면서 금속배선간의 열악한 층덮힘(Step-Coverage)를 보안할 수 있는 반도체 장치의 다층 금속배선 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming a multi-layered metal wiring of a semiconductor device that can secure a poor step-coverage between metal wirings while having a relatively low resistance .

상기 목적을 달성하기 위하여 안출된 본 발명의 다층 금속배선 형성방법은, 반도체 장치 제조 방법에 있어서, 기형성된 제1 금속배선상의 층간 절연막을 선택 식각하여 상기 제1 금속배선이 노출되는 비아홀을 형성하는 단계; 노출된 상기 제1 금속배선상에 선택적인 CVD 방법으로 알루미늄막을 형성하는 단계; 상기 층간절연막이 노출될때까지 상기 알루미늄막을 CMP하여 평탄화하는 단계; 염소 가스(Cl2) 및 아르곤 가스(Ar)를 사용한 RF 식각을 실시하여 세정처리하는 단계; 및 전체구조 상부에 제2 금속배선을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a multi-layer metal interconnection, comprising the steps of: selectively etching an interlayer insulating film on a previously formed first metal interconnection to form a via hole through which the first interconnection is exposed step; Forming an aluminum film on the exposed first metal wiring by a selective CVD method; Planarizing the aluminum film by CMP until the interlayer insulating film is exposed; Performing a cleaning process by performing RF etching using chlorine gas (Cl 2 ) and argon gas (Ar); And forming a second metal wiring over the entire structure.

이하, 첨부된 도면 제 1A 도 내지 제 1E 도를 참조하여 본 발명의 일실시예에 따른 반도체 장치의 다층 금속배선 형성방법을 상세히 설명한다.Hereinafter, a method for forming a multi-layer metal wiring of a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E.

먼저, 제 1A 도는 절연막(10)이 기형성된 기판상에 제1 금속막을 증착한 후,제1 금속배선 마스크를 이용하여 제1 금속배선(20)을 패터닝한 다음, 전체구조 상부에 CVD(Chemical Vapor Deposition ; 이하 CVD라 칭함)방식에 의한 제1 실리콘 산화막(SiO2)(30)을 형성한 것을 도시한 것이다.First, a first metal film is deposited on a substrate having an insulating film 10 formed thereon, and then the first metal interconnection 20 is patterned using a first metal interconnection mask. Then, a CVD (Chemical The first silicon oxide film (SiO 2 ) 30 is formed by CVD (Chemical Vapor Deposition) method.

제 1B 도는 상기 제1 실리콘 산화막(30)을 화학적 기계적 연마(Chemical Mechanical Polishing ; 이하 CMP라 칭함)에 의해 상기 제1 실리콘 산화막(30)을 평탄화한 것을 도시한 것이다.1B shows the first silicon oxide film 30 is planarized by chemical mechanical polishing (hereinafter referred to as CMP).

이때, 연마율은 1500Å/min 정도로 유지한다.At this time, the polishing rate is maintained at about 1500 A / min.

계속해서, 제 1C 도는 전체구조 상부에 CVD 방식에 의한 제2 실리콘 산화막(40)을 증착한 다음, 비아 콘택 마스크를 이용하여 하부 제1 금속배선(20)이 드러날때까지 제1 및 제2 실리콘 산화막(30, 40)을 차례로 식각하여 비아홀을 형성한 것을 도시한 것이다.1C, a second silicon oxide film 40 is deposited on the entire structure by a CVD method, and then the first and second silicon wafers 20 are etched by using a via contact mask until the underlying first metal wirings 20 are exposed. And the oxide films 30 and 40 are sequentially etched to form via holes.

이어서, 제 ID 도는 상기 비아홀에 선택적인(Selective) CVD 방식으로 알루미늄막(Al)(50)을 증착하여 알루미늄 플러그를 형성한 것을 도시한 것이다.Next, an aluminum film (Al) 50 is deposited on the via hole by a selective CVD method to form an aluminum plug.

마지막으로, 제 1E 도는 CMP 방식에 의해 튀어나온 헤드부의 알루미늄막(50)을 상기 제2 실리콘 산화막(40)이 드러날때까지 평탄화한 후, 평탄화된 표면을 염소 가스(Sl2)와 아르곤 가스(Ar)를 이용한 RF(Reflective Frequency) 식각에 의해 표면의 불순물들을 깨끗이 제거한 다음, 전체구조 상부에 제2 금속막을 증착한 후, 제2 금속배선 마스크를 이용하여 제2 금속배선(60)을 패터닝한 것을 도시한 것이다.Finally, the 1E turn after flattening the head of aluminum film 50 portion protruding by a CMP method until the second silicon oxide film 40 is revealed, chlorine a planarized surface gas (Sl 2) and argon gas ( Ar), the second metal film is deposited on the entire structure, and then the second metal interconnection 60 is patterned by using a second metal interconnection mask .

상기와 같이 이루어지는 본 발명은 상ㆍ하부 금속배선간 상호연결을 위한 비아홀을 형성한 후, 금속배선간의 열악한 층덮힘(Step-Coverage)을 메우기 위한 플러그로 텅스텐막 대신 알루미늄막을 사용함으로써 , 비교적 낮은 저항을 갖는 플러그 구조를 형성할 수 있어, 상ㆍ하부 금속배선간의 상호연결의 한계(Interconnection Pitch)를 극복할 수 있으며, 집적도를(Packing Density)를 증가시킬 수 있어 소자의 신뢰성을 향상시킬 수 있는 효과가 있다.In the present invention as described above, a via hole for interconnecting upper and lower metal interconnects is formed, and then an aluminum film is used instead of the tungsten film as a plug for filling up the poor step coverage of the metal interconnects, It is possible to overcome the interconnection pitch between the upper and lower metal wirings, to increase the packing density, and to improve the reliability of the device. .

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가지 자에게 있어 명백할 것이다.While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be obvious to those who have knowledge of

제 1A 도 내지 제 1E 도는 본 발명의 일실시예에 따른 반도체 장치의 다층 금속배선 형성 공정 단면도이다.1A to 1E are cross-sectional views illustrating a process of forming a multi-layer metal wiring of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

10 : 절연막 20 : 제 1 금속배선10: insulating film 20: first metal wiring

30 : 제1 실리콘 산화막 40 : 제2 실리콘 산화막30: first silicon oxide film 40: second silicon oxide film

50 : 알루미늄막 60 : 제2 금속배선50: aluminum film 60: second metal wiring

Claims (3)

반도체 장치 제조 방법에 있어서,A method of manufacturing a semiconductor device, 기형성된 제1 금속배선상의 층간 절연막을 선택 식각하여 상기 제1 금속배선이 노출되는 비아홀을 형성하는 단계;Selectively etching an interlayer insulating film on the formed first metal interconnection to form a via hole through which the first metal interconnection is exposed; 노출된 상기 제1 금속배선상에 선택적인 CVD 방법으로 알루미늄막을 형성하는 단계;Forming an aluminum film on the exposed first metal wiring by an optional CVD method; 상기 층간절연막이 노출될때까지 상기 알루미늄막을 CMP하여 평탄화하는 단계;Planarizing the aluminum film by CMP until the interlayer insulating film is exposed; 염소 가스(Cl2) 및 아르곤 가스(Ar)를 사용한 RF 식각을 실시하여 세정처리하는 단계; 및Performing a cleaning process by performing RF etching using chlorine gas (Cl 2 ) and argon gas (Ar); And 전체구조 상부에 제2 금속배선을 형성하는 단계Forming a second metal interconnection over the entire structure; 를 포함하여 이루어진 반도체 장치의 다층 금속배선 형성방법.Wherein the step of forming the multi-layer metal wiring comprises the steps of: 제 1 항에 있어서,The method according to claim 1, 상기 층간 절연막은 증착후 에치백되어 평탄화된 제1 절연막과 상기 제1 절연막상에 형성되는 제2 절연막으로 이루어지는 것을 특징으로 하는 반도체 장치의 다층 금속배선 형성방법.Wherein the interlayer insulating film comprises a first insulating film that is etched back after being deposited and is planarized and a second insulating film formed on the first insulating film. 제 2 항에 있어서,3. The method of claim 2, 상기 제1 절연막 및 제2 절연막은 실리콘 산화막(SiO2)인 것을 특징으로 하는 반도체 장치의 다층 금속배선 형성방법.Wherein the first insulating film and the second insulating film are silicon oxide films (SiO 2 ).
KR1019960023001A 1996-06-21 1996-06-21 METHOD FOR FORMING MULTI-LAYER METAL WIRING IN SEMICONDUCTOR Expired - Fee Related KR100410811B1 (en)

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KR940001375A (en) * 1992-06-27 1994-01-11 김주용 Metal wiring formation method of semiconductor device

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Publication number Priority date Publication date Assignee Title
KR940001375A (en) * 1992-06-27 1994-01-11 김주용 Metal wiring formation method of semiconductor device

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