KR100419281B1 - Transmitting Data Processor (TDP) and control method based on PMC in the Central Station for the Satellite Communication Systems - Google Patents

Abstract

The present invention has a function of receiving a traffic IP packet, management / control data, DVB-RCS signaling message, and DVB-SI message into a MPEG-2 TS packet at a central station transmitting a broadband multimedia service using satellite. As the transmission data processor and control method developed based on the PMC, PCI interface 210 for converting the bus signal of the CPU board 100 to the local data / address bus signal of the PMC board; A cam memory (CAM) 220 for storing and retrieving an IP address and a MAC address; A FIFO (230) for temporarily storing traffic or signaling data output by the CPU board (100) and then outputting them in synchronization with an output byte clock; A PCG 240 for generating a reference clock used in the transmission data processor and other timing signals provided externally; An RS-422 interface 260 for converting output data of a TTL level into an RS-422 electrical level and outputting the result to the outside; A DVB-ASI interface 270 for converting output data having a TTL level into a DVB-ASI signal and outputting the result to the outside; A line driver 280 electrically buffered to transmit a signal to an external PCI board; The cam memory 220, the FIFO 230, the PCG 240, and a programmable gate array (FPGA) 250 that performs overall control functions of the various output interfaces 260, 270, and 280 are included.

Description

Transmitting Data Processor (TDP) and control method based on PMC in the Central Station for the Satellite Communication Systems}

The present invention relates to a satellite data transmission data processor and a control method thereof. More specifically, the present invention relates to traffic IP (internet protocol) and management / Control data, DVB-RCS (Digital Video Broadcast-Return Channel Via Satellite, hereinafter referred to as 'DVB-RCS') signaling message and DVB-SI (Digital Video Broadcast-Service Information, hereinafter referred to as 'DVB-SI' It has a function to convert a message into an MPEG-2 transport stream (TS) packet and process it. It relates to a transmission data processor and control method developed based on PMC (PCI Mezzanine Card, hereinafter referred to as 'PMC'). .

At present, the Internet service over the terrestrial network has become a serious resource depletion due to the rapidly increasing number of subscribers and the widening and speeding up of the services provided. Technology development for services is underway.

In order to provide multimedia services using satellites, considering the characteristics of satellites, long Ethernet frames that can be transmitted by wire are cut into short MPEG-2 transport stream (TS) packets. The transmission technique can be applied, and information for link establishment and call establishment and resource allocation necessary for wireless communication can be processed through the same technique.

Devices capable of performing these functions enable one-way or two-way communication services through satellites, which are actively being developed worldwide.

However, the devices that have been developed or under development have low data rates, require a large amount of space to implement the devices, and have a problem of redesigning the transmission data processor to increase the transmission rate of the system.

Accordingly, an object of the present invention is to solve the above problems of the prior art, and to develop a transmission data processor and a control method thereof capable of providing a broadband satellite multimedia service, and is easily mounted on a general use CPU board and implemented. It is to facilitate.

1 is a block diagram to which a general transmission data processing apparatus is applied;

2 is a block diagram applying a satellite communication transmission data processor according to an embodiment of the present invention;

3 is a flowchart illustrating an operation method of controlling a satellite communication transmission data processor according to an exemplary embodiment of the present invention.

Satellite communication transmission data processor according to a feature of the present invention for achieving the above object,

In the satellite communication transmission data processor for converting the signal of the CPU board into satellite transmission data, and outputting

A PCI interface for converting a bus signal of the CPU board into a local data / address bus signal of the PMC board;

A cam memory for storing and retrieving an IP address and a MAC address;

A FIFO that temporarily stores the traffic or signaling data output by the CPU board and outputs the signal in synchronization with an output byte clock;

A programmable clock generator (PCG) for generating a reference clock used in the transmission data processor and other timing signals provided externally;

And a programmable gate array (FPGA) that performs overall control functions of the cam memory, the FIFO, the PCG, and the interface unit.

In the above, the interface unit,

An RS-422 interface for converting output data of a TTL level to an RS-422 electrical level and outputting the result to the outside;

A DVB-ASI interface for converting output data having a TTL level into a DVB-ASI signal and outputting the external signal;

It includes a line driver that is electrically buffered to deliver signals to external PCI boards.

The programmable gate array in the above,

Address Decoder, PCG Control Logic, Management / Control Register, PCI Interface Control Logic, CAM Control Logic, RS-422 Control Logic, DVB-ASI Control Logic, FIFO Control Logic, External Reference Clock and Timing Generation Logic, MPEG2-TS Packet Generation Performs control logic, null-packet generation logic, PCR (Program Clock Reference, hereinafter referred to as 'PCR')-packet generation logic, remultiplexing logic, and PCR counter logic functions.

The control method of the satellite communication transmission data processor according to a feature of the present invention for achieving the above object,

In the control method of the satellite communication transmission data processor for converting the signal of the CPU board into the data for satellite transmission and outputting,

Converting and buffering to local data;

Outputting a transport stream packet or a null packet according to the presence or absence of a transport stream packet when not in a PCR cycle;

In the case of a PCR cycle, generating and outputting a PCR packet;

And multiplexing the outputted data into a transport stream.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

As shown in Figure 2, the satellite communication transmission data processor according to an embodiment of the present invention,

A PCI interface 210 for converting a bus signal of the CPU board 100 into a local data / address bus signal of the PMC board;

A cam memory (CAM) 220 for storing and retrieving an IP address and a MAC address;

A FIFO (230) for temporarily storing traffic or signaling data output by the CPU board (100) and then outputting them in synchronization with an output byte clock;

A PCG 240 for generating a reference clock used in the transmission data processor and other timing signals provided externally;

An RS-422 interface 260 providing a function of converting output data of a TTL level to an RS-422 electrical level and outputting the result to the outside;

A DVB-ASI interface 270 for converting output data having a TTL level into a DVB-ASI signal and outputting the result to the outside;

A line driver 280 electrically buffered to transmit a signal to an external PCI board;

A programmable gate array (FPGA, 250) for performing overall control functions of the cam memory 220, the FIFO 230, the PCG 240, and the various interfaces 260, 270, and 280;

The programmable gate array 250 in the above,

Address Decoder, PCG Control Logic, Management / Control Register, PCI Interface Control Logic, CAM Control Logic, RS-422 Control Logic, DVB-ASI Control Logic, FIFO Control Logic, External Reference Clock and Timing Generation Logic, MPEG2-TS Packet Generation It performs control logic, null-packet generation logic, PCR-packet generation logic, remultiplexing logic, and PCR counter logic functions.

Operation of the embodiment of the present invention made as described above is as follows.

Transmitting Data Processor (TDP) receives the IP-based traffic data, the DVB-RCS signaling message and the DVB-SI message, and transmits the MPEG-2 TS packet for transmission through satellite to all terminal stations or specific terminal stations. It functions to reconfigure and output to the transport stream and to receive and process the management and control messages of the transmission data processor, and to collect the status information of the transmission data processor according to the status information request message and deliver it to the real time resource manager.

In addition, it performs the function of generating the PCR, reference clock and reference timing for system synchronization and distribution to the central station and the terminal station.

The entire function of the transmit data processor is implemented by separating the CPU board and PMC module.

That is, as shown in FIG. 1, the functions performed by the CPU board include an IP packet processing function, a PS packet generation function and a TS packet generation function block, and a management / control processing function block of a transmission data processor. Treated using.

3 is a flowchart illustrating a main data processing of TDP_PMC, and shows an operation flowchart of multiplexing MPEG2 null-packet and PCR-packets generated by the PMC by receiving output data from the CPU board 100.

On the other hand, the function performed by the PMC module has a functional outline as follows, and the functional configuration is as shown in FIG.

The PCI interface 210 converts the PCI bus signal of the CPU board 100 into a local data / address bus signal of the PMC board (S10).

The cam memory CAM provides a function of storing and retrieving a maximum of 4096 IP addresses and MAC addresses.

The FIFO 230 temporarily stores the traffic or signaling data output by the CPU board 100 and then outputs the synchronous signal to the output byte clock.

Programmable Clock Generator (PCG) 240 provides a reference clock required within the PMC board and an externally provided reference clock, and variable clock generation with two phase-locked loop (PLL) functions. Circuit.

Programmable gate array 250 generates address decoder, PCG control logic, management / control registers, PCI interface control logic, CAM control logic, RS-422 control logic, DVB-ASI control logic, FIFO control logic, external reference clock and timing generation. Performs logic, MPEG2-TS packet generation control logic, null-packet generation logic, PCR-packet generation logic, remultiplexing logic, and PCR counter logic functions:

The RS-422 interface 260 converts the output data of the TTL level into the RS-422 electrical level and outputs it to the outside. The maximum output speed is 20 Mbps.

The DVB-ASI interface 270 converts the output data of the TTL level into a DVB-ASI signal and outputs it externally, and the maximum output speed is 270Mbps.

The line driver 280 electrically buffers the signal to an external PCI board (receiving data processor or return link demodulator) through the J5 (or J3) connector-> PCI backplane of the P4 connector CPU board of the PMC module (S20). ).

Data input from the CPU board 100 via the PCI bus interface 210 is sequentially stored in the FIFO memory 230 (S20).

The PCR packet for system synchronization is generated and multiplexed at regular time intervals and output to the on-timing first compared to the traffic or bitstream transport stream packet (S40).

The traffic transport stream packet is stored in the FIFO memory and output through the ASI interface according to the transport stream output rate (S60).

In addition, when there is no buffered TS packet so that the output MPEG-2 TS packet always maintains a constant rate, a Null-TS packet is generated and output (S70).

In addition, MAC address retrieval, reference clock and timing generation, and external interface functions are handled independently by CUP control.

Accordingly, the present invention operating as described above, by converting the user traffic and control / management information, signaling information, resource allocation information, etc. consisting of the Ethernet frame into a packet suitable for the satellite environment it is possible to transmit a broadband satellite multimedia service It works.

In addition, the present invention facilitates implementation by mounting on a general commercial CPU board due to the development of the TDP-PMC board according to the standard.

Therefore, the present invention operating as described above can be easily implemented by mounting the TDP-PMC board on a general commercial CPU board to be used, and simply by replacing the high-speed CPU board to transfer higher speed data. It can be effective.

Claims (4)

In the satellite communication transmission data processor for converting the signal of the CPU board into satellite transmission data, and outputting A PCI interface for converting a bus signal of the CPU board into a local data / address bus signal of the PMC board; A cam memory for storing and retrieving an IP address and a MAC address; A FIFO that temporarily stores the traffic or signaling data output by the CPU board and outputs the signal in synchronization with an output byte clock; A PCG 240 for generating a reference clock used in the transmission data processor and other timing signals provided externally; And a programmable gate array configured to perform overall control functions of the cam memory, the FIFO, the PCG, and the interface unit. The method of claim 1, wherein the interface unit, An RS-422 interface providing a function of converting output data of a TTL level to an RS-422 electrical level and outputting the result to the outside; A DVB-ASI interface for converting output data having a TTL level into a DVB-ASI signal and outputting the external signal; Satellite communication transmission data processor including a line driver electrically buffered to transmit signals to an external PCI board. The method of claim 1, wherein the programmable gate array, Address Decoder, PCG Control Logic, Management / Control Register, PCI Interface Control Logic, CAM Control Logic, RS-422 Control Logic, DVB-ASI Control Logic, FIFO Control Logic, External Reference Clock and Timing Generation Logic, MPEG2-TS Packet Generation A satellite communications data processor that performs control logic, null-packet generation logic, PCR-packet generation logic, remultiplexing logic, and PCR counter logic functions. In the control method of the satellite communication transmission data processor for converting the signal of the CPU board into the data for satellite transmission and outputting, Converting and buffering to local data; Outputting a transport stream packet or a null packet according to the presence or absence of a transport stream packet when not in a PCR cycle; In the case of a PCR cycle, generating and outputting a PCR packet; And multiplexing the outputted data into a transport stream and outputting the multiplexed data.