KR100414758B1 - Integrated circuit for supplying a clock signal and method for constructing the same - Google Patents

Abstract

Conventionally, since the difference in the delay time of the clock tree is adjusted using a delay circuit, the phase of the clock signal changes due to the diffusion condition or the temperature change during the LSI operation. In addition, since the delay circuit must be designed every time a design change or a characteristic improvement is executed, the design period becomes long.

The clock tree 227 is composed of three stages of the 3.3 V voltage source operation buffer circuits 201 to 210 and 228, and all use a circuit which operates from the 3.3 V voltage source. Clock signal transfer time from clock input terminal 100 to clock terminal of 3.3 V voltage source operation flip-flop 106 and clock signal from clock input terminal 100 to clock terminal of 2.5 V voltage source operating flip flop 119 The delivery times are equal.

Description

Integrated circuit for clock signal supply and its construction method {INTEGRATED CIRCUIT FOR SUPPLYING A CLOCK SIGNAL AND METHOD FOR CONSTRUCTING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for supplying a clock signal and a method of constructing the same, and more particularly to a circuit for configuring a circuit using a plurality of voltage sources within an LSI and for performing data transfer between storage means of different voltage sources in the circuit. The present invention relates to an integrated circuit for supplying a clock signal called a clock tree for supplying a circuit and a method of manufacturing the same.

In large-scale semiconductor integrated circuits (hereinafter referred to as LSIs), they are often designed as synchronous circuits that operate in synchronization with clock signals. The synchronous circuit has advantages such as easy logic synthesis, but when the phase shift of the clock signal supplied to the storage means occurs, data transfer between the storage means cannot be performed normally.

As a clock signal supply circuit for easily matching the phase of a clock signal, a clock signal supply circuit called a clock tree is known. This clock tree is a clock driver circuit that supplies a clock signal to a plurality of storage means by using a buffer circuit configured in a tree shape.

If the storage means is, for example, a flip-flop, the clock tree connects several buffer circuits of the second stage to the output of the first stage buffer circuit, and the clock terminals of the almost same number of flip-flops are usually connected to each of the outputs of the second stage buffer circuit. Configure to connect. In this way, the buffer circuit is configured in a tree shape, and the clock signal is supplied to the clock terminal of the flip-flop connected to the clock tree end by supplying the clock signal to the input of the first stage buffer circuit.

As an advantage of using the clock tree, even if the number of flip-flops or the chip area of the LSI changes during the design, the gate length or gate width of the transistor constituting the buffer circuit and the number of stages of the buffer circuit are changed so that the flip of the clock tree ends. The point is that the clock signal of the same phase can be supplied to the flop.

However, with the improvement of semiconductor manufacturing process technology, it is possible to develop high-density LSI, but the power consumption is increased by increasing the number of transistors in the LSI. Therefore, a method of reducing power consumption by lowering the voltage of the voltage source of some functional blocks inside the LSI has been used.

In the case of designing an LSI using such a plurality of voltage sources, a circuit is conventionally arranged by dividing an arrangement area on the LSI for each voltage source. Therefore, the clock trees of the functional blocks with different voltage sources were generated separately from the clock trees of the other functional blocks and operated with different voltage sources.

In general, the delay time from the change of the gate input signal to the change of the output signal changes when the voltage source of the gate is changed. Therefore, the buffer circuit of the clock tree also changes the delay time when the voltage of the voltage source changes. This state is shown in FIG. Fig. 5 shows a change in delay time when a clock signal is supplied to a clock tree composed of two stage buffer circuits and operated with different voltage sources.

As shown in this figure, when the same clock signal is supplied to the clock tree of the high voltage source and the clock tree of the low voltage source, when the clock signal is transmitted to the output of the second stage buffer circuit at the ends of the two clock trees, The clock tree side is delayed T1 time compared to the clock tree of the high voltage source. For example, in the circuit configuration of FIG. 3 to be described later, in the case of the 3.3 V voltage source and the 2.5 V voltage source in the 0.35 micron process, the time difference T1 becomes 0.6 ms.

In the case of a synchronous circuit which performs data transfer between a functional block having a lower voltage source and another functional block, it is necessary to supply clock signals of the same frequency and phase to not only the flip-flops with the same voltage source but also the flip-flops with different voltage sources. The delay circuit is used to compensate for the time difference T1. This ensures that the clock signals supplied to all flip-flops are phased to ensure normal data transfer between blocks with different voltage sources.

The reason for compensating the time difference T1 by using the delay circuit is that if the compensation is made by changing the gate length or gate width of the buffer circuit in the clock tree, the buffer circuit area needs to be changed, so that the buffer circuit after the change can be arranged. This is because there may be a case.

3 is a block diagram showing an example of a conventional clock signal supply integrated circuit for supplying a clock signal to such a multi-voltage source block. This conventional circuit is an example having two types of voltage sources, a 3.3 V voltage source and a 2.5 V voltage source, as the voltage source. In FIG. 3, the clock input terminal 100 is a terminal to which a clock signal generated by an external terminal of the LSI or a clock generator inside the LSI is input. The clock input terminal 100 is connected to the clock tree 129, while connected to the clock tree 128 via the 3.3 V voltage source operation delay circuit 127.

Clock tree 128 is a clock tree of a 3.3 V voltage source and clock tree 129 is a clock tree of a 2.5 V voltage source. The flip-flop groups 110 to 113 of the 3.3 V voltage source are connected to the clock tree 128, and the flip-flop groups 123 to 126 of the 2.5 V voltage source are connected to the clock tree 129.

Next, the configuration of the clock trees 128 and 129 will be described in detail. The clock tree 128 consists of two stages of the 3.3 V voltage source operation buffer circuits 101, 102, 103, 104 and 105, and uses a circuit which all operate with the 3.3 V voltage source. The input of the 3.3 V voltage source operating buffer circuit 101 is connected to the output of the 3.3 V voltage source operating delay circuit 127, and the input of the 3.3 V voltage source operating buffer circuit 102 to 105 is the 3.3 V voltage source operating buffer circuit 101. Is connected to the output of The flip-flops operating with the 3.3 V voltage source connected to the outputs of the 3.3 V voltage source operation buffer circuits 102 to 105 are divided into the 3.3 V voltage source operating flip flop groups 110 to 113 so as to be connected in the same number.

Each clock terminal of the 3.3 V voltage source operation flip flops 106 to 109 constituting the 3.3 V voltage source operation flip flop group 110 is commonly connected to the output of the 3.3 V voltage source operation buffer circuit 102. Similarly, clock terminals of the plurality of flip-flops of the 3.3 V voltage source operation flip flop groups 111 to 113 are connected to the outputs of the 3.3 V voltage source operation buffer circuits 103 to 105, respectively.

The clock tree 129 is constituted of two stages of the 2.5V voltage source operation buffer circuits 114 to 118, and all use circuits that operate from the 2.5V voltage source. The input of the 2.5 V voltage source operating buffer circuit 114 is connected to the clock input terminal 100, and the input of the 2.5 V voltage source operating buffer circuit 115 to 118 is connected to the output of the 2.5 V voltage source operating buffer circuit 114. have. The flip-flops operating from the 2.5 V voltage sources connected to the outputs of the 2.5 V voltage source operating buffer circuits 115 to 118, respectively, are divided into 2.5 V voltage source operating flip flop groups 123 to 126 so as to be connected in the same number.

Each clock terminal of the 2.5 V voltage source operation flip flops 119 to 122 constituting the 2.5 V voltage source operation flip flop group 123 is commonly connected to the output of the 2.5 V voltage source operation buffer circuit 115. Similarly, the clock terminals of the flip-flops of the 2.5 V voltage source operation flip flop groups 124 to 126 are connected to the outputs of the 2.5 V voltage source operation buffer circuits 116 to 118, respectively.

FIG. 4 is a layout diagram showing the layout of an example of the conventional clock signal supply integrated circuit shown in FIG. In this figure, the 3.3V voltage source region 301 has a ground wiring 302, a 3.3V voltage source wiring 303, buffer circuits 101-105 of the clock tree 128, and a flip-flop of a 3.3V voltage source. And a random circuit 131 between the flip-flops and a 3.3 V voltage source operation delay circuit 127 are disposed. In the 2.5 V voltage source region 325, the ground wiring 313, the 2.5 V voltage source wiring 314, the buffer circuits 114 to 118 of the clock tree 129, and flip-flops of the 2.5 V voltage source are disposed.

3.3 V voltage source operation buffer circuit 101 to 105, 2.5 V voltage source operation buffer circuit 114 to 118, 3.3 V voltage source operation flip flop 106 to 109, 2.5 V voltage source operation flip flop 119 to 122, the 3.3 V voltage source operation delay circuit 127 and the random circuit 131 are layout cells.

A layout cell is a figure which shows layout information, such as a flip-flop and a buffer circuit. The layout cell has ground and voltage source terminals at the upper and lower ends thereof. The layout cell is rotated by 90 degrees when arranged to connect the voltage source terminal of the layout cell and the voltage source wiring, and the ground terminal and the ground wiring of the layout cell.

Next, the structure of the ground wiring 302, the 3.3V voltage source wiring 303, the ground wiring 313, and the 2.5V voltage source wiring 314 is demonstrated in detail.

The ground wiring 302 is wired in the horizontal direction with the periphery of the 3.3 V voltage source region 301. The 3.3 V voltage source wiring 303 is wired at regular intervals so as to be paired with the ground wiring 302 in the horizontal direction with respect to the 3.3 V voltage source region 301. The ground wiring 313 is wired in the horizontal direction with the periphery of the 2.5 V voltage source region 325. The 2.5 V voltage source wiring 314 is wired at regular intervals so as to be paired with the ground wiring 313 in the horizontal direction around the 2.5 V voltage source region 325.

Next, the configuration of the clock tree and the flip-flop in the 3.3 V voltage source region 301 will be described in detail. 3.3V Voltage Source Operation Flip-flops 106 to 109 are disposed between the ground wiring 302 and the 3.3V voltage source wiring 303. The 3.3V voltage source operation buffer circuits 101 and 102 are also disposed between the ground wiring 302 and the 3.3V voltage source wiring 303, respectively. The clock terminal of the 3.3 V voltage source operation flip-flops 106 to 109 is connected to the output terminal of the 3.3 V voltage source operation buffer circuit 102.

The input terminal of the 3.3 V voltage source operation buffer circuits 102 to 105 is connected to the output terminal of the 3.3 V voltage source operation buffer circuit 101. Although not shown in Fig. 4, the clock terminals of the flip-flops of the 3.3 V voltage source operation flip flop groups 111 to 113 are connected to the output terminals of the 3.3 V voltage source operation buffer circuits 103 to 105, respectively.

Next, the configuration of the clock tree and the flip-flop in the 2.5 V voltage source region 325 will be described in detail. The 2.5V voltage source operation flip-flops 119 to 122 are disposed between the ground wiring 313 and the 2.5V voltage source wiring 314. The 2.5 V voltage source operation buffer circuits 114 and 115 are also disposed between the ground wiring 313 and the 2.5 V voltage source wiring 314. The clock terminal of the 2.5 V voltage source operation flip-flops 119 to 122 is connected to the output terminal of the 2.5 V voltage source operation buffer circuit 115.

The input terminals of the 2.5 V voltage source operation buffer circuits 115 to 118 are connected to the output terminals of the 2.5 V voltage source operation buffer circuit 114. Although not shown in Fig. 4, the clock terminals of the flip-flops of the 2.5V voltage source operation flip-flop groups 124 to 126 are connected to the output terminals of the 2.5V voltage source operation buffer circuits 116 to 118, respectively.

Next, the configuration between the clock input terminal 100 and the clock trees 128 and 129 will be described in detail. The 3.3 V voltage source operation delay circuit 127 is disposed between the ground wiring 302 and the 3.3 V voltage source wiring 303. The input terminal of the 3.3 V voltage source operation buffer circuit 101 is connected to the output terminal of the delay circuit 127. The clock input terminal 100 is connected to the input terminals of the 2.5 V voltage source operation buffer circuit 114 and the 3.3 V voltage source operation delay circuit 127, respectively.

The data output terminal of the 3.3 V voltage source operating flip-flop 106 is connected to the input terminal of the random circuit 131, and the output terminal of the random circuit 131 is connected to the data input terminal of the 2.5 V voltage source operating flip-flop 119. Connected.

In FIG. 3, the clock signal transfer time from the clock input terminal 100 to the 2.5 V voltage source operation flip-flop 119 is the wiring delay time until input to the 2.5 V voltage source operation buffer circuit 114, and 2.5. The gate delay time of the V voltage source operation buffer circuit 114, the wiring delay time until input to the 2.5V voltage source operation buffer circuit 115, the gate delay time of the 2.5V voltage source operation buffer circuit 115, and The sum of the wiring delay time until inputting to the V voltage source operation flip-flops 119 to 122.

The total time is the same at the clock terminal portion of each flip-flop so that a clock signal can be supplied to the clock terminal of each flip-flop connected to the clock tree 129 at the same timing. Specifically, the wiring delay time until input to the second stage 2.5 V voltage source operation buffer circuits 115 to 118 is the same, and the gate delay time of the 2.5 V voltage source operation buffer circuits 115 to 118 is equal to 2.5. The wiring delay time until inputting to the V voltage source operation flip-flop 119 is the same.

The gate delay time is determined by the gate length and gate width of the transistor, and the wiring delay time is determined by the gate length of the transistor, the gate width, and the wiring capacitance attached to the output of the transistor. Therefore, the gate lengths and gate widths of the transistors in the buffer circuit of the same layer are equalized so that the wiring capacitance is equal in the wiring of the same layer. Therefore, the clock signal supplied to the clock terminal of the flip-flop connected to the clock tree 129 has the same timing. The same applies to the clock tree 128.

As described above, the delay time from the input of the clock trees 128 and 129 to the clock terminal of the flip-flop at the end is equalized so that the phase of the clock signal supplied to each flip-flop is adjusted.

However, because the clock tree 128 and the clock tree 129 are different in the voltage source of the buffer circuit, the gate delay time and the wiring delay time are different, so that between the clock input terminal 100 and the input of the clock tree 128 is 3.3. The delay time is adjusted by inserting the V voltage source operation delay circuit 127. Therefore, a clock signal of the same timing is transmitted to the clock terminals of the flip-flop connected to the clock tree 128 and the flip-flop connected to the clock tree 129.

As described above, it is possible to normally perform data transfer between blocks with different voltage sources, such as data transfer from the 3.3 V voltage source operation flip flop 106 through the random circuit 131 to the 2.5 V voltage source operation flip flop 119. .

Next, a method of configuring such a conventional clock signal supply integrated circuit will be described in detail with reference to FIG.

First, an area 301 for placing 3.3 V layout cells and an area 325 for placing 2.5 V layout cells are created. Subsequently, the 3.3 V voltage source wiring 303 and the ground wiring 302 of the 3.3 V voltage source region 301 and the 2.5 V voltage source wiring 314 and the ground wiring 313 of the 2.5 V voltage source region 325 are shown in FIG. 4 and FIG. Wire together. Subsequently, a 3.3 V layout cell other than the clock tree in the 3.3 V voltage source region 301 is disposed between the ground wiring 302 and the 3.3 V voltage source wiring 303, and 2.5 2.5 other than the clock tree in the 2.5 V voltage source region 325. The V layout cell is disposed between the ground wiring 313 and the 2.5 V voltage source wiring 314.

Subsequently, the clock tree of the 3.3 V voltage source region 301 is arranged and wired. Since the flip-flops connected to the 3.3 V voltage source operating buffer circuits 102 to 105 have the same configuration, the 3.3 V voltage source operating buffer circuit 102 is described below. It demonstrates.

First, the 3.3 V voltage source operation buffer circuit 102 is disposed between the ground wiring 302 and the 3.3 V voltage source wiring 303 located at the center of the 3.3 V voltage source operating flip-flops 106 to 109. Subsequently, the output terminal of the 3.3 V voltage source operation buffer circuit 102 and the clock terminals of the 3.3 V voltage source operation flip-flops 106 to 109 are connected by bypass wiring in some cases so that the wiring capacitance is equalized.

Subsequently, the 3.3 V voltage source operation buffer circuit 101 is disposed between the ground wiring 302 and the 3.3 V voltage source wiring 303 at the center position of the 3.3 V voltage source operation buffer circuits 102 to 105. Subsequently, the output terminal of the 3.3 V voltage source operation buffer circuit 101 and the input terminal of the 3.3 V voltage source operation buffer circuits 102 to 105 are connected by bypass wiring in some cases, so that the wiring capacitance is equalized. The above is the arrangement and wiring method of the clock tree in the 3.3 V voltage source region 301.

Next, the clock tree of the 2.5 V voltage source region 325 is arranged and wired. Since the flip-flops connected to the 2.5 V voltage source operating buffer circuits 115 to 118 have the same configuration, the 2.5 V voltage source operating buffer circuit 115 is described below. It demonstrates.

First, the 2.5 V voltage source operation buffer circuit 115 is disposed between the ground wiring 313 and the 2.5 V voltage source wiring 314 located at the center of the 2.5 V voltage source operating flip-flops 119 to 122. Subsequently, the output terminal of the 2.5 V voltage source operating buffer circuit 115 and the clock terminals of the 2.5 V voltage source operating flip-flops 119 to 122 are connected by bypass wiring in some cases so that the wiring capacitance is equalized.

Subsequently, the 2.5 V voltage source operation buffer circuit 114 is disposed between the ground wiring 313 and the 2.5 V voltage source wiring 314 at the center position of the 2.5 V voltage source operation buffer circuits 115 to 118. Subsequently, the output terminal of the 2.5 V voltage source operating buffer circuit 114 and the input terminal of the 2.5 V voltage source operating flip-flops 115 to 118 are connected by bypass wiring in some cases so that the wiring capacitance is equalized. The above is the arrangement, wiring method, that is, the configuration method of the clock tree in the 2.5 V voltage source region 325.

Next, the transfer time of the clock tree arrange | positioned and wired in 3.3V voltage source area | region 301 and 2.5V voltage source area | region 325 is measured. The value closest to the difference between the measured transfer time and n times the gate delay time of the buffer circuit is obtained.

Next, a delay circuit 127 in which n buffer circuits are connected in series is created. The 3.3 V voltage source operation delay circuit 127 is disposed between the ground wiring 302 and the 3.3 V voltage source wiring 303 of the 3.3 V voltage source region 301, and the output terminal of the 3.3 V voltage source operation delay circuit 127 is 3.3 V. It is connected to the input terminal of the voltage source operation buffer circuit 101.

Finally, the clock input terminal 100 is connected to the input terminal of the 2.5 V voltage source operation buffer circuit 114 and the input terminal of the 3.3 V voltage source operation delay circuit 127, respectively. At this time, from the clock input terminal 100 to the input terminal of the 3.3 V voltage source operation delay circuit 127 and the input terminal of the 2.5 V voltage source operation buffer circuit 114, in some cases, the wiring is bypassed so that the transfer time is the same. do.

When the connection is made, for example, the wiring in the longitudinal direction uses the second aluminum wiring, and the wiring in the lateral direction uses the first aluminum wiring, so that the aluminum wiring layer is changed so that the voltage source wiring and the ground wiring are not shorted. Further, the first aluminum wiring and the second aluminum wiring are connected by the first through hole to connect the longitudinal wiring and the lateral wiring.

By the way, conventionally, the delay circuit 127 adjusts the difference between the delay time of the clock tree of the functional block having a lower voltage source and other functional blocks, and the delay circuit 127 is a diffusion condition at the time of LSI manufacturing. When the temperature during the LSI operation changes, the gate delay time changes, and as a result, the phase of the clock signal supplied to the storage means of the functional blocks of different voltage sources is changed.

Therefore, in the related art, when the diffusion conditions at the time of manufacturing LSI or the temperature at the time of LSI operation change, a synchronous circuit which performs data transfer between a functional block having a lower voltage source and another functional block cannot accurately transmit data. There is a problem that the synchronous circuit design is difficult.

In addition, conventionally, whenever a layout design is executed due to a function change, a characteristic improvement, or the like, the layout position or wiring path of the layout changes, the buffer circuit of the clock tree, or the placement position or wiring path of the storage means also changes. Since it is necessary to design the delay circuit by measuring the propagation time, there is also a problem that the design period is long because the delay circuit must be designed every time a design change or a characteristic improvement is performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and by using a clock tree composed of a common voltage source without using a delay circuit, the memory circuit of a different voltage source may be changed even if the diffusion conditions in LSI manufacturing or the temperature in LSI operation change. An object of the present invention is to provide an integrated circuit for supplying a clock signal and a configuration method thereof capable of supplying a clock signal of the same phase to the same phase to normally perform data transfer between blocks of different voltage sources.

Another object of the present invention is to provide an integrated circuit for supplying a clock signal and a method of manufacturing the same, which can reduce the design time.

1 is a block diagram showing one embodiment of an integrated circuit for clock signal supply according to the present invention.

Fig. 2 is a layout for explaining an embodiment of a configuration method of an integrated circuit for clock signal supply according to the present invention.

3 is a block diagram showing an example of a conventional integrated circuit for supplying clock signals.

4 is a layout for explaining an example of a configuration method of a conventional integrated circuit for supplying clock signals.

5 is a timing chart diagram of a clock tree.

6 is a diagram illustrating a transistor model.

* Description of the symbols for the main parts of the drawings *

100: clock input terminal

101 to 105, 201 to 210, 228: 3.3 V voltage source operating buffer circuit

106 to 109: 3.3 V voltage source operation flip-flop

110 to 113: 3.3V voltage source operation flip flop group

114 to 118: 2.5 V voltage source operating buffer circuit

119 to 122: 2.5 V voltage source operation flip flop

123-126: 2.5V voltage source operation flip flop group

127: 3.3 V voltage source operation delay circuit 128,129,227: clock tree

130: data signal input terminal 131,132: random circuit

402: 3.3 V voltage source wiring 401: ground wiring

403: 2.5 V voltage source wiring

404: 3.3 V, 2.5 V common voltage source area

605: P-type channel transistor 606: N-type channel transistor

607: voltage source 608: load capacity

The present invention provides a clock signal supply integrated circuit for distributing and supplying a clock signal through a plurality of stages of buffer circuits connected in a tree shape to a plurality of storage means using different voltage sources in order to achieve the above object. A plurality of stages of buffer circuits connected in a shape are operated as the highest voltage sources among different voltage sources and the clock signals are transmitted at the same delay time. The clock signal is supplied to a plurality of storage means using the above.

In the present invention, even if there are a plurality of voltage sources, the clock signal is supplied to a plurality of storage means using different voltage sources through a plurality of stage buffer circuits using a common voltage source. Although the transfer time of the circuit varies, the wiring capacitance of the circuit for transferring the clock signal supplied to the plurality of storage means can be the same, and the delay circuit existing between the conventional clock input terminal and the input of the buffer circuit of the plurality of stages can be used. The integrated circuit for clock signal supply can be created without using.

In addition, according to the configuration method of the present invention, a plurality of different voltage source wirings and ground wirings are wired into one arrangement area, and a plurality of storage means using different voltage sources are used by the storage means for voltage source wiring and ground, respectively. Arranged between the wirings, and a plurality of stage buffer circuits are arranged in the arrangement region and between the highest voltage source voltage source wiring and the ground wiring among the different voltage sources, connected in a tree shape, and the first stage buffer circuit among the buffer circuits of the multiple stages. Is connected to the clock signal input terminal, and the output terminal of the buffer circuit of the last stage among the buffer circuits of the plurality of stages is connected to the clock terminals of the plurality of storage means, respectively.

In the present invention, when the voltage source A and the voltage source B are used, the ground, the voltage source A, and the voltage source B are wired in the arrangement area, and then the storage means using the voltage source A and the voltage source B is provided between the wiring and the ground line of the voltage source A or the voltage source. Arrange between B wiring and ground line. A plurality of stages of buffer circuits are arranged in the arrangement area and connected between the highest voltage source voltage source wiring and the ground wiring among the different voltage sources and connected in a tree shape. This makes it easier to arrange an integrated circuit using one of the plurality of voltage sources.

Embodiment of the Invention

Next, embodiment of this invention is described with drawing. Fig. 1 shows a block diagram of one embodiment of a clock signal supply integrated circuit according to the present invention for supplying a clock signal to a multivoltage source block. In the drawings, the same components as in FIG. 3 are assigned the same reference numerals. The embodiment shown in FIG. 1 is an example having two types of voltage sources of 3.3V voltage source and 2.5V voltage source as the voltage source as in the conventional example, and changes only the clock tree portion of the conventional example shown in FIG.

In FIG. 1, the clock input terminal 100 is connected to a clock tree 227. The clock tree 227 is connected to the 3.3 V voltage source operating flip flop groups 110 to 113 and the 2.5 V voltage source operating flip flop groups 123 to 126.

Next, the configuration of the clock tree 227 will be described in detail. The clock tree 227 is composed of three stages of the 3.3V voltage source operation buffer circuits 201 to 210 and 228, and all use a circuit which operates from the 3.3V voltage source. The input of the first 3.3 V voltage source operation buffer circuit 201 is connected to the clock input terminal 100. Each input terminal of the second stage 3.3V voltage source operation buffer circuit 202 and 228 is connected to an output terminal of the 3.3V voltage source operation buffer circuit 201. Each input terminal of the third stage 3.3V voltage source operation buffer circuit 203 to 206 is connected to the output terminal of the 3.3V voltage source operation buffer circuit 202. In addition, each input terminal of the third stage 3.3V voltage source operation buffer circuit 207 to 210 is connected to the output terminal of the 3.3V voltage source operation buffer circuit 228.

The output terminals of the 3.3 V voltage source operation buffer circuits 203 to 210 are connected to the 3.3 V voltage source and the 2.5 V voltage source, and they are connected to the 3.3 V voltage source operating flip flop groups 110 to 113 so as to be connected in the same number. It is divided into 2.5V voltage source operation flip-flop groups 123-126. The flip-flop groups do not need to be gathered as flip-flops of the same voltage source, but in this embodiment, the flip-flops operated by the 3.3 V voltage source and the flip-flops operated by the 2.5 V voltage source are connected to the output of the buffer circuit as in the conventional example. Doing.

Each clock terminal of the 3.3 V voltage source operation flip flops 106 to 109 constituting the 3.3 V voltage source operation flip flop group 110 is connected to an output terminal of the 3.3 V voltage source operation buffer circuit 203. Each clock terminal of the 2.5 V voltage source operation flip flops 119 to 122 constituting the 2.5 V voltage source operation flip flop group 123 is connected to the output terminal of the 3.3 V voltage source operation buffer circuit 207. Similarly, the clock terminals of the flip-flops that constitute the 3.3 V voltage source operating flip-flop groups 111 to 113 and the 2.5 V voltage source operating flip flop groups 124 to 126, respectively, are the 3.3 V voltage source operating buffer circuits 204 to 206, respectively. And 208 to 210 output terminals.

Next, a method of arranging a clock signal supply integrated circuit having such a configuration (a method of arranging clock tree elements) will be described in detail with reference to FIG. In FIG. 2, the same code | symbol is attached | subjected to the same component as FIG. 1 and FIG.

In Fig. 2, the 3.3V and 2.5V common voltage source region 404 has a ground wiring 401, a 3.3V voltage source wiring 402, a 2.5V voltage source wiring 403, and a 3.3V voltage source operation flip-flop ( F / F) 106 to 109, 2.5 V voltage source operation flip flop (F / F) 119 to 122, random circuits 131 and 132 between flip flops, and 3.3 V voltage source clock tree 227 Are arranged respectively.

Next, the structure of the ground wiring 401, the 3.3V voltage source wiring 402, and the 2.5V voltage source wiring 403 will be described in detail.

The 3.3V voltage source wiring 402 and the 2.5V voltage source wiring 403 are wired at a predetermined interval from each other in the horizontal direction and around the 3.3V and 2.5V common voltage source region 404, respectively. In addition, the ground wiring 401 is spaced at regular intervals so as to be paired with the 3.3 V voltage source wiring 402 and the 2.5 V voltage source wiring 403 in the horizontal direction around the 3.3 V and 2.5 V common voltage source region 404. do.

Next, the configuration of the clock tree 227 and the flip-flop will be described in detail.

The 3.3V voltage source operation flip-flops 106 to 109 connected to the clock tree 227 shown in FIG. 1 are disposed between the ground wiring 401 and the 3.3V voltage source wiring 402 as shown in FIG. The 3.3 V voltage source operating buffer circuit 203 of the clock tree 227 is disposed between the ground wiring 401 and the 3.3 V voltage source wiring 402, and the 3.3 V voltage source operating flip-flops 106, 107, 108 and 109 in the clock tree 227. Each clock terminal is connected to the output terminal of the 3.3 V voltage source operation buffer circuit 203.

The 3.3 V voltage source operating buffer circuit 202 in the clock tree 227 is disposed between the ground wiring 401 and the 3.3 V voltage source wiring 402, and each input terminal of the 3.3 V voltage source operating buffer circuits 203 to 206 is provided. It is connected to the output terminal of the buffer circuit 202. The 3.3 V voltage source operating buffer circuit 201 in the clock tree 227 is disposed between the ground wiring 401 and the 3.3 V voltage source wiring 402, and the input terminals of the 3.3 V voltage source operating buffer circuits 202 and 228 are 3.3. It is connected to the output terminal of the V voltage source operation buffer circuit 201.

The clock input terminal 100 is connected to the input terminal of the 3.3 V voltage source operation buffer circuit 201. The 2.5 V voltage source operation flip-flops 119 to 122 are disposed between the ground wiring 401 and the 2.5 V voltage source wiring 403. The 3.3 V voltage source operating buffer circuit 207 is disposed between the ground wiring 401 and the 3.3 V voltage source wiring 402, and the clock terminals of the 2.5 V voltage source operating flip-flops 119 to 122 have a 3.3 V voltage source operating buffer circuit ( 207) is connected to the output terminal.

The 3.3V voltage source operation buffer circuit 22 is wired between the ground wiring 401 and the 3.3V voltage source wiring 402, and the input terminal of the 3.3V voltage source operating buffer circuits 207 to 210 is connected to the 3.3V voltage source operating buffer circuit. 228 is connected to the output terminal.

Also, although not shown in FIG. 2, the respective output terminals of the 3.3 V voltage source operation buffer circuits 204 to 206 and 208 to 210 are also provided correspondingly to the 3.3 V voltage source operating flip-flop groups 111 to 113 and the 2.5 V voltage source. It is connected to clock terminals of a plurality of flip-flops each of the operation flip-flop groups 124 to 126.

In Fig. 1, for example, a clock signal input to the flip-flop 106, which operates as a 3.3 V voltage source, is operated through a 3.3 V voltage source operation buffer circuit 201 to 203 of a clock tree. The clock terminal of the flip-flop 106 is transferred.

The transfer time at this time is the wiring delay time until input to the 3.3 V voltage source operation buffer circuit 201, the gate delay time of the 3.3 V voltage source operation buffer circuit 201, and the 3.3 V voltage source operation buffer circuit 202. Wiring delay time until input to the circuit, the gate delay time of the 3.3 V voltage source operation buffer circuit 202, the wiring delay time until input to the 3.3 V voltage source operation buffer circuit 203, and 3.3 V voltage source operation The sum of the gate delay time of the buffer circuit 203 and the wiring delay time until input to the 3.3V voltage source operation flip-flop 106 circuit.

The clock signal input to the 2.5 V voltage source operating flip-flop 119 which operates as a 2.5 V voltage source is connected to the 2.5 V voltage source operating flip flop 119 through the 3.3 V voltage source operating buffer circuits 201, 228 and 207 of the clock tree. It is delivered to the clock terminal.

Therefore, the transfer time at this time includes the wiring delay time until input to the 3.3 V voltage source operation buffer circuit 201, the gate delay time of the 3.3 V voltage source operation buffer circuit 201, and the 3.3 V voltage source operation buffer circuit ( 228 wiring delay time until input, the 3.3V voltage source operation buffer circuit 228, the gate delay time, 3.3V voltage source operation buffer circuit 207, the wiring delay time until the input, 3.3V The sum of the gate delay time of the voltage source operation buffer circuit 207 and the wiring delay time until input to the 2.5V voltage source operation flip flop 119.

Here, the clock signal transfer time from the clock input terminal 100 to the clock terminal of the 3.3 V voltage source operating flip-flop 106 and the clock terminal of the clock input terminal 100 to the clock terminal of the 2.5 V voltage source operating flip-flop 119. To equalize the clock signal transfer time, first, the wiring delay time from the clock input terminal 100 to the 3.3 V voltage source operation buffer circuit 202 and the 3.3 V voltage source operation buffer from the clock input terminal 100 are input. The wiring delay time until input to the circuit 228 is made equal.

Subsequently, the gate delay time of the 3.3 V voltage source operation buffer circuit 202 and the gate delay time of the 3.3 V voltage source operation buffer circuit 228 are made equal. Next, the wiring delay time from the 3.3 V voltage source operating buffer circuit 202 to the 3.3 V voltage source operating buffer circuit 203 and the 3.3 V voltage source operating buffer circuit 228 from the 3.3 V voltage source operating buffer circuit 207 The wiring delay time until it is inputted by) is equal.

Subsequently, the gate delay time of the 3.3 V voltage source operation buffer circuit 203 and the gate delay time of the 3.3 V voltage source operation buffer circuit 207 are made equal. Then, the wiring delay time from the 3.3 V voltage source operating buffer circuit 203 to the 3.3 V voltage source operating flip flop 106 and the 2.5 V voltage source operating flip flop 119 from the 3.3 V voltage source operating buffer circuit 207. The wiring delay time until it is inputted by) is equal.

In order to generate the clock tree as described above, the gate lengths and gate widths of the transistors of the buffer circuits of the same layer are equalized, so that the wiring capacitance is equalized even in the wiring of the same layer. As a result, the clock signals supplied to the clock terminals of the flip-flops constituting the flip-flop groups 110 to 113 and 123 to 126 connected to the clock tree 227 have the same timing.

In this embodiment, since the clock tree 227 is constituted by a 3.3 V voltage source circuit, the clock signal having the 3.3 V voltage width is supplied to the 2.5 V voltage source operation flip-flop groups 123 to 126, but the problem is practical. There is no.

To further explain this point, as shown in the transistor model diagram of FIG. 6, the 2.5V voltage source operation flip-flop uses the P-type channel transistor 605 and the N-type channel transistor 606 in which the gates and the drains are connected, respectively. If it is an input terminal, a 3.3 V voltage clock signal is input to the common gate 604 of the transistors 605 and 606. Of these, the 2.5 V voltage source is the voltage source 607 connected to the source 601 of the P-type channel transistor 605.

In general, a load capacitance 608 is attached to the source 601 of the P-type channel transistor 605. When a 3.3 V voltage is applied to the gate 604, the voltage of the voltage of the voltage source 607 at the source 601 position. The dropping takes a short time before the current flows from the source 601 to the drain 602 of the transistors 605 and 606.

When the voltage source 607 is a 2.5V voltage source, when a 3.3V voltage is applied to the gate 604, the voltage drop of the voltage supplied to the source 601 becomes slightly larger than that of the 3.3V voltage source. Therefore, the time from when the 3.3 V voltage is applied to the gate 604 to when the current flows from the source 601 to the drain 602 requires slightly more than when the voltage source 607 is a 3.3 V voltage source. However, this time delay is not a problem in operation as a flip-flop.

In general, when a P-type transistor applies a voltage exceeding a threshold to a gate, current flows from the source side to the drain. In addition, in the N-type transistor, when a voltage exceeding a threshold is applied to the gate, current flows from the drain to the source. In this case, since the voltage 3.3 V applied to the gate 604 of the P-type channel transistor 605 of the flip-flop of the 2.5 V voltage source exceeds the threshold of the P-type channel transistor 605 of the 2.5 V voltage source, the transistor ( The current flows from the source side to the drain of 605, so there is no operational problem as a flip-flop.

Next, an embodiment of a method of configuring an integrated circuit according to the present invention will be described in detail with reference to FIG. 2.

First, a voltage source region 404 for arranging 3.3 V layout cells and 2.5 V layout cells is created. Subsequently, the 3.3V voltage source wiring 402, the 2.5V voltage source wiring 403, and the ground wiring 401 are wired to the 3.3V and 2.5V common voltage source region 404. Subsequently, a 3.3 V layout cell other than the clock tree is placed between the ground wiring 401 and the 3.3 V voltage source wiring 402 in the 3.3 V and 2.5 V common voltage source region 404, and the 2.5 V layout cell is grounded. Disposed between the 401 and the 2.5 V voltage source wiring 403.

Subsequently, the clock trees of the voltage source region 404 common to 3.3 V and 2.5 V are arranged and wired. In this case, since the flip-flops connected to the 3.3 V voltage source operation buffer circuits 203 to 206 have the same configuration, the flip-flops connected to the 3.3 V voltage source operation buffer circuits 207 to 210 also have the same configuration, and thus the 3.3 V voltage source is described below. The operation buffer circuits 203 and 207 are representatively described.

The third stage 3.3V voltage source operating buffer circuit 203 is disposed between the ground wiring 401 and the 3.3V voltage source wiring 402 near the 3.3V voltage source operating flip-flops 106 to 109, and the 3.3V voltage source operating buffer circuit The output terminal of 203 is connected by bypass wiring in some cases so that the wiring capacitance becomes equal to the clock terminals of the 3.3V voltage source operation flip-flops 106 to 109.

Subsequently, a second stage 3.3V voltage source operation buffer circuit 202 is disposed between the ground wiring 401 and the 3.3V voltage source wiring 402. Subsequently, in some cases, the output terminal of the 3.3 V voltage source operation buffer circuit 202 is connected to the input terminal of the third stage 3.3 V voltage source operation buffer circuit 203 to 206 so that the wiring capacitance is equal, and in some cases, bypassed. .

Further, the third stage 3.3V voltage source operation buffer circuit 207 is disposed between the 3.3V voltage source wiring 402 and the ground wiring 401 at the center position of the 2.5V voltage source operating flip-flops 119 to 122, and the 3.3 In some cases, the output terminal of the V voltage source operation buffer circuit 207 is connected to the clock terminals of the 2.5 V voltage source operation flip-flops 119 to 122 by bypass wiring in order to make the wiring capacitance equal.

Subsequently, a second stage 3.3V voltage source operation buffer circuit 228 is disposed between the ground wiring 401 and the 3.3V voltage source wiring 402 located at the center of the 3.3V voltage source operating buffer circuits 207 to 210. FIG. Subsequently, the output terminal of the 3.3 V voltage source operating buffer circuit 228 is bypassed in some cases so as to be equal to the input terminal of the 3.3 V voltage source operating buffer circuits 207 to 210 so as to be connected by aluminum wiring. do.

Subsequently, the first stage 3.3 V voltage source operation buffer circuit 201 is disposed between the ground wiring 401 and the 3.3 V voltage source wiring 402. Next, the output terminal of the 3.3 V voltage source operation buffer circuit 201 and the input terminal of the 3.3 V voltage source operation buffer circuits 202 and 228 are connected so that the wiring capacitance becomes equal.

The above is the arrangement and wiring method (configuration method of the integrated circuit) of the clock tree in the voltage source region 404 common to 3.3V and 2.5V. Finally, the output of the clock input terminal 100 is connected to the input terminal of the 3.3 V voltage source operation buffer circuit 201.

Next, 2nd Embodiment of this invention is described with reference to drawings.

In Fig. 1, the 3.3 V voltage source operating flip flops 106 to 109 connected to the 3.3 V voltage source operating buffer circuit 203 are flip flops that operate from the 3.3 V voltage source. Further, the 2.5 V voltage source operating flip flops 119 to 122 connected to the 3.3 V voltage source operating buffer circuit 207 are flip flops that operate from the 2.5 V voltage source. Thus, the flip-flop groups connected to the output of the 3rd-stage buffer of a clock tree are gathered by the flip-flops which operate with the same voltage source in embodiment of FIG.

In the second embodiment of the present invention, the unit for collecting the flip-flops is collected not close to the voltage source, but in the region where the arrangement area is close. For example, in Fig. 2, the 3.3 V voltage source operating flip flops 107 and 109 and the 2.5 V voltage source operating flip flops 119 and 121 are combined, and the clock terminals of these flip flops are connected to the output terminal of the 3.3 V voltage source operating buffer circuit 203. do. As a result, the wiring length between the buffer circuits of the clock tree is shortened, making it easy to adjust the delay time when generating the clock tree.

In the conventional example, the clock tree of the functional block of the 2.5 V voltage source operation uses the buffer circuit of the 2.5 V voltage source operation, whereas the buffer circuit of the 3.3 V voltage source operation is used in the present invention. Therefore, the power consumption increases slightly compared with the conventional example, but the increase in power consumption is small because only the buffer circuit of the clock tree is used.

As described above, according to the present invention, the clock signal is supplied to the storage means of the different voltage sources through a plurality of buffer circuits operating in the same voltage source in common, so that even if the diffusion condition and the temperature condition change, The transfer time varies, but because the wiring capacity is the same, the transfer times output from the buffer circuits of the plurality of final stages become equal to each other, and therefore the clocks supplied to the plurality of storage means connected to the buffer circuits of the plurality of final stages. Since the phases of the signals can be made equal, data transfer can be performed between clocks of storage means having different voltage sources.

In addition, according to the present invention, since the configuration does not include a delay circuit for adjusting the transfer time of the integrated circuit, the design period of the layout design can be shortened as compared with the prior art.

Claims (3)

A clock signal supply integrated circuit for distributing and supplying a clock signal through a plurality of stage buffer circuits connected in a tree shape to a plurality of storage means using different voltage sources, The plurality of stage buffer circuits connected in the tree shape are operated as the highest voltage source among the different voltage sources, and the clock signals are transmitted at the same delay time. And a clock signal from a buffer circuit to a plurality of storage means using the different voltage sources, respectively. 2. The memory device of claim 1, wherein the plurality of storage means are flip-flops, and the buffer circuit of the last stage is composed of a plurality of buffer circuits arranged in parallel, and each of the plurality of buffer circuits is configured to provide the clock signal with a plurality of flip-flops. An integrated circuit for supplying a clock signal, characterized in that for supplying. A plurality of different voltage source wiring and ground wirings are wired in one arrangement area, and a plurality of storage means using different voltage sources are arranged between the voltage source voltage wiring and ground wiring for voltage storage used by the storage means, respectively. Is arranged in the arrangement area and between the highest voltage source voltage source wiring and the ground wiring among the different voltage sources and connected in a tree shape, and the input terminal of the buffer circuit of the first stage of the plurality of buffer circuits is connected. And a clock signal input terminal, and an output terminal of the buffer circuit of the last stage of the buffer circuits of the plurality of stages is connected to clock terminals of the plurality of storage means, respectively.