KR100408001B1 - Method for forming gate isolation film of semiconductor - Google Patents
Method for forming gate isolation film of semiconductor Download PDFInfo
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- KR100408001B1 KR100408001B1 KR10-2001-0087212A KR20010087212A KR100408001B1 KR 100408001 B1 KR100408001 B1 KR 100408001B1 KR 20010087212 A KR20010087212 A KR 20010087212A KR 100408001 B1 KR100408001 B1 KR 100408001B1
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000002955 isolation Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 2
- 229910004140 HfO Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000007789 gas Substances 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 62
- 230000009977 dual effect Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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- Condensed Matter Physics & Semiconductors (AREA)
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- Chemical & Material Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 기판 조건에 따라 막 성장 두께가 달라지는 것을 이용하여 기판을 질소 또는 산소를 함유한 가스 분위기에서 열처리한후 고유전막을 증착하여 누설 전류를 억제할 수 있도록한 반도체 소자의 게이트 절연막 형성 방법에 관한 것으로, 제 1 영역과 제 2 영역을 갖는 반도체 기판상에 유전막을 형성하는 단계;상기 제 1 영역의 상기 유전막을 제거하는 단계;상기 제 2 영역의 유전막에 의해 성장 속도가 차이나는 것을 이용하여 전면에 상기 유전막보다 유전율이 높은 물질을 증착하여 제 1 영역에 제 1 두께의 게이트 절연막을, 제 2 영역에 제 1 두께보다 작은 제 2 두께의 게이트 절연막을 동시에 형성하는 단계를 포함한다.The present invention relates to a method for forming a gate insulating film of a semiconductor device in which a substrate is heat-treated in a gas atmosphere containing nitrogen or oxygen by using a film growth thickness that varies according to substrate conditions, and then a high dielectric film is deposited to suppress leakage current. A method of manufacturing a dielectric film, the method comprising: forming a dielectric film on a semiconductor substrate having a first region and a second region; removing the dielectric layer of the first region; using a growth rate different by the dielectric layer of the second region; Depositing a material having a higher dielectric constant than the dielectric film on the entire surface, and simultaneously forming a gate insulating film having a first thickness in the first region and a gate insulating film having a second thickness smaller than the first thickness in the second region.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 기판 조건에 따라 막 성장 두께가 달라지는 것을 이용하여 기판을 질소 또는 산소를 함유한 가스 분위기에서 열처리한후 고유전막을 증착하여 누설 전류를 억제할 수 있도록한 반도체 소자의 게이트 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of semiconductor devices, wherein a substrate is heat-treated in a gas atmosphere containing nitrogen or oxygen by using a film growth thickness that varies according to substrate conditions, thereby depositing a high dielectric film to suppress leakage current. A method of forming a gate insulating film of a semiconductor device.
반도체 장치 제조 공정에 있어서, 절연막의 용도는 외부의 불순물 침입을 방지하는 표면 보호막(Surface Passivation) 역할과 이온주입 마스크 역할 또는, 실리콘 기판의 절연막으로서의 역할로 구분할 수 있다.In the semiconductor device manufacturing process, the use of the insulating film can be divided into the role of the surface passivation (i.e., surface implantation) and the ion implantation mask or the role of the insulating film of the silicon substrate.
특히, 절연막의 역할은 반도체 제조 수율에 상당한 영향을 미치며, 현재까지도 이에 대한 많은 연구가 계속되고 있다.In particular, the role of the insulating film has a significant effect on the semiconductor manufacturing yield, and many studies on this continue.
실리콘 기판 상에 소오스/드레인(Source/Drain)간의 전기적 전도 채널(Channel)을 형성하며 전하를 유지하려 할 때 사용되는 게이트 절연막은 초고속 동작을 수행하기 위한 최소한의 두께로 형성하여 소자의 고집적화를 극대화 하는 것이 당면 과제이다.The gate insulating film, which is used to maintain electric charge and forms an electric conduction channel between source / drain on a silicon substrate, is formed to a minimum thickness to perform ultra-fast operation to maximize device integration. Doing that is a challenge.
이하에서 종래 기술의 게이트 절연막에 관하여 설명한다.Hereinafter, a gate insulating film of the prior art will be described.
종래 기술에서는 게이트 절연막을 퍼니스(furnace)에서 습식 분위기에서 성장시킨 열산화막(Thermal Oxide)을 사용한다.In the prior art, a thermal oxide film in which a gate insulating film is grown in a wet atmosphere in a furnace is used.
그리고 한 웨이퍼내에서 서로 다른 두께를 갖는 듀얼 게이트 산화막을 형성하기 위하여 두껍게 형성할 부분을 마스킹한후에 얇은 막을 성장시킬 부분만 N2이온 주입한다.Then, in order to form dual gate oxide films having different thicknesses in one wafer, after masking portions to be thickly formed, only N 2 ions are implanted to grow thin films.
그리고 마스크를 제거한후에 열산화 공정을 진헹하면 N2이온 주입된 영역은 N2이온이 주입되지 않은 영역에 비해 성장 속도가 현저히 느려 한 웨이퍼내에 서로 다른 게이트 절연막을 형성할 수 있다.And if jinheng the thermal oxidation process after removing the mask 2 N ion-implanted regions can be formed in another gate insulating film to each other in a wafer, the growth rate significantly slower than the area N 2 ions have not been implanted.
이러한 공정으로 형성된 게이트 산화막은 질소 이온 주입시에 발생된 기판 손상에 의해 얇은 게이트 산화막의 신뢰성이 떨어지는 문제가 있다.The gate oxide film formed by such a process has a problem that the reliability of the thin gate oxide film is deteriorated due to substrate damage generated during nitrogen ion implantation.
이를 해결하기 위한 다른 방법으로 다음과 같은 방법을 사용한다.To solve this problem, use the following method.
열산화 공정을 먼저 진행하여 전면에 두꺼운 게이트 산화막(thick gate oxide)을 형성한 후에 전면에 포토레지스트를 도포하고 얇은 게이트 산화막을 형성할 부분만 오픈되도록 패터닝한다.The thermal oxidation process is first performed to form a thick gate oxide on the front surface, and then a photoresist is applied on the front surface and patterned to open only a portion to form a thin gate oxide film.
그리고 습식 식각 공정을 진행하여 얇은 게이트 산화막 형성 부분의 두꺼운 게이트 산화막을 제거하고 다시 얇은 게이트 산화막을 형성하는 방법이 있다.There is a method of performing a wet etching process to remove the thick gate oxide film of the thin gate oxide film forming portion and to form the thin gate oxide film again.
이때 두꺼운 게이트 산화막 부분이 약간 더 두꺼워지는데, 이는 얇은 게이트 산화막의 전세(precleaning) 공정시에 시간을 적정하게 조정하면 최종적으로 두꺼운 게이트 산화막의 두께를 만들 수 있다.At this time, the thick gate oxide portion becomes slightly thicker, which can be finally made by properly adjusting the time during the precleaning process of the thin gate oxide layer.
소자의 선폭이 점점 축소되면서 게이트 산화막의 두께도 낮아져 현재, 0.13㎛ 로직 기술의 경우 물리적 두께가 20Å 정도인 게이트 산화막을 사용하고 있다.As the line width of the device is gradually reduced, the thickness of the gate oxide is also lowered. Currently, a 0.13 μm logic technology uses a gate oxide having a physical thickness of about 20 μs.
그 이하의 sub-0.1㎛에서는 약 16Å 정도의 두께를 필요로 하는데 이 경우 두께가 작아 직접 터널링에 의한 급격한 누설 전류가 발생하여 게이트 유전막으로의 기능을 유지하지 못한다.Sub-0.1 μm or less requires a thickness of about 16 mA. In this case, the thickness is so small that a rapid leakage current due to direct tunneling occurs and thus it cannot maintain its function as a gate dielectric film.
이 문제를 해결하기 위하여 유전 상수가 7 이상의 고유전 물질을 사용하는 방법이 제시되고 있다.In order to solve this problem, a method of using a dielectric material having a dielectric constant of 7 or more has been proposed.
그러나 이와 같은 종래 기술의 반도체 소자의 게이트 절연막 및 그 제조 공정은 다음과 같은 문제점이 있다.However, such a gate insulating film and a manufacturing process of the semiconductor device of the prior art has the following problems.
종래 기술에서는 소자의 고지적화에 따라 형성 공정 및 요구되는 특성이 더 엄격해지고 있음에도 이를 충족시킬 수 있는 게이트 산화막 제조 공정이 제시되지 못하고 있다.In the prior art, although the formation process and the required characteristics are becoming more stringent according to the high-density of the device, a gate oxide film manufacturing process that can satisfy this has not been proposed.
특히 고유전막을 사용하여 듀얼 게이트 산화막을 형성하는 경우에는 두 번의 증착 공정을 진행하여야 한다.In particular, when a dual gate oxide film is formed using a high dielectric film, two deposition processes must be performed.
두 번의 증착 공정으로 듀얼 게이트 산화막을 형성하는 경우에는 반복 증착에 따른 공정의 복잡성 이외에 첫 번째 증착한 고유전막과 두 번째 증착한 고유전막 사이에 이물(particle)이 존재할 확률이 높고 표면 거칠기가 좋지 않다.In the case of forming a dual gate oxide film by two deposition processes, in addition to the complexity of the repeated deposition process, there is a high possibility that particles exist between the first high dielectric film and the second high dielectric film, and the surface roughness is poor. .
본 발명은 이와 같은 종래 기술의 게이트 절연막 및 그의 형성 공정의 문제를 해결하기 위한 것으로, 기판 조건에 따라 막 성장 두께가 달라지는 것을 이용하여 기판을 질소 또는 산소를 함유한 가스 분위기에서 열처리한후 고유전막을 증착하여 누설 전류를 억제할 수 있도록한 반도체 소자의 게이트 절연막 형성 방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art gate insulating film and its formation process, the high-k dielectric film after heat-treating the substrate in a gas atmosphere containing nitrogen or oxygen using a film growth thickness that varies depending on the substrate conditions It is an object of the present invention to provide a method for forming a gate insulating film of a semiconductor device capable of suppressing the leakage current by depositing the same.
도 1a내지 도 1d는 본 발명에 따른 듀얼 게이트 절연막 형성을 위한 공정 단면도1A to 1D are cross-sectional views of a process for forming a dual gate insulating film according to the present invention.
도 2a내지 도 2d는 열처리 분위기에 따른 Ta2O5박막의 증착 상태를 보여주는 TEM 사진2a to 2d are TEM photographs showing the deposition state of the Ta 2 O 5 thin film according to the heat treatment atmosphere
도 3a와 도 3b는 본 발명에 따른 게이트 절연막의 XRD 패턴 및 I-V 특성 그래프3A and 3B are graphs of XRD patterns and I-V characteristics of the gate insulating film according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11. 반도체 기판 12. 소자 격리층11. Semiconductor substrate 12. Device isolation layer
13. 유전막 14. 포토레지스트 패턴13. Dielectric Film 14. Photoresist Pattern
15a. 제 1 게이트 유전막 15b. 제 2 게이트 유전막15a. First gate dielectric layer 15b. Second gate dielectric layer
16. 게이트 전극 형성용 물질층16. Material layer for forming gate electrode
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 게이트 절연막 형성 방법은 제 1 영역과 제 2 영역을 갖는 반도체 기판상에 유전막을 형성하는 단계;상기 제 1 영역의 상기 유전막을 제거하는 단계;상기 제 2 영역의 유전막에 의해 성장 속도가 차이나는 것을 이용하여 전면에 상기 유전막보다 유전율이 높은 물질을 증착하여 제 1 영역에 제 1 두께의 게이트 절연막을, 제 2 영역에 제 1 두께보다 작은 제 2 두께의 게이트 절연막을 동시에 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a gate insulating film of a semiconductor device, the method including: forming a dielectric film on a semiconductor substrate having a first region and a second region; removing the dielectric layer in the first region; By depositing a material having a higher dielectric constant than the dielectric film on the entire surface by using a difference in growth rate by the dielectric film of the second region, a gate insulating film having a first thickness in the first region and a material smaller than the first thickness in the second region are deposited. And simultaneously forming a gate insulating film of two thicknesses.
이하, 첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 게이트 절연막 형성 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a gate insulating film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a내지 도 1d는 본 발명에 따른 듀얼 게이트 절연막 형성을 위한 공정 단면도이다.1A to 1D are cross-sectional views of a process for forming a dual gate insulating film according to the present invention.
그리고 도 2a내지 도 2d는 열처리 분위기에 따른 Ta2O5박막의 증착 상태를 보여주는 TEM 사진이고, 도 3a와 도 3b는 본 발명에 따른 게이트 절연막의 XRD 패턴 및 I-V 특성 그래프이다.2A to 2D are TEM photographs showing deposition states of Ta 2 O 5 thin films according to a heat treatment atmosphere, and FIGS. 3A and 3B are XRD patterns and IV characteristics graphs of a gate insulating film according to the present invention.
본 발명은 기판을 RTP(Rapid Thermal Process) 방식으로 O2,NO,N2O,NH3등의 하나를 사용하여 전처리 한 후에 LPCVD(Low Pressure Chemical Vapor Deposition) 공정으로 고유전막 Si3N4또는 Ta2O5등을 증착하여 게이트 절연막을 형성하는 것이다.The present invention is a substrate in a RTP (Rapid Thermal Process) method O 2, NO, N 2 O , NH 3 after such pre-treatment using one of a LPCVD (Low Pressure Chemical Vapor Deposition) process specific conductive film Si 3 N 4 or Ta 2 O 5 or the like is deposited to form a gate insulating film.
공정 진행은 먼저, 도 1a에서와 같이, 소자 격리층(12)을 갖고 제 1 두께의 게이트 절연막 형성 영역과 제 1 두께보다 작은 제 2 두께를 갖는 게이트 절연막형성 영역을 갖는 반도체 기판(11)상에 RTP(Rapid Thermal Process) 방식으로 O2,NO,N2O,NH3의 어느 하나를 사용하여 15 ~ 20Å의 두께로 얇은 유전막(13)을 형성한다.The process proceeds first, as shown in FIG. 1A, on the semiconductor substrate 11 having the device isolation layer 12 and the gate insulating film forming region having the first thickness and the gate insulating film forming region having the second thickness smaller than the first thickness. To form a thin dielectric film 13 to a thickness of 15 ~ 20Å by using any one of O 2 , NO, N 2 O, NH 3 in a rapid thermal process (RTP) method.
상기 유전막(13)은 질화 산화막(SiON) 또는 순수한 산화막(SiO2), 질화막(Si3N4)의 어느 하나의 조성을 갖는다.The dielectric layer 13 may have any one of a nitride oxide layer (SiON), a pure oxide layer (SiO 2 ), and a nitride layer (Si 3 N 4 ).
그리고 도 1b에서와 같이, 상기 유전막(13)상에 포토레지스트를 도포하고 선택적으로 패터닝하여 제 1 두께의 게이트 절연막 형성 영역이 오픈되는 포토레지스트 패턴(14)을 형성한다.As shown in FIG. 1B, a photoresist is applied and selectively patterned on the dielectric layer 13 to form a photoresist pattern 14 in which a gate insulating layer formation region having a first thickness is opened.
이어, 상기 포토레지스트 패턴(14)을 마스크로 하여 노출된 유전막(13)을 습식 식각 공정으로 제거한다.Subsequently, the exposed dielectric layer 13 is removed by a wet etching process using the photoresist pattern 14 as a mask.
그리고 도 1c에서와 같이, 상기 포토레지스트 패턴을 제거한후 LPCVD 공정으로 전면에 유전 상수가 큰 Ta2O5,Si3N4,Al2O3,TiO2,HfO2,ZrO2의 어느 하나의 고유전막을 증착한다.As shown in FIG. 1C, after removing the photoresist pattern, any one of Ta 2 O 5 , Si 3 N 4 , Al 2 O 3 , TiO 2 , HfO 2 , ZrO 2 having a large dielectric constant on the front surface is removed by the LPCVD process. A high dielectric film is deposited.
이때, 제 2 두께를 갖는 게이트 절연막 형성 영역에서는 유전막(13)에 의해 성장 속도가 느려 얇은 두께의 유전막이 형성되고, 제 1 두께의 게이트 절연막 형성 영역에서는 두꺼운 유전막이 형성된다.At this time, in the gate insulating film forming region having the second thickness, the growth rate is slowed by the dielectric film 13 to form a thin dielectric film, and a thick dielectric film is formed in the gate insulating film forming region of the first thickness.
이와 같은 공정으로 서로 두께가 다른 제 1 게이트 유전막(15a)과 제 2 게이트 유전막(15b)이 형성된다.In this process, the first gate dielectric layer 15a and the second gate dielectric layer 15b having different thicknesses are formed.
이어, 도 1d에서와 같이, 후속 공정으로 게이트 전극 형성용 물질층(16)을형성하여 트랜지스터 형성 공정을 진행한다.Subsequently, as shown in FIG. 1D, the transistor forming process is performed by forming the gate electrode forming material layer 16 in a subsequent process.
도 2a내지 도 2d는 각각 O2,NO,N2O,NH3의 가스를 사용한 열처리후에 Ta2O5의 고유전막을 형성한후의 TEM 사진으로 각각 서로 다른 두께의 유전막이 형성된 것을 알 수 있다.2A to 2D are TEM photographs of Ta 2 O 5 after forming a high dielectric film of Ta 2 O 5 after heat treatment using gases of O 2 , NO, N 2 O, and NH 3 , respectively. .
또한, 열처리의 조건을 달리하여 두께가 다른 Ta2O5의 고유전막의 전류 특성이 서로 다르게 나타나는 것을 알 수 있다.In addition, it can be seen that the current characteristics of the high-k dielectric film of Ta 2 O 5 having different thickness are different from each other by different heat treatment conditions.
이와 같은 본 발명에 따른 게이트 절연막 형성 공정은 한번의 LPCVD 공정으로 서로 다른 두께를 갖는 게이트 절연막을 형성할 수 있고, 게이트 산화막 자체의 물리적 두께를 증가시킬 수 있다.The gate insulating film forming process according to the present invention can form a gate insulating film having a different thickness in one LPCVD process, it is possible to increase the physical thickness of the gate oxide film itself.
이와 같은 본 발명에 따른 반도체 소자의 게이트 절연막 형성 방법은 다음과 같은 효과가 있다.Such a method for forming a gate insulating film of a semiconductor device according to the present invention has the following effects.
첫째, 듀얼 게이트 절연막 형성시에 한번의 LPCVD 공정을 사용하여 공정이 단순하다.First, the process is simple by using one LPCVD process when forming the dual gate insulating film.
둘째, 반복적인 증착 공정을 사용하지 않으므로 유전막간의 이물 잔류 문제를 해결할 수 있다.Second, since the repetitive deposition process is not used, the problem of foreign material remaining between dielectric films can be solved.
셋째, 게이트 절연막의 물리적 두께를 증가시켜 직접 터널링에 의한 누설 전류의 급격한 증가를 막고, 표면 거칠기를 좋게 하여 소자의 신뢰성을 높일 수 있다.Third, by increasing the physical thickness of the gate insulating film to prevent a sudden increase in leakage current by direct tunneling, and improve the surface roughness can improve the reliability of the device.
넷째, PMOS 트랜지스터에서의 보론 침투 현상을 억제할 수 있다.Fourth, boron penetration in the PMOS transistor can be suppressed.
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