KR100373341B1 - Method for forming capacitor having metal bottom electrode - Google Patents
Method for forming capacitor having metal bottom electrode Download PDFInfo
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- KR100373341B1 KR100373341B1 KR10-1999-0018799A KR19990018799A KR100373341B1 KR 100373341 B1 KR100373341 B1 KR 100373341B1 KR 19990018799 A KR19990018799 A KR 19990018799A KR 100373341 B1 KR100373341 B1 KR 100373341B1
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- 239000003990 capacitor Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 title abstract description 11
- 239000002184 metal Substances 0.000 title abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 230000008569 process Effects 0.000 claims abstract description 9
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 239000002994 raw material Substances 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 239000012159 carrier gas Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 5
- 239000012495 reaction gas Substances 0.000 claims description 4
- 239000007800 oxidant agent Substances 0.000 claims description 3
- 125000002524 organometallic group Chemical group 0.000 claims 2
- 238000005406 washing Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 73
- 239000007769 metal material Substances 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002715 modification method Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
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Abstract
본 발명은 유효 산화막 두께를 감소시킬 수 있으며 캐패시터의 누설전류를 감소시킬 수 있는 캐패시터 제조 방법에 관한 것으로, 금속 물질로 캐패시터의 하부전극을 형성하고, 상기 하부전극 표면의 산화막을 제거하기 위한 세정 공정을 실시하고, 상기 하부전극 상에 유전막 및 상부전극을 형성하는 캐패시터 제조 방법을 제공한다. 본 발명은 MIM 구조의 캐패시터 제조 공정 중 (BaxSr1-x)TiO3(BST) 또는 Ta2O5박막을 증착하기에 앞서 금속 하부전극을 세정함으로써 표면에 존재하는 산화막을 제거하여, 유효산화막 두께의 증가를 억제하고 금속 하부전극의 산화를 방지하여 캐패시터의 누설전류 특성의 열화를 방지할 수 있는 방법이다.The present invention relates to a method for manufacturing a capacitor that can reduce the effective oxide film thickness and reduce the leakage current of the capacitor. The present invention relates to a cleaning process for forming a lower electrode of a capacitor from a metal material and removing an oxide film on the surface of the lower electrode. The present invention provides a capacitor manufacturing method for forming a dielectric film and an upper electrode on the lower electrode. The present invention is effective by removing the oxide film present on the surface by cleaning the metal lower electrode prior to depositing a (Ba x Sr 1-x ) TiO 3 (BST) or Ta 2 O 5 thin film during the capacitor manufacturing process of the MIM structure. It is a method of preventing the deterioration of the leakage current characteristics of the capacitor by suppressing an increase in the oxide film thickness and preventing oxidation of the metal lower electrode.
Description
본 발명은 반도체 메모리 소자 제조 분야에 관한 것으로, 특히 금속 하부전극을 갖는 캐패시터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method of manufacturing a capacitor having a metal lower electrode.
현재 반도체 메모리소자는 크게 리드/라이트(read/write) 메모리와 리드전용 메모리(ROM)로 구분할 수 있다. 특히 리드/라이트 메모리는 다이나믹램(Dynamic RAM, 이하 DRAM이라 칭함)과 스태틱램(static RAM)으로 나뉘어진다. DRAM의 단위 셀(unit cell)은 1개의 트랜지스터(transistor)와 1개의 캐패시터로 구성되어 집적도에서 가장 앞서고 있다. 반도체 메모리 소자의 고집적화가 급진전됨에 따라 3년마다 메모리의 용량이 4배씩 증가되어 현재에는 256Mb(mega bit) DRAM 및 1Gb(giga bit)에 대한 연구에 많은 진전을 보이고 있다. 이와 같이 DRAM의 집적도가 높아질수록 전기 신호를 읽고 기록하는 역할을 하는 셀의 면적은 점점 감소하고 있다. 예를 들어, 256Mb의 DRAM의 경우 셀 면적은 0.5 ㎛2이며, 이 경우 셀의 기본 구성요소 중의 하나인 캐패시터의 면적은 0.3㎛2이하로 작아져야 한다.Currently, semiconductor memory devices can be classified into read / write memory and read-only memory (ROM). In particular, the read / write memory is divided into a dynamic RAM (hereinafter referred to as DRAM) and a static RAM. The unit cell of a DRAM consists of one transistor and one capacitor, leading the integration. With the rapid integration of semiconductor memory devices, memory capacity has increased by four times every three years, and now, much progress has been made in research on 256Mb (mega bit) DRAM and 1Gb (giga bit). As the density of DRAM increases, the area of a cell that reads and writes an electrical signal decreases. For example, for a 256 Mb DRAM, the cell area is 0.5 μm 2 , in which case the area of the capacitor, which is one of the basic components of the cell, should be reduced to 0.3 μm 2 or less.
이와 같은 반도체 메모리 소자의 집적도 향상에 따라 작은 면적에 높은 캐패시턴스를 확보하기 위해서 높은 유전상수를 갖는 유전막으로 캐패시터를 형성하거나 유전막을 얇게 형성하거나 또는 캐패시터의 단면적을 증가시키는 방법이 제시되고 있다. 캐패시터의 단면적(전하저장전극의 표면적)을 증가시키기 위해서, 스택형 캐패시터 또는 트렌치형 캐패시터를 형성하는 기술 또는 반구형 폴리실리콘막을 사용하는 기술 등 여러 가지 기술이 제안된바 있으나, 이러한 기술들은 캐패시터의 구조를 복잡하게 만들며 공정이 너무 복잡하여 제조 단가의 상승과 수율을 저하시키는 등의 문제점이 있다.In order to secure a high capacitance in a small area, a method of forming a capacitor with a dielectric film having a high dielectric constant, forming a thin dielectric film, or increasing the cross-sectional area of a capacitor is proposed. In order to increase the cross-sectional area of the capacitor (surface area of the charge storage electrode), various techniques have been proposed, such as a technique for forming a stacked capacitor or a trench capacitor, or a technique using a hemispherical polysilicon film. To make the complex and the process is too complicated, there is a problem such as an increase in manufacturing cost and lowering the yield.
캐패시터의 유전막으로는 보통 SiO2/Si3N4계 유전물질을 사용하는데SiO2/Si3N4계 유전막의 두께를 감소시켜 캐패시턴스를 증가시키는 방법은 기술상 한계가 있다. 따라서, SiO2/Si3N4계 보다 유전율이 높은 Ta2O5, (BaxSr1-x)TiO3등의 고유전 물질을 이용한 캐패시터 제조 방법이 제시되고 있다.As the dielectric film of the capacitor, SiO 2 / Si 3 N 4 based dielectric materials are usually used. However, there is a technical limitation in the method of increasing capacitance by reducing the thickness of the SiO 2 / Si 3 N 4 based dielectric film. Accordingly, a method of manufacturing a capacitor using a high dielectric material such as Ta 2 O 5 and (Ba x Sr 1-x ) TiO 3 having a higher dielectric constant than that of a SiO 2 / Si 3 N 4 system has been proposed.
반도체 메모리 소자의 제조 공정 중 Ta2O5와 같은 고유전율의 물질을 이용한 캐패시터 제조에 있어 소자의 집적화에 따라 유전막의 유효산화막 두께(Tox) 감소 및 누설전류 특성의 개선이 요구되고 있다. Ta2O5를 포함한 캐패시터 제조 공정시, 하부전극 물질로 폴리실리콘을 사용하는 경우 유전막의 유효산화막 두께(Tox)를 30Å 이하로 감소시키는 것이 곤란하다. 이에 따라 폴리실리콘과의 전기적 에너지 장벽(일함수)이 커서 유효산화막 두께를 감소시킬 수 있으며 동일한 유효산화막 두께에서의 누설전류를 감소시킬 수 있는 금속 물질을 이용하여 하부전극을 형성한다. 이와 같이 금속 물질로 하부전극을 형성하는 방법은 바이어스 전압(bias voltage)에 따른 캐패시턴스의 변화량(ΔC) 값이 작은 장점도 갖는다.In the manufacture of a capacitor using a high dielectric constant material such as Ta 2 O 5 during the manufacturing process of a semiconductor memory device, it is required to reduce the effective oxide thickness (T ox ) of the dielectric film and to improve leakage current characteristics as the device is integrated. In the process of manufacturing a capacitor including Ta 2 O 5 , when polysilicon is used as the lower electrode material, it is difficult to reduce the effective oxide thickness (T ox ) of the dielectric film to 30 kPa or less. Accordingly, the electrical energy barrier (work function) with the polysilicon is large, so that the effective oxide film thickness can be reduced, and the lower electrode is formed using a metal material that can reduce the leakage current at the same effective oxide film thickness. As such, the method of forming the lower electrode from the metal material also has an advantage of having a small change amount of capacitance ΔC according to a bias voltage.
한편, 금속 물질을 상, 하부전극으로 이용한 MIM(metal-insulator-metal) 구조의 캐패시터 제조 공정에서 금속 전극 물질의 표면에 산화막이 존재하게 되면 유전막 증착 및 열처리 공정 후에 유전막과 하부전극 물질 사이의 층간산화막에 의해 유효 산화막 두께 값이 증가하게 된다. 또한, 동일한 열처리 온도에서도 산화막의 산소 확산에 의해 하부전극의 산화가 발생하여 누설전류 특성이 열화된다.On the other hand, if an oxide film is present on the surface of the metal electrode material in the MIM (metal-insulator-metal) capacitor manufacturing process using a metal material as the upper and lower electrodes, the interlayer between the dielectric film and the lower electrode material after the dielectric film deposition and heat treatment process The oxide film increases the effective oxide film thickness value. In addition, even at the same heat treatment temperature, oxidation of the lower electrode occurs due to oxygen diffusion of the oxide film, and the leakage current characteristic is deteriorated.
따라서, 하부전극의 물성 및 두께 등에 영향을 주지않고 하부전극 표면의 산화막만을 제거하는 표면 개질 방법이 요구된다.Accordingly, there is a need for a surface modification method for removing only the oxide film on the surface of the lower electrode without affecting the physical properties and thickness of the lower electrode.
상기 문제점을 해결하기 위하여 안출된 본 발명은 유효 산화막 두께를 감소시킬 수 있으며 캐패시터의 누설전류를 감소시킬 수 있는 캐패시터 제조 방법 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a capacitor manufacturing method that can reduce the effective oxide film thickness and can reduce the leakage current of the capacitor.
도1a 내지 도1d는 본 발명의 일실시예에 따른 캐패시터 제조 공정 단면도,1A to 1D are cross-sectional views of a capacitor manufacturing process according to an embodiment of the present invention;
도2는 종래 기술과 본 발명에 따라 형성된 캐패시터의 누설전류 특성을 보이는 그래프.2 is a graph showing leakage current characteristics of a capacitor formed according to the prior art and the present invention.
* 도면의 주요부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
1: 폴리실리콘막 2: 제1 TiN막1: polysilicon film 2: first TiN film
3: W막 4: Ta2O5막3: W film 4: Ta 2 O 5 film
5: 제2 TiN막 6: 폴리실리콘막5: second TiN film 6: polysilicon film
상기 목적을 달성하기 위한 본 발명은 텅스텐으로 캐패시터의 하부전극을 형성하는 제1 단계; 완충산화삭각제를 이용하여 상기 텅스텐 하부전극 표면의 산화막을 제거하기 위한 세정 공정을 실시하는 제2 단계; 상기 텅스텐 하부전극 상에 유전막을 형성하는 제3 단계; 및 상기 유전막 상에 상부전극을 형성하는 제4 단계를 포함하는 캐패시터 제조 방법을 제공한다.The present invention for achieving the above object is a first step of forming a lower electrode of the capacitor from tungsten; A second step of performing a cleaning process for removing an oxide film on the surface of the tungsten lower electrode using a buffered oxidizing agent; Forming a dielectric film on the tungsten lower electrode; And a fourth step of forming an upper electrode on the dielectric layer.
금속 물질을 상, 하부전극으로 이용한 MIM(metal-insulator-metal) 구조의 캐패시터 형성시 유전막 증착 후의 열공정에 의한 하부전극 물질의 산화 방지 및 캐패시터의 유효산화막 두께, 누설전류 특성을 개선하여 신뢰성 있는 소자를 제조하기 위해서는 양질의 캐패시터 유전막을 증착하는 방법과 함께 유전막 하부층(under layer)의 처리 방법도 매우 중요하다.When forming a metal-insulator-metal (MIM) capacitor using a metal material as the upper and lower electrodes, it is possible to reliably prevent the oxidation of the lower electrode material by the thermal process after the deposition of the dielectric film, and to improve the effective oxide film thickness and leakage current characteristics of the capacitor. In order to manufacture a device, a method of depositing a high quality capacitor dielectric film and a method of treating an underlayer of a dielectric film are also very important.
본 발명은 MIM 구조의 캐패시터 제조 공정 중 (BaxSr1-x)TiO3(BST) 또는 Ta2O5박막을 증착하기에 앞서 금속 하부전극을 세정함으로써 표면에 존재하는 산화막을 제거하여, 유효산화막 두께의 증가를 억제하고 금속 하부전극의 산화를 방지하여캐패시터의 누설전류 특성의 열화를 방지할 수 있는 방법이다.The present invention is effective by removing the oxide film present on the surface by cleaning the metal lower electrode prior to depositing a (Ba x Sr 1-x ) TiO 3 (BST) or Ta 2 O 5 thin film during the capacitor manufacturing process of the MIM structure. It is a method of preventing the deterioration of the leakage current characteristics of the capacitor by suppressing an increase in the oxide film thickness and preventing oxidation of the metal lower electrode.
본 발명에서는 일예로 금속 하부전극으로 텅스텐(W) 막을 사용하여 300:1로 희석된 완충산화식각제(buffered oxide etchant, 이하 BOE라 함)로 텅스텐막 표면을 세정한다.In the present invention, for example, a tungsten (W) film is used as a metal lower electrode, and the surface of the tungsten film is cleaned with a buffered oxide etchant (BOE) diluted to 300: 1.
이하, 첨부된 도면 도1a 내지 도1d 그리고 도2를 참조하여 본 발명의 일실시예에 따른 캐패시터 제조 방법을 상세히 설명한다.Hereinafter, a capacitor manufacturing method according to an embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1D and FIG. 2.
먼저, 도1a에 도시한 바와 같이 도핑된 폴리실리콘막(1) 상에 장벽층(barrier layer)인 제1 TiN막(2)을 유기금속화학기상증착법(metal organic chemical vapor deposition, 이하 MOCVD라 함)으로 형성한다. MOCVD 증착 공정에서 원료물질로는 TiN(CH3)2)4(TDMAT)를 이용하고 운반가스로는 He과 Ar을 사용한다. 원료물질의 유량은 200 sccm 내지 500 sccm, 운반가스인 He과 Ar은 각각 100 sccm 내지 300 sccm 정도로 사용하여 증착한다. 반응로 내의 압력은 2 Torr 내지 10 Torr로 유지하고, 300 ℃ 내지 500 ℃ 온도에서 100 Å 내지 200 Å 두께의 제1 TiN막(2)을 증착한다.First, as shown in FIG. 1A, the first TiN film 2, which is a barrier layer, on the doped polysilicon film 1 is referred to as metal organic chemical vapor deposition (MOCVD). To form). In the MOCVD deposition process, TiN (CH 3 ) 2 ) 4 (TDMAT) is used as a raw material and He and Ar are used as carrier gases. The flow rate of the raw material is 200 sccm to 500 sccm, the carrier gas He and Ar are deposited using about 100 sccm to 300 sccm, respectively. The pressure in the reactor is maintained at 2 Torr to 10 Torr, and the first TiN film 2 having a thickness of 100 Pa to 200 Pa is deposited at a temperature of 300 to 500 ° C.
제1 TiN막(2) 증착 후 500 W 내지 1000 W의 전력(power)으로 20초 내지 50초 정도 플라즈마 처리를 실시한다.After deposition of the first TiN film 2, plasma treatment is performed for about 20 to 50 seconds at a power of 500 W to 1000 W.
다음으로, 도1b에 도시한 바와 같이 제1 TiN막(2) 상에 화학기상증착법(chemical vapor deposition, 이하 CVD법이라 함)으로 W막(3)을 증착한다. W막(3) 증착시, 원료 물질로는 WF6를 이용하고 반응가스로는 H2를 사용한다. 증착시 반응로 내의 압력은 80 Torr 내지 110 Torr로 유지하고, 350 ℃ 내지 450 ℃ 온도에서 W막(3)을 증착한다.Next, as shown in FIG. 1B, the W film 3 is deposited on the first TiN film 2 by chemical vapor deposition (hereinafter referred to as CVD method). In depositing the W film 3, WF 6 is used as a raw material and H 2 is used as a reaction gas. During deposition, the pressure in the reactor is maintained at 80 Torr to 110 Torr, and the W film 3 is deposited at a temperature of 350 ° C to 450 ° C.
이어서, W막(3) 표면의 산화막(WO3막)을 제거하기 위해 300:1로 희석된 BOE로 30초 내지 50초 동안 세정 공정을 실시한 후, 도1c에 도시한 바와 같이 저압화학기상증착법(low pressure chemical vapor deposition, LPCVD)으로 Ta2O5막(4)을 증착한다. 이때, Ta2O5막(4)을 대신하여 (BaxSr1-x)TiO3(이하, BST라 함)(상기 x는 1 보다 작다)막을 증착할 수도 있다.Subsequently, in order to remove the oxide film (WO 3 film) on the surface of the W film 3, a cleaning process was performed for 30 seconds to 50 seconds with BOE diluted to 300: 1, followed by low pressure chemical vapor deposition as shown in FIG. 1C. Ta 2 O 5 film 4 is deposited by low pressure chemical vapor deposition (LPCVD). At this time, a (Ba x Sr 1-x ) TiO 3 (hereinafter referred to as BST) film (hereinafter, x is smaller than 1) may be deposited instead of the Ta 2 O 5 film 4.
Ta2O5막(4) 증착 원료 물질로는 0.005 cc 내지 2 cc의 탄탈륨에톡사이드(tantalum etoxide) [Ta(C2H5O)5]를 사용하고, 반응 원료의 운반 가스 및 산화제로는 350 sccm 내지 450 sccm의 N2가스와 20 sccm 내지 50 sccm의 O2가스를 사용한다. 반응로 내의 압력은 0.1 Torr 내지 0.6 Torr로 유지하고, 350 ℃ 내지 450 ℃ 온도에서 Ta2O5막(4)을 증착한다.As a deposition material for Ta 2 O 5 film (4), tantalum etoxide (Ta (C 2 H 5 O) 5 ) of 0.005 cc to 2 cc is used. Uses 350 sccm to 450 sccm of N 2 gas and 20 sccm to 50 sccm of O 2 gas. The pressure in the reactor is maintained at 0.1 Torr to 0.6 Torr, and the Ta 2 O 5 film 4 is deposited at a temperature of 350 ° C. to 450 ° C.
Ta2O5막(4) 증착후 급속열처리(rapid thermal process) 공정으로 550 ℃ 내지 670 ℃ 온도에서 산소 분위기로 열처리하거나, 350 ℃ 이하의 온도에서 10 W 내지 100 W의 전력을 인가하여 02또는 N2O 가스로 플라즈마 어닐(anneal)을 실시한다.After the deposition of the Ta 2 O 5 film (4), a rapid thermal process is used to heat the substrate at an oxygen atmosphere at a temperature of 550 ° C. to 670 ° C., or to apply a power of 10 W to 100 W at a temperature of 350 ° C. or less to give 0 2. Or plasma annealing with N 2 O gas.
어닐 후, 도1d에 도시한 바와 같이 상부전극 물질로서 제2 TiN막(5) 및 도핑된 폴리실리콘막(6)을 차례로 증착하여 캐패시터를 완성한다. 이때, 제2 TiN막(5)은 CVD법 또는 MOCVD법으로 형성한다. MOCVD법을 이용할 경우는 상기 제 TiN막 형성과 동일하게 원료물질로 Ti(N(CH3)2)4를 이용하고 운반가스로 He과 Ar을 사용하여 형성한다. 상기 TiN막(5)은 상부전극을 이루는 폴리실리콘막(6)과 Ta2O5막(4)의 일함수(work function)를 감소시키기 위한 것으로서, CVD법으로 200 Å 내지 500 Å 두께로 증착할 수도 있으며, 이때 원료 물질로는 10 sccm 내지 1000 sccm의 TiCl4를 사용하고 반응가스로는 10 sccm 내지 1000 sccm의 NH3가스를 사용하며 증착시 압력은 0.1 Torr 내지 2 Torr가 되도록 한다. 폴리실리콘막(6)은 800Å 내지 1200 Å 두께로 증착한다.After annealing, as shown in FIG. 1D, the second TiN film 5 and the doped polysilicon film 6 are sequentially deposited as the upper electrode material to complete the capacitor. At this time, the second TiN film 5 is formed by CVD or MOCVD. In the case of using the MOCVD method, Ti (N (CH 3 ) 2 ) 4 is used as a raw material and He and Ar are used as carrier gases in the same manner as the TiN film. The TiN film 5 is to reduce the work function of the polysilicon film 6 and the Ta 2 O 5 film constituting the upper electrode, and is deposited to a thickness of 200 to 500 Å by CVD. In this case, 10 sccm to 1000 sccm of TiCl 4 may be used as a raw material, and 10 sccm to 1000 sccm of NH 3 gas may be used as a reaction gas, and the deposition pressure may be 0.1 Torr to 2 Torr. The polysilicon film 6 is deposited to a thickness of 800 Å to 1200 Å.
도2는 종래와 같이 이전세정(pre-cleaning) 없이 Ta2O5막을 증착한 경우와 본 발명에 따라 W막을 BOE로 이전세정하고 Ta2O5막을 증착한 경우의 전압에 다른 누설전류 특성을 보이는 그래프이다. 1.0 V의 전압에서 종래의 경우 누설전류가 1.04E-4 A/㎠인데 반하여 본 발명의 경우는 3.44E-8 A/㎠로 개선됨을 보이고 있다. 한편, 종래 43.96 Å이었던 유효산화막의 두께도 본 발명에 따라 31.05 Å으로 감소한다.Figure 2 shows the leakage current characteristics different from the voltage when the Ta 2 O 5 film is deposited without pre-cleaning and the W film is transferred to BOE and the Ta 2 O 5 film is deposited according to the present invention. This graph is shown. At a voltage of 1.0 V, the leakage current is 1.04E-4 A / cm 2 in the conventional case, whereas the present invention is improved to 3.44E-8 A / cm 2. On the other hand, the thickness of the effective oxide film, which was 43.96 mm 3, is also reduced to 31.05 mm 3 according to the present invention.
이와 같이 본 발명은 Ta2O5또는 BST 등과 같이 유전막을 갖는 캐패시터 제조 공정 중 하부전극으로 금속 물질을 이용하고 유전막 형성 이전에 하부전극을 세정하여 유전막의 전기적 특성을 향상시킬 수 있는 방법으로서, 실린더 구조 등과같은 3차원 구조의 캐패시터에 적용할 수 있다.As described above, the present invention is a method for improving the electrical characteristics of a dielectric film by using a metal material as a lower electrode and cleaning the lower electrode before formation of a dielectric film during a capacitor manufacturing process having a dielectric film such as Ta 2 O 5 or BST. It can be applied to a capacitor having a three-dimensional structure such as a structure.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 금속 물질을 하부전극으로 사용하고 Ta2O5또는 (BaxSr1-x)TiO3등과 같은 고유전물질을 유전막으로 이용하는 캐패시터 제조 공정 중 유전막 형성 전에 하부전극을 세정함으로써 하부전극 표면에 존재하는 산화막을 제거하여 유전막의 유효 산화막 두께를 감소시키고 누설전류 특성을 향상 시킬 수 있다.According to the present invention, the lower electrode is cleaned before forming the dielectric layer during the capacitor manufacturing process using the metal material as the lower electrode and using the high dielectric material such as Ta 2 O 5 or (Ba x Sr 1-x ) TiO 3 as the dielectric layer. By removing the oxide film present on the lower electrode surface, the effective oxide film thickness of the dielectric film can be reduced and the leakage current characteristic can be improved.
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