KR100373339B1 - Word line control circuit of sram - Google Patents

Abstract

PURPOSE: A word line control circuit of an SRAM is provided to reduce the power consumption by controlling word lines in a write operation. CONSTITUTION: A word line control circuit of an SRAM includes a first voltage detection circuit(21), a second voltage detection circuit(22), and a logic operation circuit(23). The first voltage detection circuit(21) is used for detecting a variation of voltages of data bit line(DB). The second voltage detection circuit(22) is used for detecting a variation of voltages of data bit lines(inverse DB). The logic operation circuit(23) receives an output of the first voltage detection circuit(21) and an output of the second voltage detection circuit(22) and generates a word line control signal.

Description

SRAM's Wordline Control Circuit

TECHNICAL FIELD The present invention relates to semiconductor memories, and more particularly to static RAM (SRAM), and more particularly to word line control circuits of SRAM.

In general, unlike DRAM (Dynamic RAM) cells, SRAM cells have a characteristic of maintaining this information once data is written. Therefore, when the address is changed during the SRAM write operation, the word line of the address is enabled after a predetermined time, and is maintained in the 'on' state, and is disabled at the same time as the write operation is completed.

However, the enable holding time is not adjusted by the time point at which writing is actually performed, and the word line is not disabled until the writing operation is completed.

Therefore, even when the writing operation actually writes to the cell, the word line continues to be 'on', causing a constant current, thereby causing unnecessary power consumption.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an SRAM word line control circuit which can reduce power consumption by controlling a word line during a write operation.

According to an aspect of the present invention for achieving the above object, the first voltage detection means for detecting a voltage change of the positive data bit line; Second voltage detecting means for detecting a voltage change of the sub data bit line; And logic operation means for receiving outputs of the first and second voltage detection means to generate a word line control signal.

In SRAM, the data bit line (DB) and the sub data bit line (DB) ) Is precharged to the power supply voltage (Vcc) and keeps all 'high' while recording '1'. The line drops below a certain voltage and this voltage '1' is recorded in the cell via the line, and when '0' is written, the DB line falls below a certain voltage and '0' is written in the cell via the DB line. In the present invention, the write operation of the SRAM cell and the DB line When each of the voltages are sensed and one of the lines falls below a certain voltage, a detection signal is generated to disable the word lines.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

First degree DB, An explanatory diagram of the voltage change of the line, DB, When the voltage of the line becomes below the predetermined voltage Va, data is written to the cell.

2A-2B is a wordline control circuit diagram according to the present invention, 3A or DB of FIG. 2A, Line voltage variation and signal timing diagram, DB of FIG. 3B or FIG. Fig. 4 is a schematic diagram of an SRAM design using a separate word line technique. Fig. 5 is a circuit diagram of a local X decoder to which the present invention is applied. And 24 denote delay units, and MP1 to MP3 denote PMOS transistors, respectively.

As shown in FIG. 2A, the voltage detector 21 detects a change in voltage of the DB line, and the voltage detector 22 The voltage change of the line is detected, and the negative OR gate 23 receives the outputs of the two voltage detectors 21 and 22 and outputs a constant voltage detection signal for controlling the word line. I.e. DB as 3A help, The line detects a voltage change, and the negative logic sum gate 23 receives the outputs of the two voltage detectors 21 and 22 and outputs a constant voltage detection signal for controlling the word line. I.e. DB as 3A help, Output high when the line is pre-charged (before the write operation), DB, When one of the lines falls below a certain voltage (which is actually written to the cell), it outputs 'low'.

The voltage detectors 21 and 22 are DB or A PMOS transistor (MP1) receiving an input voltage (INPUT) as a gate and a power supply voltage (Vcc) as a source from an input terminal connected to a line, the input voltage (INPUT) as a gate, and a source is the PMOS transistor (MP1). A PMOS transistor (MP2) connected to a drain of the PMOS transistor (MP2) having a drain connected to an output terminal, a gate connected to the output terminal, a source connected to a drain of the PMOS transistor (MP1), and a drain connected to the drain. And a pull-down part comprising an NMOS transistor (MN1) whose input voltage (INPUT) is input to the gate, the source is grounded, and the drain is connected to the output terminal.

Looking at the operation of the present invention configured as described above are as follows.

When the contact point between the PMOS transistor MP1 and the PMOS transistor MP2 is node A, when the power supply voltage Vcc is input to the input terminal, the output voltage of the output terminal becomes '0' and the PMOS transistor MP3 is turned on. The node A has a potential of the threshold voltage V _tp of the PMOS.

Then, the input voltage (INPUT) of the input stage is decreased when the threshold voltage (V _tp) of the PMOS transistor (MP1) is "on", but the transfection sitter (MP2) is node A and the potential of the threshold voltage (V _tp) of the PMOS It is still 'off' because it has a potential.

However, if the input voltage INPUT continues to decrease, the output voltage increases and the transistor MP1 is 'off' to increase the potential of the node A. As the potential of the node A increases, the transistor MP2 is 'on' momentarily and the pull-up occurs at a high speed to generate a pulse having a sharp edge, and the pull-down operation is performed. It's almost like a normal CMOS inverter.

Therefore, the length L and the width W of the two transistors MP2 and MP3 channels are adjusted to maintain a 'low' at a predetermined constant voltage or higher, and to be 'high' when the predetermined voltage is lower than the predetermined voltage.

And the DB of the worst case circuit of FIG. Line (the DB farthest from the data input buffer, Line) and the output signal is applied to logic that disables the word line when the sensor finishes sensing during read operation.

Also, DB, like 3B help If the line falls below a certain voltage and is written to the cell at some time after V _b , a delay part causing some delay may be attached to the output of FIG. 2A as shown in FIG. 2B to delay the constant voltage detection signal.

Therefore, when designing an SRAM using the wordline technique divided into a global X decoder, a section X decoder and a local X decoder as in the fourth diagram, the local X decoder configured as the fifth diagram in each block enables the section X decoder. A constant voltage detection signal is applied to adjust the word line pulses.

As described above, the present invention is a DB, By disabling the word line by detecting the point of time when the voltage is written to the cell, the flow of static current can be interrupted and unnecessary power consumption can be reduced.

First degree DB, Explanatory diagram of the voltage change of the line,

2A to 2B is a word line control circuit diagram according to the present invention,

DB of FIG. 3A or FIG. 2A, Line voltage variation and signal timing

3 is the DB of FIG. 2B, Line voltage variation and signal timing

4 is an explanatory diagram of an SRAM design using a separate wordline technique;

5 is a circuit diagram of a local X decoder to which the present invention is applied.

* Explanation of symbols for main parts of the drawings

21,22: voltage detector 23: negative logic gate

MP1 to MP3: PMOS transistor 24: delay unit

Claims (4)

First voltage detecting means for detecting a voltage change of the positive data bit line; Second voltage detecting means for detecting a voltage change of the sub data bit line; And Logic operation means for generating the word line control signal by receiving the output of the first and second voltage detection means SRAM word line control circuit having a. The method of claim 1, And a delay means for delaying the output of the logic operation means by a predetermined time period. The method according to claim 1 or 2, The first and second voltage detection means, respectively A first PMOS transistor receiving an input voltage from a input terminal as a gate and a power supply voltage as a source; a second inputting the input voltage as a gate and a source connected to a drain of the first PMOS transistor, the drain being connected to an output terminal; A pull-up part including a PMOS transistor, a third PMOS transistor having a gate connected to the output terminal, a source connected to a drain of the first PMOS transistor, and a drain being grounded; And a pull-down part having an NMOS transistor having the input voltage input to a gate, a source being grounded, and a drain connected to the output terminal. The method according to claim 1 or 2, And said logic operation means comprises a negative logic gate for inputting the outputs of said first and second voltage detection means.