KR100370134B1 - Semiconductor memory device - Google Patents

Abstract

The present invention is to provide a semiconductor memory device that can have a flexible internal time margin according to the clock signal cycle and the operation speed of the semiconductor memory device, the structure of the semiconductor memory device for achieving the above object is an external clock signal A clock buffer for receiving an internal clock signal, a command decoder for receiving an external command signal and outputting an internal command signal in synchronization with the internal clock signal, and receiving an external address signal to synchronize with the internal clock signal An address decoder for outputting an internal address signal, a row control for receiving a signal for controlling a word line and a sense amplifier by receiving the internal command signal and the internal address signal, and detecting a clock period by receiving the external clock signal; Delay control signal, which is a signal that controls the internal delay, A clock cycle detector for outputting the first delay unit for adjusting the operation time of the sense amplifier by receiving the delay signal, a second delay unit for adjusting the disable point of the word line according to the delay signal, and a semiconductor memory device; It is characterized by consisting of a conventional bit line and a memory cell.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to semiconductor memory devices suitable for softening an internal time margin in accordance with the operation speed of the device.

In a semiconductor memory device, a delay time must be secured in order to load a charge of a memory cell on a bit line or to write a charge of a bit line to a memory cell.

However, since the delay time is fixed regardless of the operating speed of the semiconductor memory device, a chip that lacks a time margin in a high speed operation is classified as defective.

Various methods have been proposed to secure an appropriate time margin of such a semiconductor memory device.

Hereinafter, a semiconductor memory device according to the related art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a conventional semiconductor memory device, and FIG. 2 is an operation timing diagram of a conventional semiconductor memory device.

First, as shown in FIG. 1, a circuit of a conventional semiconductor memory device receives a clock buffer 1 that receives an external clock signal and generates an internal clock signal, and an external command signal. A command decoder 2 for outputting an internal command signal in synchronization with the internal clock signal, and an address decoder for receiving an external address signal and outputting an internal address signal in synchronization with the internal clock signal ( A row control (Row) for receiving an address decoder (3) and a signal for controlling a word line (7) and a sense amplifier (8) by receiving the internal command signal and the internal address signal. Control 4, the first delay unit 5 for adjusting the operating time of the sense amplifier 8, the second delay unit 6 for adjusting the disable timing of the word line 7, Conventional Bit Lines of Semiconductor Memory Devices (Bi) t Lines 10 and 10a and memory cells 9.

A driving method of a conventional semiconductor memory device having the above configuration will be described below.

When the command decoder 2 outputs an Act signal among the internal command signals by the combination of the external command signals, the external address signal is decoded and input to the row control 4.

Thereafter, when the word line 7 is enabled, the charge of the memory cell 9 in which the data '1' is stored flows into the first bit line 10.

As shown in FIG. 2, the voltage level of the first bit line 10 increases slightly.

The sense amplifier 8 uses the first delay unit 5 to secure Delay1, which is a predetermined delay time, so that the charge of the memory cell 9 can be sufficiently loaded on the first bit line 10. The operation signal is received from the first delay unit 5 and the voltage difference between the first bit line 10 and the second bit line 10a is detected and amplified to '1' and '0', respectively.

That is, as shown in FIG. 2, after the voltage level of the word line 7 increases, the voltage level of the first bit line 10 increases slightly, and when the voltage level of the operation signal increases, the first bit line increases. The voltage levels of 10 and the second bit line 10a are amplified.

On the contrary, in the case where the automatic precharge signal is generated by the command decoder 2 due to the combination of the external command signals, the word line 7 causes the display after the delay time Delay2, which is a predetermined delay time, is passed by the second delay unit 6. It is disabled.

Delay2 is a delay time for allowing the charges of the first bit line 10 and the second bit line 10a to be sufficiently written in the memory cell 9, and a predetermined time must be secured from an external clock signal.

However, the conventional semiconductor memory device as described above has the following problems.

First, since the delay time is fixed irrespective of the period of the external clock signal and the operation speed of the semiconductor memory device, the semiconductor memory device is classified as defective even if the time margin is insufficient by about 1 to 2 ns in the high speed operation.

Second, a circuit change experiment is required to see time margins at the time of the sense amplifier operation and the word line disable time.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the semiconductor memory device of the prior art, and an object thereof is to provide a semiconductor memory device having a flexible internal time margin according to a cycle of an external clock signal and an operating speed of the semiconductor memory device.

1 is a block diagram of a conventional semiconductor memory device

2 is a timing diagram of a conventional semiconductor memory device.

3 is a configuration diagram of a semiconductor memory device according to the present invention.

4 is a timing diagram during the act operation according to the present invention.

5 is a timing diagram at the time of automatic precharge operation according to the present invention.

6 is a circuit diagram of a clock period detector according to the present invention.

7 is a timing diagram of a clock period detector according to the present invention.

Explanation of symbols for the main parts of the drawings

21: clock buffer 22: command decoder

23: address decoder 24: row control

25 clock cycle detector 26 first delay unit

27: second delay unit 28: sense amplifier

29 word line 30 memory cell

31, 31a: first bit line, second bit line

In accordance with an aspect of the present invention, a semiconductor memory device may include a clock buffer configured to receive an external clock signal and generate an internal clock signal, and output an internal command signal in synchronization with the internal clock signal by receiving an external command signal. A command decoder that receives a command decoder, an external address signal, and outputs an internal address signal in synchronization with the internal clock signal, and receives a signal that controls the word line and the sense amplifier by receiving the internal command signal and the internal address signal. A row period for outputting the output signal, a clock period detector for outputting a delay signal which is a signal for controlling an internal delay by detecting a clock period by receiving the external clock signal, and a timing for adjusting an operation time of a sense amplifier by receiving the delay signal; 1 delay unit and the word line display according to the delay signal. And a second delay unit for adjusting the time table, characterized by consisting of a conventional bit line and the memory cells of the semiconductor memory device.

According to an aspect of the present invention, a method of driving a semiconductor memory device may include converting an external clock signal into an internal clock signal; Outputting an internal command signal by combining the internal clock signal and an external command signal; Decoding the internal clock signal and an external address signal; Detecting a period of the external clock signal; Determining whether the internal command signal is an act signal or an auto precharge signal; And a delay unit adjusting a sense amplifier operation time and a disable time point of the word line according to the period of the external clock signal.

Hereinafter, a semiconductor memory device and an operation thereof of the present invention will be described with reference to the accompanying drawings.

3 is a configuration diagram of a semiconductor memory device according to the present invention.

First, as shown in FIG. 3, the semiconductor memory device according to the present invention includes a clock buffer 21 for receiving an external clock signal and generating an internal clock signal, and receiving an external command signal to the internal clock signal. A command decoder 22 that synchronously outputs an internal command signal, an address decoder 23 that receives an external address signal and outputs an internal address signal in synchronization with the internal clock signal, and the internal command signal and the internal address A row control 24 that receives a signal and outputs a signal for controlling the word line 29 and the sense amplifier 28, and receives an external clock signal to detect clock periods at (n-1) and (n) points. Clock period detector 25 for outputting a delay control signal, which is a signal for controlling internal delay, and a first delay for receiving an input of the delay signal and adjusting an operation time of the sense amplifier 28. And a second delay unit 27 for adjusting the disable timing of the word line 29 according to the delay signal, and the conventional bit lines 31 and 31a and the memory cell 30 of the semiconductor memory device. It is composed of

Referring to the driving method of the semiconductor memory device of the present invention having the above configuration as follows.

4 is a timing diagram when an act signal occurs in the command decoder 22, and FIG. 5 is a timing diagram when an auto precharge signal occurs.

First, the clock buffer 21 receives an external clock signal as an input and outputs an internal clock signal.

The command decoder 22 outputs an internal command signal by combining the internal clock signal and the external command signal.

In addition, the external address signal is decoded and input to the row control 24.

The clock period detector 25 receives the external clock signal and detects the period of the external clock signal at (n-1) and (n) time points.

Thereafter, the command decoder 22 selects and outputs one of an act signal and an auto precharge signal, which are internal command signals, by the external command signal.

If the command decoder 22 outputs an act signal as shown in FIG. 4, the charge of the memory cell 30 in which the corresponding word line 29 is enabled and data '1' is stored is first. It flows into the bit line 31.

Here, the voltage level of the first bit line 31 rises slightly.

The clock period detector 25 transmits the delay control signal at the time (n) to the first delay unit 26 for the period of the external clock signal.

Here, the delay control signal may have 2 to 4 bits and may be selected according to the operating speed of the semiconductor memory device when designing a circuit.

Thereafter, the first delay unit 26 decodes the input delay control signal to speed up the operation of the sense amplifier 28 when the period between (n-1) and (n) is short, and (n-1). If the period between the viewpoint and the (n) viewpoint is long, the operation of the sense amplifier 28 is delayed.

The sense amplifier 28 detects a voltage difference between the first bit line 31 and the second bit line 31a and amplifies the signals to '1' and '0', respectively.

On the contrary, as shown in FIG. 5, when the command decoder 22 outputs the automatic precharge signal, the clock period detector 25 sends the delay control signal at the time (n) to the second delay unit 27. send.

Thereafter, the second delay unit 27 decodes the input delay signal, and if the period between the (n-1) time point and the (n) time point is short, accelerates the disable time point of the word line 29, and (n-1). If the period between the time point n) and time point n is long, the disable time point of the word line 29 is delayed.

Through this operation, the operating time of the sense amplifier 28 and the disabling time of the word line 29 may be adjusted in proportion to the period of the external clock signal of the semiconductor memory device.

In addition, while operating the semiconductor memory device at a constant speed, the sense amplifier 28 operates while inputting the act signal at the (n) time point of the external clock signal and changing only the periods at the (n-1) time point and the (n) time point of the clock signal. By adjusting the viewpoint, the bit line sensing timing of the semiconductor memory device may be tested.

On the contrary, while operating the semiconductor memory device at a constant speed, the automatic precharge signal is input at the (n) time point of the external clock signal and the word line 29 is changed while only changing the periods at the (n-1) time point and the (n) time point of the clock signal. By adjusting the disable timing, the automatic precharge timing can be tested after writing the data of the semiconductor memory device.

6 is a circuit diagram of a clock period detector 25 according to the present invention.

As illustrated in FIG. 6, the clock period detector 25 inputs the first delay signal and the inverters INV01, INV02, INV03, INV04, INV05, and CNV01 that output the first delay signal through the input of an external clock signal. The inverters INV11, INV12, INV13 and CNV11 for outputting the second delay signal, the inverters INV21, INV22, INV23 and CNV21 for outputting the third delay signal, and the third delay signal for inputting the second delay signal. Inverters INV31, INV32, INV33, and CNV31 that output a fourth delay signal, NAND0 that receives the external clock signal and the output signal of INV03, INV0 that outputs the LCLKT signal by inputting the output signal of the NAND0, NMOS01, NMOS11, NMOS21, NMOS31, and the third and fourth delay signals having the LCLKT signal as a gate input, the first, second, third and fourth delay signals as drain inputs, and the VSS as a source input. NOR07 serving as an input, NAND07 serving as the input of the second delay signal and the NOR07, INV07 serving as the fourth delay signal, and NAND17 serving as the input of the third delay signal and the INV07. NAND08 outputting a CLKEN <0> signal to the outputs of the NAND07 and INV07; DFF01 and DFF11 to latch CLKEN <0> and CLKEN <1> signals respectively, and to pass CLKEN <0> and CLKEN <1> signals when the LCLKT signal is Logic 'L', and the DFF01 and DFF11, respectively. It is composed of DFF02 and DFF12 circuits that respectively receive the output signals of the LCLKT signal and pass the input signal when the logic signal is 'H', and when the LCLKT signal is the logic 'L', latch and output the delay control signal.

7 is a timing diagram for explaining the operation of the clock period detector 25 according to the present invention.

From the period 1 to the fourth delay signal, the value is latched through DFF01 and DFF11 at the point (n-1) of the external clock signal and passed through the DFF02 and DFF12 so that the delay control signal at the point (n-1) is With the value of '11' which is a periodic value, and in Period2, since the external clock signal at (n) is generated after the third delay signal is generated and before the fourth delay signal is generated, this value is latched and passed to (n) delay control. The signal has a value of '10' which is a period value of Period2.

Due to this operation, when the clock period detector () according to the present invention is used, the period of the external clock signals of (n-1) and (n) is detected at (n) and the delay control signal is detected by the first delay unit ( 26) and the second delay unit 27 adjusts the operation of the sense amplifier 28 and the word line 29 disable timing according to the period of the external clock signal.

The circuit of the semiconductor memory device of the present invention as described above has the following effects.

It has a step-by-step delay time for low-speed or high-speed operation according to the period of the external clock signal, and a flexible internal time margin can be secured according to the operation speed of the semiconductor memory device.

In addition, the test for securing the operating margin at the time of operating the sense amplifier and the time of disabling the word line while reducing the period of (n-1) and (n) from the predetermined time before the internal command signal is input is performed. can do.

Claims (4)

A clock buffer which receives an external clock signal and generates an internal clock signal; A command decoder configured to receive an external command signal and output an internal command signal in synchronization with the internal clock signal; An address decoder configured to receive an external address signal and output an internal address signal in synchronization with the internal clock signal; A row control which receives the internal command signal and the internal address signal and outputs a signal for controlling a word line and a sense amplifier; A clock period detector which receives the external clock signal and detects a clock period and outputs a delay control signal which is a signal for controlling an internal delay; A first delay unit which receives the delay signal and adjusts an operation time of a sense amplifier; A second delay unit for adjusting a disable point of a word line according to the delay signal; A semiconductor memory device comprising a conventional bit line and a memory cell of a semiconductor memory device. Converting an external clock signal into an internal clock signal; Outputting an internal command signal by combining the internal clock signal and an external command signal; Decoding the internal clock signal and an external address signal; Detecting a period of the external clock signal; Determining whether the internal command signal is an act signal or an auto precharge signal; And a delay unit adjusting a sense amplifier operation time and a disable time point of the word line according to the period of the external clock signal. The method of claim 2, wherein the detecting of the period of the external clock signal comprises detecting periods of time (n-1) and time point (n). 3. The method of claim 2, wherein in the adjusting of the sense amplifier operation point and the word line disable point according to the period of the external clock signal, the periods of the (n-1) time point and the (n) time point of the clock signal are varied. And a test for securing an operation margin at a sense amplifier operation point and a word line disable point.