KR100376265B1 - Memory repair circuit using an antifuse having a MOS structure - Google Patents

Abstract

According to an exemplary embodiment of the present invention, a memory repair circuit includes a power-up reset circuit for outputting a power supply voltage when a power becomes higher than a predetermined voltage at 0V, an address multiplexer for outputting a signal for selecting a fuse to be programmed, a voltage generator for supplying a program voltage, and An antifuse circuit for programming the antifuse device according to the output of the power-up reset circuit, the address multiplexer and the voltage generator and sensing whether the antifuse device is programmed, and a defective cell to the redundancy cell according to the output signal of the antifuse circuit. It includes a redundancy block for replacing.

Description

Memory repair circuit using an antifuse having a MOS structure}

The present invention relates to an antifuse having an MOS (Metal-Oxide-Semiconductor) structure and a memory repair circuit using the same.

BACKGROUND OF THE INVENTION Semiconductor integrated circuits have led to the inclusion of more circuit elements in a given silicon region as technology advances. Reducing or eliminating defects in these circuit elements requires more circuit elements. To maximize die utilization and achieve higher densities, circuit designers are struggling to reduce the size of individual circuit elements. This reduction in size makes these circuit elements increasingly affected by defects due to impurities during the manufacturing process. Such defects should be identifiable by testing procedures upon completion of integrated circuit fabrication, or by semiconductor chip level or package completion. It is economically undesirable to discard defective integrated circuits when a defect is identified, especially when a small number of circuit elements are actually defective.

Expecting zero defects in the fabrication of integrated circuits is impractical. Thus, redundant circuits are provided in the integrated circuit to reduce the number of integrated circuits discarded. If the first device is determined to be defective, then the redundant circuitry replaces the defective circuitry. The actual reduction in discarded devices is achieved using redundant circuitry without a substantial increase in the cost of integrated circuit devices.

One integrated circuit that uses redundant circuitry is, for example, integrated memory circuits such as DRAM, SRAM, VRAM, and EPROM. Typical integrated memory circuits include a plurality of memories arranged in an array of addressable rows and columns. The memory in rows and columns is the first circuit element of the integrated memory circuit. By providing redundant circuitry, the defective first column, row, or individual bit can be replaced.

Since the first circuit elements of the individual integrated memory circuits can be addressed separately, a fuse control programmable circuit for programming a redundant circuit according to the fuse blowing or the address of the defective first circuit element to replace the defective element. Requires antifuse. This process is very effective for permanently replacing defective devices.

For example, in the case of DRAM, a particular memory cell is selected by providing the row and column address where the particular memory cell is located. The redundancy circuit must recognize a valid first memory circuit element and cause all signals to be changed to the redundant circuit element when an address for the defective first circuit element is provided by the user. Thus, multiple fuses or antifuses are associated with each redundant circuit element. Possible combinations of blown or unblown fuses corresponding to each redundant circuit element represent a single address of all the first elements that the corresponding redundant element will replace.

The anti-fuse is a device that serves as a switch that connects two electrodes by using breakdown in the structure of the electrode / insulator / electrode. The dielectric breakdown voltage of this insulator is called the anti-fuse program voltage (PGM), and the two electrodes are short-circuited through the program.

The present invention provides a memory repair circuit using an anti-fuse of the MOS structure capable of repairing defective cells by configuring the anti-fuse as a MOS (Metal / Oxide / Semiconductor) transistor and properly programming the anti-fuse circuit employing the same. There is a purpose.

The memory repair circuit according to the present invention includes a plurality of antifuse elements programmed when a power supply voltage is supplied to a first electrode and a negative voltage is supplied to a second electrode;

A latch unit for detecting and latching a program state of the antifuse device;

And a redundancy block for replacing a defective cell with a redundancy cell according to the output of the latch unit.

Memory repair circuit according to an embodiment of the present invention is a power-up reset circuit for outputting a power supply voltage when the power is above a certain voltage at 0V,

An address multiplexer that outputs a signal for selecting a fuse to be programmed;

Voltage generator for supplying program voltage,

An antifuse circuit for programming an antifuse device according to the output of the power up reset circuit, an address multiplexer and a voltage generator and sensing whether the antifuse is programmed;

And a redundancy block for replacing a defective cell with a redundancy cell according to the output signal of the antifuse circuit.

1A is a block diagram illustrating a memory repair circuit using antifuse according to the present invention.

FIG. 1B is a diagram for explaining an output state of the voltage generator of FIG. 1. FIG.

2 is a first embodiment of the antifuse circuit of FIG.

3 is a second embodiment of the antifuse circuit of FIG.

4A to 4C are views showing the configuration of the antifuse device used in FIG.

5A is a waveform diagram for explaining the operation of FIG. 2;

5B is a waveform diagram for explaining the operation of FIG.

6A to 6F are views showing the configuration of the antifuse device used in FIG.

Explanation of symbols on the main parts of the drawings

10: anti-fuse circuit 20: power-up reset circuit

30: address multiplexer 40: voltage generator

50: redundancy blocks 60, 31; Bias control

80, 33: latch portion 32, 70: antifuse element

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A is a block diagram illustrating a memory repair circuit using antifuse according to the present invention. The repair circuit according to the present invention includes an anti-fuse circuit 10 for programming an anti-fuse and sensing whether the anti-fuse is programmed, a power-up reset circuit 20 for outputting a VCC when the power becomes above a predetermined voltage at 0 V, a program Redundancy for replacing a defective cell with a redundancy cell according to the address multiplexer 30 for outputting a signal for selecting a fuse to be connected, the voltage generator 40 for supplying a program voltage, and the output signal RO of the antifuse circuit 10. Block 50. The voltage generator 40 outputs, for example, -4V (NGND) or 0V through the anode terminal of the PN diode D1 connected between the negative voltage generating terminal NGND and ground as shown in FIG. For example, 8V (PVCC) or VCC (3.3V) voltage is output through the cathode terminal of the PN diode D2 connected between the VCC terminal and the PVCC terminal.

FIG. 2 is a first embodiment of the antifuse circuit of FIG. 1. The antifuse circuit is a circuit for programming antifuse using the voltage difference between VCC (3.3V) and NGND (-4V), and is composed of a bias control unit 60, an antifuse element 70, and a latch unit 80. An operation of the antifuse circuit will be described with reference to FIG. 5A.

Initialization behavior

If the control signal pwrupb from the power-up reset circuit 20 is high as shown in FIG. 5A and the special address SA is low, the output of the NOR gate I11 becomes low and passes through the PMOS transistor P12. The power supply voltage Vcc is transmitted to the first node N1. In addition, the power supply voltage Vcc is transferred to the second node N2 through the PMOS transistor P14. Since the control signal pwrup from the power-up reset circuit 20 is low, the power supply voltage Vcc is transmitted to the third node N3 through the PMOS transistor P15, but the NMOS transistor N16 is transmitted by the control signal pwrupb. ) Is turned on and the NMOS transistor N17 is turned on by the high potential of the second node N2, so that the output RO of the latch formed of the inverting gates I18 and I19 becomes high.

Program behavior

When the power is stabilized and the control signal pwrup-p goes high with a short pulse, the first and second nodes and the second nodes N1 and N2 are initialized to 0V. When the special address SA for selecting the antifuse device becomes high, VCC is applied to one electrode of the antifuse device 70, that is, the second node N2. At this time, when the output NGND of the voltage generator 40 becomes -4V and is transferred to the other electrode of the antifuse device 70, the voltage difference between the two ends of the antifuse device 70 becomes a high voltage of 7V or more. 70 is programmed.

Read and Latch Operation

After the program is completed, power is stabilized for a certain period of time when the power is turned off and then on as shown in FIG. 5A. At this time, the control signal pwrupb becomes high so that the output of the NOR gate I11 becomes low. Therefore, when VCC is transmitted to the first and second nodes N1 and N2 and the anti-fuse device 70 is programmed, the voltage of the second node N2 is passed to the ground through the anti-fuse device 70, so that the low do. Since the control signal pwrup goes low, the third node N3 becomes the VSS potential, but since the second node N2 is low, the current path to the ground is blocked. Thus, the output of latch 80 remains low.

The antifuse element 70 used in FIG. 2 may be configured as shown in FIGS. 4A, 4B, 4C, and 4D. The configuration thereof is as follows.

Referring to FIG. 4A, an N well 110 is formed in the P-type substrate 100, and a P well 120 is formed in the N well 110. A first N + region 130A and a second N + region 130B are formed in the P well 120, and an insulating film and a gate electrode are formed on the substrate 100 between the first and second N + regions 130A and 130B. 140 is formed sequentially. The gate electrode 140 is connected to VCC and the first and second N + regions 130A and 130B are connected to the negative voltage generator terminal NGND of the voltage generator 40 of FIG. 1.

Referring to FIG. 4B, an N well 110 is formed in the P-type substrate 100, and a P well 120 is formed in the N well 110. An N + region 130 is formed in the P well 120, and an insulating film and a gate electrode 140 are sequentially formed on one side of the substrate 100 of the N + region 130. The gate electrode 140 is connected to the VCC and the N + region 130 is connected to the negative voltage generator terminal NGND of the voltage generator 40 of FIG. 1.

Referring to FIG. 4C, an N well 110 is formed in a P-type substrate 100, and a first P + region 150A and a second P + region 150B are formed in the N well 110. An insulating film and a gate electrode 140 are sequentially formed on the substrate 100 between the first and second P + regions 150A and 150B. The gate electrode 140 is connected to the VCC and the first and second P + regions 150A and 150B are connected to the negative voltage generator terminal NGND of the voltage generator 40 of FIG. 1.

Referring to FIG. 4D, an N well 110 is formed in the P-type substrate 100, a P + region 150 is formed in the N well 110, and an upper portion of the substrate 100 on one side of the P + region 150 is formed. In the insulating film and the gate electrode 140 are sequentially formed. The gate electrode 140 is connected to VCC and the N + region 130 is connected to the negative voltage generation terminal NGND of the voltage generator 40 of FIG. 1.

4A to 4D, VCC (3.3V) is applied to the gate electrode and NGND (-4V) is applied to the junction to generate dielectric breakdown at the edge portion between the gate terminal and the junction. The gate electrode and the junction are turned on. 4A and 4B are constructed using triple well NMOS, and FIGS. 4C and 4D are constructed using triple well PMOS. The P wells of FIGS. 4A and 4B are left in a floating state or connected to the negative voltage generating terminal NGND of the voltage generator 40, and VCC is applied to the N wells. The N wells of FIGS. 4C and 4D are in a floating state. Keep it.

3 is a second embodiment of the antifuse circuit of FIG. FIG. 3 is a circuit diagram of applying and programming a positive voltage generated by the voltage generator 40 to the antifuse element, and includes an antifuse element 32, a bias control unit 31, and a latch unit 33. The operation of FIG. 3 will be described with reference to FIG. 5B.

Initialization behavior

As shown in FIG. 5B, the VCC voltage is transmitted to the gate electrode of the antifuse element 32 during the initialization period (power stabilization period), but since the antifuse element 32 is not programmed (off state), the fourth node N4. ) Does not carry VCC.

Since the control signal pwrup_p of FIG. 5B is high, the PMOS transistor P20 is turned off. Since the NMOS transistor N21 is turned on or the fourth node N4 is low, the fifth node N5 is also low. do. At this time, since the special address SA is low, the NMOS transistor N22 is turned off. Since the control signal pwrupb is high, the NMOS transistor N23 (designed with a very large on-state resistance) is turned on, which makes the fifth node N5 surely low. Since the control signal pwrup is low, VCC is transmitted to the sixth and seventh nodes N6 and N7 through the PMOS transistors P24, P25, and P27, respectively. At this time, the control signal pwrup_p is high, but since the on resistance of the NMOS transistor N26 is increased, the sixth node N6 has a constant voltage. The PMOS transistor P27 is turned off by the potential of the sixth node N6, while the NMOS transistor N28 is turned on, so the seventh node N7 is turned low. Therefore, the output RO of the latch composed of the inverters I29 and I30 goes low. When the power is stabilized, the control signal pwrup is high and the control signal pwrupb is low, and the PMOS transistor P24 and the NMOS transistor N23 are turned off. If the control signal pwrupb_p is a low signal with a short pulse, the PMOS transistor P20 is turned on, and VCC is applied to the fifth and fourth nodes N5 and N4 to be initialized. When the control signal pwrupb_p becomes high again, the PMOS transistor P20 is turned off while the NMOS transistor N26 is turned on to bring the sixth node N6 low.

Program operation

When the special address SA becomes high, the NMOS transistor N22 is turned on so that the fourth node and the fifth node N4 and N5 become high. When a high voltage (7 V or more) is output from the positive voltage output terminal PVCC of the voltage generator 40 of FIG. 1, the anti-fuse device is programmed. The high-fuse device is connected to the fourth node N4 through the anti-fuse device 32. However, since the gate voltage of the NMOS transistor N21 is VCC (3.3V or more), the voltage difference between the gate and the fourth node N4 is less than 4V, thereby stably operating below the breakdown voltage.

Read and Latch Operation

When the program is completed, as shown in FIG. 5B, when the power is turned off and then turned on, power stabilization is performed for a predetermined period, and the control signal pwrupb_p becomes high so that the PMOS transistor P20 is turned off. Since the VCC is transmitted to the antifuse element 32 through the positive voltage output terminal PVCC of the voltage generator 40 and the antifuse element 32 is programmed (on state), the fourth and fifth nodes N4 and V5 is delivered to N5). Since the special address SA is low, the NMOS transistor N22 is turned off. Although the control signal pwrupb is high, since the on-resistance of the NMOS transistor N23 is very large, there is almost no current path through the NMOS transistor N23. Therefore, the fifth node N5 remains high. Since the control signal pwrup is low, the PMOS transistor P24 is turned on or the PMOS transistor P25 is turned off due to the potential of the fifth node N5, so the sixth node N6 remains low. . Since the sixth node N6 is in the low state, the PMOS transistor P27 is turned on, while the NMOS transistor N28 is turned off, so that the VCC is transmitted to the seventh node N7 through the PMOS transistors P24 and P27. Therefore, the seventh node N7 goes high and the output of the latch 33 goes low.

The antifuse element 32 used in FIG. 3 may be configured as shown in FIGS. 6A, 6B, 6C, 6D, 6E, and 6F. The configuration thereof is as follows.

Referring to FIG. 6A, an N well 110 is formed in the P-type substrate 100, and a P well 120 is formed in the N well 110. A first N + region 130A and a second N + region 130B are formed in the P well 120, and an insulating film and a gate electrode are formed on the substrate 100 between the first and second N + regions 130A and 130B. 140 is formed sequentially. The gate electrode 140 is connected to the positive voltage generation terminal PVCC of the voltage generator 40 of FIG. 1, and the first and second N + regions 130A and 130B are connected to the fourth node N4 of FIG. 3. .

Referring to FIG. 6B, an N well 110 is formed in the P-type substrate 100, and a P well 120 is formed in the N well 110. An N + region 130 is formed in the P well 120, and an insulating film and a gate electrode 140 are sequentially formed on one side of the substrate 100 of the N + region 130. The gate electrode 140 is connected to the positive voltage generation terminal PVCC of the voltage generator 40 of FIG. 1, and the N + region 130 is connected to the WP 4 node N4 of FIG. 3.

Referring to FIG. 6C, an N well 110 is formed in a P-type substrate 100, and a first P + region 150A and a second P + region 150B are formed in the N well 110. An insulating film and a gate electrode 140 are sequentially formed on the substrate 100 between the first and second P + regions 150A and 150B. The gate electrode 140 is connected to the positive voltage generating terminal PVCC of the voltage generator 40 of FIG. 1, and the first and second P + regions 150A and 150B are connected to the fourth node N4 of FIG. 3. do.

Referring to FIG. 6D, an N well 110 is formed in the P-type substrate 100, a P + region 150 is formed in the N well 110, and is formed on the one side substrate 100 of the P + region 150. In the insulating film and the gate electrode 140 are sequentially formed. The gate electrode 140 is connected to the positive voltage generating terminal PVCC of the voltage generator 40 of FIG. 1, and the N + region 130 is connected to the fourth node N4 of FIG. 3.

Referring to FIG. 6E, an N well 110 is formed in the P-type substrate 100, and a first N + region 130A and a second N + region 130B are formed in the N well 110. An insulating film and a gate electrode 140 are sequentially formed on the substrate 100 between the first and second N + regions 130A and 130B. The gate electrode 140 is connected to the positive voltage generating terminal PVCC of the voltage generator 40 of FIG. 1, and the first and second N + regions 130A and 130B are connected to the fourth node N4 of FIG. 3. do.

In Figs. 6A to 6E, PVCC (7V) is applied to the gate electrode and 0V is applied to the junction to generate insulation breakdown at the edge portion between the gate electrode and the junction, thereby making the gate electrode and the junction between the on state.

Referring to FIG. 6F, a P well 120 is formed in a P-type substrate 100, an N + region 130 is formed in the P well 120, and an upper portion of one substrate 100 of the N + region 150 is formed. In the insulating film and the gate electrode 140 are sequentially formed. The gate electrode 140 is connected to the positive voltage generating terminal PVCC of the voltage generator 40 of FIG. 1, and the N + region 130 is connected to the fourth node N4 of FIG. 3. 6A and 6B are constructed using triple well NMOS, and FIGS. 6C and 6D are constructed using triple well PMOS. 6E and 6F are constructed using NMOS. The P wells of FIGS. 6E and 6F are left floating or connected to the junction and VCC is applied to the N wells. The N wells of FIGS. 6C and 6D are left floating or connected to the junction. The P wells of FIGS. 6E and 6F are kept floating.

As described above, the present invention can replace a defective cell of a memory device with a redundant cell by using a method of electrically programming an anti-fuse device having a MOS structure, and in particular, a defect generated after a burn-in test is also repaired. It is possible to improve the productivity of the memory device.

Claims (32)

An anti-fuse device comprising a plurality of anti-fuse devices programmed when a power supply voltage, a source and a drain are supplied with a negative voltage, and a latch unit for detecting and latching a program state of the anti-fuse device. Circuit; An address multiplexer for selecting the antifuse device; A voltage generator for supplying the negative voltage; And And a redundancy block for replacing a defective cell with a redundancy cell according to the output of the latch unit. delete The method of claim 1, And the MOS transistor comprises NMOS having a source and a drain formed in a triple P well. The method of claim 3, wherein And maintaining the triple P well in a floating state or connected to the drain and the source. The method of claim 1, And the MOS transistor has only one of a source and a drain formed in a triple P well. The method of claim 5, And maintaining the triple P well in a floating state or connected to the drain and the source. The method of claim 1, And the MOS transistor comprises a PMOS having a source and a drain formed in an N well of a P-type substrate. The method of claim 7, wherein And the N well of the PMOS is floated. The method of claim 1, And the MOS transistor forms only one of a source or a drain in an N well of a P-type substrate, and a power supply voltage is supplied to a gate, and a negative voltage is supplied to one of the source or a drain, respectively. A power-up reset circuit that outputs a supply voltage when the power is above a certain voltage at 0V, An address multiplexer that outputs a signal for selecting a fuse to be programmed; Voltage generator for supplying program voltage, An antifuse circuit for programming an antifuse device consisting of MOS transistors and sensing whether the antifuse device is programmed according to an output of the power up reset circuit, an address multiplexer and a voltage generator; And a redundancy block for replacing a defective cell with a redundancy cell according to the output signal of the antifuse circuit. The method of claim 10, And the MOS transistor is composed of NMOS having a source and a drain formed in a triple P well, and a power voltage is connected to a gate electrode, and a source and a drain are connected to each other so that a negative voltage is applied to the MOS transistor. The method of claim 11, And maintaining the triple P well in a floating state or connected to the drain and the source. The method of claim 10, And the MOS transistor is formed of a MOS in which only one of a source and a drain is formed in a triple P well, and a power supply voltage is applied to a gate electrode and a negative voltage is applied to the source or drain. The method of claim 13, And maintaining the triple P well in a floating state or connected to the drain and the source. The method of claim 10, The anti-fuse device may be configured to generate an anti-fuse device according to an output signal from the address multiplexer and a first and second control signals of the power-up reset circuit while a negative voltage is applied to one electrode of the anti-fuse device. A bias control unit for turning on or off a power supply voltage applied to the other electrode; And a latch unit for latching a program state of the fuse according to the first control signal and the third control signal of the power-up reset circuit. The method of claim 15, The bias control unit includes a NOR gate for logically combining an output signal from the address multiplexer and a first control signal from the power-up reset circuit; A switching element for switching a power supply voltage in accordance with an output signal of the NOR gate; A transistor element for passing a power supply voltage via the switching element to ground in accordance with a second control signal from the power up reset circuit; And a transistor element connected between the switching element and the power supply voltage applying terminal of the anti-fuse element and having a gate electrode grounded thereto. The method of claim 15, The latch unit includes a switching element for switching a power supply voltage in accordance with a third control signal from the power-up reset circuit; A first transistor connected between the switching element and the first node and turned on according to a first control signal from the power-up reset circuit; A second transistor connected between the first node and ground and having a gate electrode connected to a power supply voltage applying terminal of the antifuse device; And a latch circuit for latching the potential of the connection point of the switching element and the second transistor. A plurality of antifuse elements, each of which is composed of a MOS transistor, wherein a high voltage is supplied to a gate and a voltage lower than a power supply voltage to a source and a drain; A latch unit for detecting and latching a program state of the antifuse device; And And a redundancy block for replacing a defective cell with a redundancy cell according to the output of the latch unit. The method of claim 18, An address multiplexer for selecting the antifuse device; And a voltage generator for supplying the high voltage. The method of claim 18, And the MOS transistor comprises NMOS having a source and a drain formed in a triple P well. The method of claim 19, And maintaining the triple P well in a floating state or connected to the drain and the source. The method of claim 18, And the MOS transistor forms only one of a source and a drain in a triple P well, and applies a high voltage to a gate electrode and a voltage lower than a power supply voltage to the source or drain. The method of claim 21, And maintaining the triple P well in a floating state or connected to the drain or source. The method of claim 18, And the MOS transistor comprises a PMOS having a source and a drain formed in an N well of a P-type substrate. The method of claim 23, And the N well of the PMOS is floated. The method of claim 18, And the MOS transistor forms only one of a source or a drain in an N well of a P-type substrate, and a power supply voltage is supplied to a gate, and a negative voltage is supplied to one of the source or a drain, respectively. The method of claim 18, And the MOS transistor comprises an NMOS having a source and a drain formed in the P well. The method of claim 26, And the P well is floated. The method of claim 18, And the MOS transistor forms one of a source and a drain in a P well, and applies a high voltage to a gate and a voltage lower than a power supply voltage to a source or a drain, respectively. The method of claim 10, The antifuse circuit may include a source of the antifuse device according to an output signal from the address multiplexer and a first and fourth control signals of the power up reset circuit in a state where a high voltage is applied to a gate electrode of the antifuse device. A bias controller for turning on or off a voltage lower than a power supply voltage applied to the drain electrode; And a latch unit for latching a program state of the fuse in accordance with third and fourth control signals of the power-up reset circuit. The method of claim 29, The bias control unit may include a switching device for transmitting a power supply voltage to a first node according to the fourth control signal; A first transistor connected between the drain and source terminal connection node of the anti-fuse device and the first node and whose gate electrode is supplied with a power voltage; A second transistor connected between the first node and ground and turned on according to an output signal of the address multiplexer; And a third transistor connected in parallel with the second transistor and turned on according to the first control signal of the power-up reset circuit, but having a large on-resistance. The method of claim 29, The latch unit and a switching element for transmitting a power supply voltage to the first node in accordance with the third control signal; A first transistor connected between the first node and a second node and turned on according to the first control signal; A second transistor connected between the second node and ground and turned on according to a program state of the antifuse device; And a latch circuit for latching the potential of the first node.