KR100356472B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100356472B1 KR100356472B1 KR1020000085521A KR20000085521A KR100356472B1 KR 100356472 B1 KR100356472 B1 KR 100356472B1 KR 1020000085521 A KR1020000085521 A KR 1020000085521A KR 20000085521 A KR20000085521 A KR 20000085521A KR 100356472 B1 KR100356472 B1 KR 100356472B1
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- forming
- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 20
- 239000012535 impurity Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 게이트 상부에는 실리사이드막을 형성하고, 소오스 및 드레인 영역에는 실리사이드막을 형성하지 않음으로써 게이트 저항을 줄일 수 있고, 자기정렬 식각 공정으로 콘택홀을 형성한 후 도전층을 형성하더라도 오정렬에 의한 게이트와 소오스 및 드레인 영역의 도통을 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a silicide film is formed on a gate and a silicide film is not formed on a source and a drain region, thereby reducing gate resistance, and forming a contact hole through a self-aligned etching process. Even if the layer is formed, the conduction of the gate and the source and drain regions due to misalignment can be prevented, thereby providing a semiconductor device manufacturing method which can improve the reliability of the device.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 게이트 상부에는 실리사이드막을 형성하고, 소오스 및 드레인 영역에는 실리사이드막을 형성하지 않음으로써 게이트 저항을 줄일 수 있고, 자기정렬 식각 공정으로 콘택홀을 형성한 후 도전층을 형성하더라도 오정렬에 의한 게이트와 소오스 및 드레인 영역의 도통을 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a silicide layer is formed on a gate and a silicide layer is not formed on a source and a drain region, thereby reducing gate resistance and forming a contact hole through a self-aligned etching process. Even if the conductive layer is formed, it is possible to prevent conduction between the gate and the source and drain regions due to misalignment, and to improve the reliability of the device.
반도체 소자의 고집적화 및 소형화에 따라 그에 적용되는 트랜지스터의 크기도 작아지고 있다. 이러한 트랜지스터의 게이트 저항을 낮추기 위해 게이트로 사용되는 폴리실리콘 상부에 실리사이드를 형성하는 방법을 사용하고 있다. 그러나, 이 방법은 게이트 뿐만 아니라 소오스 및 드레인 영역에도 실리사이드가 형성된다. 이와 같이 소오스 및 드레인 영역에도 실리사이드가 형성되면 오정렬을 고려하여 게이트와 소오스 및 드레인 영역 사이를 어느 정도 간격으로 이격시켜야 한다. 즉, 후속 공정으로 층간 절연막을 형성한 후 소오스 및 드레인 영역을 노출시키는 콘택홀을 형성할 때 오정렬에 의해 게이트도 노출될 수 있다. 이 경우 콘택홀을 매립시키는 도전층을 형성할 때 게이트와 소오스 및 드레인 영역이 도통된다. 상기와 같은 문제점은 게이트로 사용되는 폴리실리콘막 상부에 질화막과 같은 식각 정지막을 형성하면 해결할 수 있다. 그러나, 폴리실리콘막 상부에 식각 정지막을 형성할 경우 실리사이드를 형성할 수 없기 때문에 게이트 저항을 낮출 수가 없게 된다.As the integration and miniaturization of semiconductor devices increase, the size of transistors applied thereto is also decreasing. In order to lower the gate resistance of the transistor, a method of forming silicide on top of polysilicon used as a gate is used. However, this method forms silicides in the source and drain regions as well as the gates. As described above, when silicide is formed in the source and drain regions, the gate and the source and drain regions must be spaced apart at some intervals in consideration of misalignment. That is, the gate may also be exposed by misalignment when forming the contact hole exposing the source and drain regions after forming the interlayer insulating film in a subsequent process. In this case, the gate, the source, and the drain region are conductive when forming the conductive layer filling the contact hole. The above problem can be solved by forming an etch stop layer such as a nitride layer on the polysilicon layer used as a gate. However, when the etch stop layer is formed on the polysilicon layer, the silicide cannot be formed, and thus the gate resistance cannot be lowered.
이와는 반대로 폴리실리콘 실리사이드 공정을 실시하지 않으면 자기정렬 식각 공정으로 콘택홀을 형성할 때 게이트와 소오스 및 드레인 영역사이를 소정 간격 이격시키지 않아도 된다. 이 때문에 소자의 크기는 상당히 줄일 수 있지만, 실리사이드 공정을 실시한 구조에 비해 저항이 상당히 증가하게 되어 소자의 신뢰성은 크게 저하된다.On the contrary, when the polysilicon silicide process is not performed, the gate, source, and drain regions do not have to be spaced apart from each other when the contact hole is formed by the self-aligned etching process. As a result, the size of the device can be considerably reduced, but the resistance is considerably increased compared to the structure in which the silicide process is performed, and the reliability of the device is greatly reduced.
본 발명의 목적은 게이트 저항을 줄일 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.An object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the gate resistance.
본 발명의 다른 목적은 게이트 상부에는 실리사이드가 형성되고, 소오스 및 드레인 영역에는 실리사이드가 형성되지 않도록 함으로써 게이트와 소오스 및 드레인 영역의 도통을 방지할 수 있는 반도체 소자의 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing conduction between the gate and the source and drain regions by forming silicide on the gate and preventing the silicide from being formed in the source and drain regions.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 제조 방법을 설명ㅇ하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to illustrate a method of manufacturing a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 폴리실리콘막 14 : 제 1 절연막13 polysilicon film 14 first insulating film
15 : 스페이서 16 : 접합 영역15 spacer 16 junction region
17 : 제 2 절연막 18 : 실리사이드막17 second insulating film 18 silicide film
19 : 제 3 절연막 20 : 제 4 절연막19: third insulating film 20: fourth insulating film
21 : 콘택홀21: contact hole
본 발명에 따른 반도체 소자의 제조 방법은 반도체 기판 상부에 게이트 산화막, 폴리실리콘막 및 제 1 절연막을 순차적으로 형성한 후 이들을 패터닝하여 게이트 패턴을 형성하는 단계와, 상기 게이트 패턴 측벽에 스페이서를 형성한 후 상기 반도체 기판상에 접합 영역을 형성하는 단계와, 전체 구조 상부에 제 2 절연막을 형성한 후 연마하여 상기 제 1 절연막을 노출시키는 단계와, 상기 제 1 절연막을 제거한 후 노출된 상기 폴리실리콘막 상부에 실리사이드막을 형성하는 단계와, 전체 구조 상부에 제 3 절연막을 형성한 후 연마 공정을 실시하여 상기 제 2 절연막을 노출시키는 단계와, 전체 구조 상부에 제 4 절연막을 형성한 후 상기 제 4 및 제 2 절연막의 소정 영역을 자기정렬 식각 공정으로 제거하여 상기 접합 영역을 노출시키는 콘택홀을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In the method of manufacturing a semiconductor device according to the present invention, a gate oxide film, a polysilicon film, and a first insulating film are sequentially formed on a semiconductor substrate, and then patterned to form a gate pattern, and a spacer is formed on the sidewall of the gate pattern. Forming a junction region on the semiconductor substrate, forming and polishing a second insulating film over the entire structure to expose the first insulating film, and removing the first insulating film and then exposing the polysilicon film. Forming a silicide film on the upper surface, forming a third insulating film on the entire structure, and then performing a polishing process to expose the second insulating film, and forming a fourth insulating film on the entire structure, Removing a predetermined region of the second insulating layer by a self-aligned etching process to form a contact hole exposing the junction region; Characterized in that it comprises a step.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 게이트 산화막(12), 폴리실리콘막(13) 및 제 1 절연막(14)을 순차적으로 형성한다. 제 1 절연막(14), 폴리실리콘막(13) 및 게이트 산화막(12)의 소정 영역을 식각하여 게이트 패턴을 형성한다. 저농도 불순물 이온 주입 공정을 실시하여 반도체 기판(11)상에 저농도 불순물 영역을 형성한다. 게이트 패턴 측벽에 스페이서(15)를 형성한 후 고농도 불순물 이온 주입 공정을 실시하여 고농도 불순물 영역을 형성한다. 이에 의해 LDD 구조의 접합 영역(16)이 형성된다. 전체 구조 상부에 제 2 절연막(17)을 형성한다.Referring to FIG. 1A, the gate oxide film 12, the polysilicon film 13, and the first insulating film 14 are sequentially formed on the semiconductor substrate 11. Predetermined regions of the first insulating layer 14, the polysilicon layer 13, and the gate oxide layer 12 are etched to form a gate pattern. A low concentration impurity ion implantation process is performed to form a low concentration impurity region on the semiconductor substrate 11. After the spacers 15 are formed on the gate pattern sidewalls, a high concentration impurity ion implantation process is performed to form a high concentration impurity region. As a result, the junction region 16 of the LDD structure is formed. The second insulating film 17 is formed over the entire structure.
도 1(b)를 참조하면, 제 2 절연막(17)을 연마하여 제 1 절연막(14)을 노출시킨다. 노출된 제 1 절연막(14)을 제거하여 폴리실리콘막(13)을 노출시킨다. 전체 구조 상부에 Ti 또는 Co등을 증착한 후 열처리 공정을 실시하여 폴리실리콘막(13) 상부에 실리사이드막(18)을 형성한다. 그리고, 전체 구조 상부에 제 3 절연막(19)을 형성한 후 연마 공정을 실시하여 제 2 절연막(17)과 같이 평탄화한다.Referring to FIG. 1B, the second insulating layer 17 is polished to expose the first insulating layer 14. The exposed first insulating film 14 is removed to expose the polysilicon film 13. After depositing Ti or Co on the entire structure, a heat treatment process is performed to form the silicide layer 18 on the polysilicon layer 13. After the third insulating film 19 is formed over the entire structure, a polishing process is performed to planarize like the second insulating film 17.
도 1(c)를 참조하면, 전체 구조 상부에 제 4 절연막(20)을 형성한다. 그리고, 제 4 절연막(20) 및 제 2 절연막(17)의 소정 영역을 자기정렬 식각 공정으로 제거하여 접합 영역을 노출시키는 콘택홀(21)을 형성한다.Referring to FIG. 1C, a fourth insulating film 20 is formed on the entire structure. Then, the predetermined regions of the fourth insulating film 20 and the second insulating film 17 are removed by a self-aligned etching process to form a contact hole 21 exposing the junction region.
상술한 바와 같이 본 발명에 의하면 게이트 상부에는 실리사이드막을 형성하고, 소오스 및 드레인 영역에는 실리사이드막을 형성하지 않음으로써 게이트 저항을 줄일 수 있다. 또한, 자기정렬 식각 공정으로 콘택홀을 형성한 후 도전층을 형성하더라도 오정렬에 의한 게이트와 소오스 및 드레인 영역의 도통을 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, the gate resistance can be reduced by forming the silicide layer on the gate and the silicide layer on the source and drain regions. In addition, even when the conductive layer is formed after the contact hole is formed by the self-aligned etching process, conduction between the gate, the source, and the drain region due to misalignment can be prevented, thereby improving the reliability of the device.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01264357A (en) * | 1988-04-15 | 1989-10-20 | Hitachi Ltd | Data terminal system for integrated service digital network |
| KR19990031569A (en) * | 1997-10-13 | 1999-05-06 | 윤종용 | Selective silicide formation method |
| KR20000013839A (en) * | 1998-08-13 | 2000-03-06 | 윤종용 | Semiconductor device and method for forming thereof |
| KR20020015165A (en) * | 2000-08-21 | 2002-02-27 | 윤종용 | Method of semiconductor device using salicidation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01264357A (en) * | 1988-04-15 | 1989-10-20 | Hitachi Ltd | Data terminal system for integrated service digital network |
| KR19990031569A (en) * | 1997-10-13 | 1999-05-06 | 윤종용 | Selective silicide formation method |
| KR20000013839A (en) * | 1998-08-13 | 2000-03-06 | 윤종용 | Semiconductor device and method for forming thereof |
| KR20020015165A (en) * | 2000-08-21 | 2002-02-27 | 윤종용 | Method of semiconductor device using salicidation |
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