KR100356476B1 - Method of forming a inter-metal dielectric layer in a damascene process - Google Patents

Abstract

The present invention relates to a method of forming an interlayer dielectric (IMD) in a damascene process of a semiconductor device, and due to the high thickness of a conventional interlayer dielectric, the integration of the device is reduced and the RC delay is increased during the operation of the device. In order to solve the problem, by forming an intermetallic insulating film in a stacked structure of a silicon oxide film and a fluorinated amorphous carbon layer (aF; C), it is possible to have a low dielectric constant without increasing the thickness of the intermetallic insulating film, fluorinated amorphous Since the carbon layer serves as an etch stop layer, a method of forming an intermetallic insulating film is disclosed in a damascene process of a semiconductor device capable of further simplifying the damascene process and at the same time improving the degree of integration of the device.

Description

Method of forming a inter-metal dielectric layer in a damascene process

The present invention relates to a method for forming an interlayer insulating film in a damascene process of a semiconductor device.

As the degree of integration of semiconductor devices increases, the patterning process of fine metal interconnections becomes difficult. Accordingly, a damascene process, which can easily form fine metal interconnect patterns, is applied. However, the damascene process has an advantage of easily forming a fine metallization pattern, but a problem of causing device defects and lowering the density due to the compressive stress and high thickness of the silicon oxide film used as the interlayer insulating film. have.

1 is a cross-sectional view of a device illustrated to explain a method for forming an interlayer insulating film in a damascene process of a conventional semiconductor device.

First, the first silicon to be used as an etch stop layer in the wiring pattern is formed on the inter-silicon insulating film 12 on the semiconductor substrate 11 on which various elements for manufacturing a semiconductor device are formed. The nitride film 13 is formed. Thereafter, selected portions of the first silicon nitride layer 13 and the polysilicon insulating layer 12 are etched to form the metal contact 14, and the conductive material is embedded only in the metal contact 14 by a conductive material deposition and polishing process. Be sure to Next, the first metal wiring 15 is patterned by forming a first metal wiring material on the entire structure and patterning the first metal wiring material to be in contact with the portion where the metal contact 14 is formed. A first silicon interlayer insulating film 16 and a second silicon nitride film 17 used as an etch stop layer are formed on the entire structure. Next, the selected portions of the second silicon nitride film 17 and the first interlayer insulating film 16 are etched to form a via contact 18 through which a portion of the upper surface of the first metal wire 15 is exposed. Thereafter, the via contact 18 is filled with the conductive material through a conductive material deposition and polishing process, and the second interlayer insulating film 20 is formed on the entire structure. Then, the selected portion of the second interlayer insulating film 20 is etched to expose the via contact 18, and then a metal material is deposited and polished to form the second metal wiring 19.

When the damascene process is performed in this manner, the phenomenon of lifting (A) of the interlayer insulating film occurs due to the high compressive stress of the silicon oxide film used as the interlayer insulating films 16 and 20, or the metal wiring sidewalls. There is a problem that the void (B) occurs in. In addition, the silicon nitride film is deposited as an etch stop layer between the intermetallic insulating films (between 16 and 20), and the silicon nitride film has a high dielectric constant, which causes a problem of RC delay during device operation. Because of this problem, it is difficult to form an etching target reproducibly when the silicon nitride film is not deposited, and when an misalignment occurs, the interlayer insulating film is etched due to the difference in the etching rate between the metal wiring and the interlayer insulating film, thereby making it difficult to proceed with the subsequent process. In addition, an additional process for forming a silicon nitride film degrades the characteristics of the damascene process, which is advantageous for process simplification. Due to the high dielectric constant of the silicon oxide film used as the interlayer insulating film, as the target thickness of the interlayer insulating film is 5000 Å or more, the size of the via contact is reduced, which increases the aspect ratio, making it difficult to fill the via contact. .

Accordingly, the present invention provides a dual layer structure of an oxide film and an fluorinated amorphous carbon layer in the damascene process of a semiconductor device, thereby achieving a high integration of the device in a simple process. The purpose is to provide a formation method.

In the damascene process of a semiconductor device according to the present invention for achieving the above object, a method of forming an interlayer metal interlayer insulating film between the fine metal wiring patterns formed by the damascene process is a laminated structure of a silicon oxide film and an fluorinated amorphous carbon layer. Characterized in that formed.

1 is a cross-sectional view showing a device for explaining a method for forming an interlayer insulating film in a damascene process of a conventional semiconductor device.

2A to 2C are cross-sectional views of devices sequentially shown to explain a method of forming an interlayer insulating film in a damascene process of a semiconductor device according to the present invention.

Figure 3 is a graph showing the stress characteristics according to the temperature of the high density plasma oxide film.

4A and 4B are graphs showing changes in stress characteristics and dielectric constants according to the deposition gas flow rate of the fluorinated amorphous carbon layer.

<Description of the symbols for the main parts of the drawings>

21 semiconductor substrate 22 polysilicon interlayer insulating film

23: metal contact 24: the first metal wiring

25: first interlayer insulating film 26: via contact

27: second metal wiring 28: second metal interlayer insulating film

29: passivation film 22A, 25A: silicon oxide film

22B, 25B, 29A: Fluorinated amorphous carbon layer (a-F: C)

29B: Silicon Nitride Film

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2C are cross-sectional views of devices sequentially illustrated to explain a method for forming an interlayer insulating film in a damascene process of a semiconductor device according to the present invention.

As shown in FIG. 2A, an inter-silicon interlayer insulating film 22 is formed on a semiconductor substrate 21 on which various elements for manufacturing a semiconductor device are formed. The inter-silicon interlayer insulating film 22 is formed of a laminated structure of a first silicon oxide film 22A having a compressive stress and a first Fluorinated Amorphous Carbon (aF; C) layer 22B having a tensile stress or a BPSG film. To form. Here, the fluorinated amorphous carbon layer 22B is formed by using C ₄ F ₈ and CH ₄ or CF ₄ and CH ₄ as the deposition source gas, and the dielectric constant is low by using only high power or by controlling the high power and low power ratio during deposition. Have tensile stress. When CH ₄ : C ₄ F ₈ = 1: 6 and the flow rate of C ₄ F ₈ is 0.2 to 1.0 slm, the fluorinated amorphous carbon layer 22B having high tensile stress and dielectric constant can be formed.

In addition, the first silicon oxide film 22A is formed using a high density plasma USG (HDP USG), and boron or phosphorus ions are implanted to lower the dielectric constant of the silicon oxide film. Subsequently, the selected portion of the inter-silicon insulating layer 22 is etched to form the metal contact 23, and the conductive material is embedded in the metal contact 23 through the process of layering and polishing the conductive material. Next, a metal material is deposited on the entire structure and patterned to be in contact with the metal contact 23 to form the first metal wiring 24. Here, the first interlayer insulating film 25 is formed immediately after the inter-silicon insulating film 22 is formed, and a dual damascene process of simultaneously forming a metal contact 23 and a trench in which the metal wiring is to be formed is performed. It is also possible.

As shown in FIG. 2B, a second silicon oxide film 25A is formed on the entire structure and a polishing process is performed to expose the top surface of the first metal wiring 24. Thereafter, after forming the second fluorinated amorphous carbon layers aF: C and 25B, the selected region is etched to form a via contact 26 through which a portion of the upper surface of the first metal wire 24 is exposed. Here, the stacked structure of the second silicon oxide film 25A and the second fluorinated amorphous carbon layer 25B serves as the first interlayer insulating film 25, wherein the silicon oxide film has a compressive stress and the fluorinated amorphous carbon layer is tensile Because of the stress, the mutual stresses are canceled out. In addition, since the fluorinated amorphous carbon layer has a low dielectric constant of less than 2, even if the thickness of the intermetallic insulating film 25 is thinned, the insulating properties can be increased, and the RC delay during operation of the device can be minimized. The second fluorinated amorphous carbon layer 25B is formed using C ₄ F ₈ and CH ₄ or CF ₄ and CH _4, and uses only high power during deposition or adjusts the ratio of high power and low power to have low dielectric constant and tensile stress. . When CH ₄ : C ₄ F ₈ = 1: 6 and the flow rate of C ₄ F ₈ is 0.2 to 1.0 slm, the fluorinated amorphous carbon layer 22B having high tensile stress and dielectric constant can be formed.

In the deposition of the second silicon oxide film 25A, boron (B) or phosphorus (P) ions are implanted to lower the dielectric constant of the silicon oxide film.

As shown in FIG. 2C, the second interlayer insulating film 28 is formed on the entire structure in which the via contact 26 is formed using the silicon oxide film, and the second interlayer insulating film is exposed to expose the upper portion of the via contact 26. Etch (28). In this case, since the lower fluorinated amorphous carbon layer 25B serves as an etch stop layer, it is not necessary to form a separate etch stop film before forming the second interlayer insulating film 28. The second interlayer insulating film 28 is formed so as to maximize the voids by using a PECVD silicon oxide film having poor step coverage characteristics. This is to facilitate formation of a trench for subsequent second metallization. Thereafter, the second metal wirings 27 are formed through a metal material deposition and polishing process. Then, a passivation film 29 having a laminated structure of a third fluorinated amorphous carbon layer 29A having a tensile stress and a third silicon oxide film 29B having a compressive stress is formed on the entire structure.

As described above, when the intermetallic insulating film is formed in the damascene process with the laminated structure of the silicon oxide film having the compressive stress and the aF: C layer having the tensile stress, the stresses of the interlayer insulating film due to the opposing stresses between the stacked films Will be offset. In addition, since the a-F: C layer has a low dielectric constant of 2 or less, it is not necessary to form a thick interlayer insulating film for low dielectric properties, thereby improving the degree of integration of the device. In addition, since the a-F: C layer serves as an etch stop layer in a trench forming process for forming metal wiring, there is no need to form a separate etch stop layer. This makes it possible to achieve a higher integration of the device while proceeding with the damascene process more simply.

3 is a graph showing the stress characteristics according to the temperature of the high density plasma oxide film, and shows the case of the high density plasma USG film. As shown, the HDP-USG film has a low compressive stress at room temperature, but has a higher compressive stress as the temperature increases.

4A and 4B are graphs showing changes in stress characteristics and dielectric constants according to the deposition gas flow rate of the fluorinated amorphous carbon layer. As the deposition power, dual frequency power (high frequency power and low frequency power) is used, and the deposition temperature is 250 ° C. Examples of the source gas include C ₄ F ₈ and CH ₄ .

As shown in Figure 4a, it can be seen that as the flow rate ratio of C ₄ F ₈ and CH ₄ increases, the stress of the fluorinated amorphous carbon layer is transferred to the tensile stress. With a flow rate ratio of 6, when the flow rate ratio is less than 6, the fluorinated amorphous carbon layer has a stable state, but when the flow rate ratio is 6 or more, the tensile stress is intensified, resulting in an unstable film state. By using a single frequency power (high frequency power) as the deposition power, it is possible to obtain a fluorinated amorphous carbon layer having tensile stress in a region where the ratio of C ₄ F ₈ is lower than in the graph shown.

Figure 4b is a graph showing the dielectric constant change over during the deposition and the flow rate of the annealing after the C ₄ F ₈ and CH ₄ of the fluorinated amorphous carbon layer, the portion changed from the stable state to the unstable state C ₄ F ₈ and the flow ratio of CH ₄ It can be seen that if the value of 6 or more has a low dielectric constant.

As described above, the present invention uses a layered structure of a silicon oxide film and a fluorinated amorphous carbon (aF: C) layer having a low dielectric constant when forming an intermetallic insulating film in a damascene process of a semiconductor device. It is possible to form an insulating film having a low dielectric constant without increasing the film thickness. Accordingly, the RC delay problem may be solved due to the increase in the thickness of the interlayer insulating film. In addition, since the a-F: C layer also serves as an etch stop layer during the trench forming process for forming the metal wiring, there is no need to form a separate etch stop layer, thereby simplifying the process and facilitating high integration.

Claims (5)

In the damascene process for forming a fine metallization pattern of a semiconductor device, The interlayer insulating film between the fine metallization patterns is formed in a stacked structure of a silicon oxide film and an fluorinated amorphous carbon layer, and the fluorinated amorphous carbon layer is formed of C ₄ F ₈ and CH ₄ or CF ₄ having a mixing ratio of 1: 6. A method of forming an interlayer insulating film in a damascene process of a semiconductor device, characterized in that formed of CH ₄ . The method of claim 1, The silicon oxide film is a high density plasma USG film, characterized in that the interlayer insulating film forming method in the damascene process of the semiconductor device. The method of claim 1, The silicon oxide film is formed by implanting boron or phosphorus ions in the damascene process of the semiconductor device. delete The method of claim 1, The C ₄ F ₈ supply amount is 0.2 to 1.0 slm, the interlayer insulating film forming method in the damascene process of the semiconductor device.