KR100341577B1 - A QFCB siganl generator in memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor technology, and more particularly, to high-speed operating memory, such as DDR double data rate synchronous dynamic random access memory (SDRAM), and more particularly to a module configured to provide a common data bus. A memory device to be used. It is an object of the present invention to provide a QFCB signal generation circuit that is enabled only while data is input according to the burst length, and operates quickly and accurately even when an interrupt or write command is continuously (without delay). The present invention implements a QFCB signal generation circuit that forms a window as much as the timing at which data is inputted and outputted by using a counter composed of an internal shift register during a write command.

Description

Data switch control signal generation circuit of a memory device {A QFCB siganl generator in memory device}

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor technology, and more particularly, to high-speed operating memory, such as DDR double data rate synchronous dynamic random access memory (SDRAM), and more particularly to a module configured to provide a common data bus. A circuit for generating a data switch control signal (QFCB, DQ FET Control Bar) of a memory device to be used.

In the memory module, as shown in FIG. 1, a plurality of memory chips 11 are configured on one board 10 and data buses are commonly used. That is, the data bus is commonly connected to each memory chip 11.

At this time, a chip other than a chip selected and operated through the memory controller 12 and the chip select bus, that is, a chip which does not perform a read or write operation, is also connected to the data bus in common, and thus the data output buffer of the chip. They also act as a load on this common data bus. Therefore, in such a case, the load of the data bus is particularly large in a high-speed memory having a high operating frequency.

In order to solve this problem, as shown in FIG. 2, a data switch (S / W) 23 is employed between the common data bus and each memory chip 21 to perform data input / output operations in a read / write operation. A method of reducing the load of the common data bus by turning on only the data S / W 23 of the performing chip has been proposed. Reference numeral 22 denotes a memory controller.

At this time, a signal controlling the on / off operation of the data S / W 23 is a QFCB signal generated in the memory chip 21. The signal is enabled at a logic level low only while data is inputted and outputted, thereby causing a data window. Form a (data window).

3 is a timing diagram of a QFCB signal according to a burst length. The QFCB signal is a signal that operates with respect to data at the time of reading or writing, but will be described based only on the writing operation. do.

During a write operation, the QFCB signal must be enabled by the write command and disabled at the last data at the end of the data input. In this case, it is important to note that the QFCB signal is enabled while each data is input according to the burst length. Also, if the previous write command is interrupted by another command in the middle of data input and the data input stops, the QFCB signal is accordingly. It must be disabled. Also, if another write command is entered without a write after the write command, QFCB should not be disabled until the data entered by the second write command is received.

However, since the QFCB signal is recommended by JEDEC and a generation circuit that satisfies the above requirement has not yet been proposed, the conventional DRAM has not used the QFCB signal.

SUMMARY OF THE INVENTION The present invention provides a QFCB signal generation circuit for enabling a QFCB signal that is enabled only while data is input according to the burst length, and operates quickly and accurately even when an interrupt or write command is continuously received (without delay). have.

1 is a block diagram of a conventional memory module.

2 is a block diagram of an improved memory module.

3 is a timing diagram of a QFCB signal according to a burst length.

4 is a block diagram of a QFCB generation circuit according to an embodiment of the present invention.

5A is a block diagram of the write qfcb on / off block 40 of FIG.

5B is a circuit diagram of the QFC pu / pd block 42 of FIG.

5C is an illustration of the output driver 44 of FIG. 4.

Fig. 5D is a timing diagram of the signal shown in Figs. 4 and 5A to 5C.

6 is a circuit diagram of the wtqfc_inc block 50 of FIG.

7 is a timing diagram of a write qfc enable signal according to the shift counter output wt0, wt1, wt2, wt3 and burst length of FIG.

8 is a detailed circuit diagram of the wtqfc_inc block shown in FIG. 6;

9 is a detailed circuit diagram of the wt_qfcenb block 52 of FIG.

* Explanation of symbols for the main parts of the drawings

40: write qfcb on / off block

42: QFC pu / pd block

44: output driver

In order to achieve the above technical problem, the present invention provides a data switch control signal generation circuit for selectively switching electrical connections between a common data bus of a memory module having a plurality of memory chips and each memory chip, the clock signal and A plurality of shift counting means for shift counting the control write command signal to the reset signal; QFCB enable signal generation means for enabling the data switch control signal (QFCB) by a set burst length in a section in which write data is input through a logical operation of an output of each of the plurality of shift counting means; Output drive signal generating means for generating a pull-down drive signal and a pull-up drive signal by inputting the QFCB enable signal; And output driving means for controlling the pull-down driving signal and the pull-up driving signal and outputting the QFCB. The present invention also provides a common data bus of a memory module including a plurality of memory chips and a plurality of memory chips. A data switch control signal (QFCB) generation circuit for selectively switching electrical connections, wherein the data switch control signal (QFCB) is set by a burst length set in a section in which write data is input under control of a clock signal, a reset signal, and a write command signal. QFCB enable signal generation means for enabling a; Output drive signal generating means for generating a pull-down drive signal and a pull-up drive signal by inputting the QFCB enable signal; And output driving means for outputting the QFCB under control of the pull-down driving signal and the pull-up driving signal. That is, the present invention provides a timing at which data is inputted and outputted using a counter configured with an internal shift register during a write command. A QFCB signal generation circuit is formed which forms as many windows as follows. Hereinafter, preferred embodiments of the present invention will be described in order to enable those skilled in the art to more easily implement the present invention. Shall be.

4 is a block diagram of a QFCB generation circuit according to an exemplary embodiment of the present invention, and includes a write qfcb for generating a write qfc enable signal wt_qfcenb for enabling the QFCB signal by a necessary period during a write command. QFC outputting pull up / pull down drive signals pd and pu by inputting on / off block 40 and write qfc enable signal wt_qfcenb output from write qfcb on / off block 40 as input. pu / pd block 42 and an output driver 44 which is controlled by the pu and pd signals output from the QFC pu / pd block 42 and outputs a QFCB signal.

5A illustrates a block configuration of the write qfcb on / off block 40 of FIG. 4, wherein the write qfcb on / off block 40 performs an external clock clk, reset pulse reset, and write command signal wt_cmd. A shift counting value wt0, wt1, wt2, and wt4 that increments and shifts every cycle of the external clock clk as an input, and an output wt0, wt1, wt2 of the wtqfc_inc block 50; , wt4 is inputted into a wt_qfcenb block 52 that outputs the write qfc enable signal wt_qfcenb as an input.

Here, the write command signal wt_cmd is a pulse generated by the command decoder when a write command is received in synchronization with a rising edge of the clock from the outside, and the reset signal is a burst stop command or precharge. This pulse is input when the write operation is interrupted by the (precharge) command.

Meanwhile, as illustrated in FIG. 5B, the QFC pu / pd block 42 of FIG. 4 includes an inverter I50 that inverts the write qfc enable signal wt_qfcenb and outputs the pull-down driving signal pd, and the write qfc. The pulse generator 54 outputs the pull-up drive signal pu with the enable signal wt_qfcenb as an input. The pulse generator 54 includes a plurality of inverters I51, I52, and I53 for delaying the write qfc enable signal wt_qfcenb by a predetermined time, and a NAND gate I54 for inputting the output and the write qfc enable signal wt_qfcenb of the inverter I53. ) And an inverter I55 that inverts the output of the NAND gate I54 and outputs the pull-up driving signal pu.

5C illustrates the output driver 44 of FIG. 4, a pull-up PMOS transistor P1 having a pull-up drive signal pu as a gate input and a pull-down NMOS transistor N1 having a pull-down drive signal pd as a gate input. It consists of).

FIG. 5D is a timing diagram of the signal shown in FIGS. 4 and 5A to 5C. The operation of the QFCB generation circuit will be briefly described with reference to the following.

First, when the write qfc enable signal wt_qfcenb, which forms a data input window of the burst length, is enabled low, the output QFCB of the output driver 44 outputs the pd signal high in the QFC pu / pd block 42. The transition to the low level in the impedance (Hi-Z) state. In this state, if the write qfc enable signal wt_qfcenb is disabled, the pulse generator 44 of the QFC pu / pd block 42 generates the pu signal as a short pulse, which causes the QFCB signal to be disabled at a high level and then immediately becomes a high impedance ( Hi-Z) state.

6 is a block diagram of the wtqfc_inc block 50 of FIG. 5A. The wtqfc_inc block 50 may include a first shift counter for receiving a reset pulse reset and an external clock clk. 60), a second shift counter 61 for outputting wt1 by inputting wt0 of the first shift counter 60, a third shift counter 62 for outputting wt2 by input of wt1, and wt2 Is configured as a fourth shift counter 63 for outputting wt3.

The timing of the write qfc enable signal according to the output wt0, wt1, wt2, wt3 and the burst length of each shift counter is shown in FIG. When the write command signal wt_cmd is input first, wt0 is enabled, wt1 is enabled by the next clock clk, and wt0 is disabled. Then at clock clk wt2 is enabled and wt1 is disabled, and this operation is repeated every clock clk until the last wt3 is disabled. When the burst length is set to 2 (BL2) in the mode register set (or extended mode register set), the write qfc enable signal wt_qfcenb corresponds to the inverse of the wt0 signal, and when the burst length is 4 (BL4) the wt_qfcenb signal Is made through the NAND of wt0 and wt1, and when the burst length is 8 (BL8), the wt_qfcenb signal is generated through the NAND of wt0, wt1, wt2, wt4.

Specific logic for generating wt0, wt1, wt2, wt4 signals and wt_qfcenb signals is illustrated in the accompanying drawings, FIGS. 8 and 9.

8 is a diagram illustrating a detailed circuit configuration of the wtqfc_inc block shown in FIG. 6. First, the first shift counter 60 includes a pull-up PMOS transistor P5 having a write command signal wt_cmd as a gate input; A driver 80 composed of a pull-down NMOS transistor N2, a PMOS transistor P1 having a gate input as a reset clock rst_clk generated using an external clock clk as a source, and a latch composed of two inverters I7 and I8 ( 81).

The reset clock rst_clk is an inverter I68 for inverting the external clock clk, inverters I69, I72, and I73 for delaying the output of the inverter I68 for a predetermined time, and outputs of the inverters I68 and I73. A signal produced by the clock generator 86 composed of the NAND gate I162 as an input, is employed to reset the counting value on the falling edge of the external clock clk after the write command signal wt_cmd is enabled.

Meanwhile, the second shift counter 61 includes an inverter I13 and a transmission gate T12 so that when the external clock clk is at a high level, that is, on the rising edge of the clock, the first switching unit 82 passes the wt0. ), A first latch portion 83 composed of a NAND gate I79 and inverters I21 and I17 for inputting an output of the first switching portion 82 and a reset pulse reset, and an inverter I19 and a transmission gate. A second switching unit 84 and a second switching unit 84 that operate at the falling edge of the clock to pass the output of the first latch unit 83 when the external clock clk is at a low level. And a second latch portion 85 composed of a NAND gate I81 and an inverter I22 and I20 for inputting the output of the reset pulse reset and the reset pulse reset. The output of the second latch portion 85 is an inverter I48, It is outputted as a wt1 signal through I47).

Since the configurations of the third shift counter 62 and the fourth shift counter 63 are the same as those of the above-described second shift counter 61, description thereof will be omitted. Unexplained reference numerals T41, T23, T33, T28 are transmission gates, I83, I85, I87, I89 are NAND gates, I40, I23, I44, I24, I26, I25, I45, I46, I37, I27, I34, I32, I28, I31, I50, and I49 represent inverters, respectively.

9 is a diagram illustrating a detailed circuit configuration of the wt_qfcenb block 52 of FIG. 5, and is composed of a NAND logic unit 90, a driver 91, and a latch 92.

The NAND logic unit 90 inputs a NAND gate I209 which receives the wt1 signal and the bl2 signal inverted through the inverter I188, an output of the NAND gate I209, and an inverted wt0 through the inverter I186. NAND gate I192 to be used, NAND gate I210 to input wt2 signal and bl2 signal, NAND gate I211 to input wt3 signal and bl8 signal, NAND gate I210 and NAND gate ( A NAND gate I193 having the output of I211 as an input, and a NOR gate I194 having the output of the NAND gate I192 and the NAND gate I193 as input.

The bl2, bl4 and bl8 signals are defined in Table 1 below.

BL2 BL4 BL8 bl2 H L L bl4 L H L bl8 L L H

In the logic shown in FIG. 9, the bl4 signal is not used because the bl4 signal can be represented by the bl2 and bl8 signals as shown in Table 1 above.

As a result, the NAND logic unit 90 blocks signals except for the wt0 signal when the burst length is 2, blocks wt2 and wt3 when the burst length is 4, and gives out wt0 and wt1 when the burst length is 8, wt0, N1 wt1, wt2, and wt3.

The driver 91 has a pull-up PMOS transistor P101 and a pull-down NMOS transistor N100 having the output of the NAND logic unit 90 as a gate input, and a pull-up PMOS having the wt0 signal inverted through the inverter I197 as a gate input. A transistor P196 and an NMOS transistor N99 for synchronizing the timing at which the write qfc enable signal wt_qfcenb is disabled to the external clock clk with the external clock clk as the gate input.

The latch portion 92 is composed of two inverters I105 and I104.

As described above, the QFCB signal generating circuit of the present invention can form a QFCB signal that forms a window corresponding to the timing at which data is inputted and outputted according to the burst length, and when a write operation is interrupted by a burst stop command or a precharge command. In other words, when the reset pulse reset occurs, wt0, wt1, wt2, wt3 are all disabled low to reset the write qfc enable signal wt_qfcenb, and when the write command comes in continuously (without delay), it is re-enabled from wt0. Because it performs grounding, the wt_qfcenb signal can be operated continuously without being disabled.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

For example, in the above-described embodiment, the case where the external clock is supplied to the clock stage of the shift counter has been described as an example. However, the present invention can also be applied to the case of using a DLL (Delayed-Interlock Loop) clock or an internal clock. have.

In addition, in the above-described embodiment, the case where NAND logic is used in the wt_qfcenb block has been described as an example. However, it is also possible to combine the signals using other logic.

The above-described present invention can generate a QFCB signal accurately and quickly in a memory operating at a high speed, and by employing such a QFCB signal in the memory, it is possible to reduce the load of the data bus outside the chip.

Claims (13)

A data switch control signal generation circuit for selectively switching electrical connections between a common data bus of a memory module having a plurality of memory chips and each memory chip, A plurality of shift counting means for shift counting a control write command signal to a clock signal and a reset signal; QFCB enable signal generation means for enabling the data switch control signal (QFCB) by a set burst length in a section in which write data is input through a logical operation of an output of each of the plurality of shift counting means; Output drive signal generating means for generating a pull-down drive signal and a pull-up drive signal by inputting the QFCB enable signal; And Output driving means for outputting the QFCB under control of the pull-down driving signal and the pull-up driving signal; Data switch control signal generation circuit of the memory device comprising a. The method of claim 1, The plurality of shift counting means, A first shift counter configured to receive the write command signal under control of the clock signal and the reset signal; A second shift counter configured to receive the output of the first shift counter under control of the clock signal and the reset signal; A third shift counter controlled by the clock signal and the reset signal to receive an output of the second shift counter; And And a fourth shift counter configured to receive the output of the third shift counter under the control of the clock signal and the reset signal. The method of claim 1, The output drive signal generating means, Inverting means for inverting the QFCB enable signal to output the pull-down driving signal; And pulse generating means for outputting the pull-up drive signal at the rising edge of the QFCB enable signal. The method of claim 2, The QFCB enable signal generation means, Outputting the first shift counter when the burst length is 2; outputting the output of the first and second shift counters when the burst length is 4; A logic operation unit configured to output an output of the fourth shift counter; A driving unit driving the output of the logical operation unit to a predetermined level; And And a latch portion for latching an output of the drive portion. The method of claim 2, The first shift counter, A driver having a pull-up transistor and a pull-down transistor using the write command signal as a gate input, and a counter reset transistor having a reset clock synchronized with a falling edge of the clock signal as a gate input; And a latch for latching an output of the driver from when the write command signal is enabled to when the reset clock is enabled. The method of claim 5, Each of the second to third shift counters, A first switching unit configured to pass an output of a front end shift counter in synchronization with a rising edge of the clock signal; A first latch unit latching an output of the first switching unit and controlled by the reset signal; A second switching unit configured to pass an output of the first latch unit in synchronization with a falling edge of the clock signal; And And latching an output of the second switching unit, the second switching unit being controlled by the reset signal. The method of claim 4, wherein The drive unit, A first pull-up transistor controlled by an output of the logic calculator; A second pull-up transistor controlled by the output of the first shift counter; A pull-down transistor controlled by an output of the logic calculator; And And a switching transistor for synchronizing a disable time point of the QFCB signal to the clock signal. The method of claim 5, The reset clock, And the inverted value of the clock signal and the clock signal delayed for a predetermined time. The method according to any one of claims 1 to 8, The clock signal, A data switch control signal generation circuit, characterized in that the external clock. The method according to any one of claims 1 to 8, The clock signal, A data switch control signal generation circuit, characterized in that the internal clock. The method according to any one of claims 1 to 8, The clock signal, A data switch control signal generation circuit characterized in that it is a delayed synchronization loop (DLL) clock. The method according to any one of claims 1 to 8, The reset signal, And a pulse signal for interrupting a write operation by a burst stop command or a precharge command. In a circuit for generating a data switch control signal (QFCB) for selectively switching electrical connections between a common data bus of a memory module having a plurality of memory chips and each memory chip, QFCB enable signal generation means for enabling the data switch control signal (QFCB) by a burst length set in a section in which write data is controlled by a clock signal, a reset signal, and a write command signal; Output drive signal generating means for generating a pull-down drive signal and a pull-up drive signal by inputting the QFCB enable signal; And Output driving means for outputting the QFCB under control of the pull-down driving signal and the pull-up driving signal; Data switch control signal generation circuit of the memory device comprising a.