KR100333364B1 - Method for planarizing semiconductor device - Google Patents
Method for planarizing semiconductor device Download PDFInfo
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- KR100333364B1 KR100333364B1 KR1019950012608A KR19950012608A KR100333364B1 KR 100333364 B1 KR100333364 B1 KR 100333364B1 KR 1019950012608 A KR1019950012608 A KR 1019950012608A KR 19950012608 A KR19950012608 A KR 19950012608A KR 100333364 B1 KR100333364 B1 KR 100333364B1
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- oxide layer
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- oxide film
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 평탄화 방법에 관한 것으로, 특히 종래의 SOG막을 사용하는 대신에 절연막의 다단계 증착 기법을 이용함으로써 평탄화를 이룩하루 수 있는 반도체 소자의 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a semiconductor device, and more particularly to a planarization method of a semiconductor device capable of achieving planarization by using a multi-step deposition technique of an insulating film instead of using a conventional SOG film.
최근 반도체 소자의 고집적화 경향으로 배선 설계가 자유롭고 용이하며 배선 저항 및 전류용량등의 설정을 여유있게 할 수 있는 다층 배선 기술에 관한 연구가 활발히 진행되고 있다.Recently, due to the high integration trend of semiconductor devices, research on a multilayer wiring technology that enables free and easy wiring design and allows setting of wiring resistance and current capacity has been actively conducted.
다층 배선 기술에서는 하층 배선의 표면 요철 때문에 발생하는 상층의 단선문제, 배선사이에 쇼트 문제를 최소화 하기 위하여 SOG(spin on glass), 또는 BPSG(boron-phosporus silicate glass), PSG(phosporus silicate glass)와 같은 복합 수지 물질을 플로우(flow)시켜 다층 금속층의 층간 절연물로써 평탄화를 이룰 수 있었다.In the multilayer wiring technology, in order to minimize the disconnection problem of the upper layer caused by the surface irregularities of the lower layer wiring and the short problem between the wirings, the spin on glass (SOG), the boron-phosporus silicate glass (BPSG), and the phosporus silicate glass (PSG) The same composite resin material was flowed to achieve planarization with the interlayer insulator of the multilayer metal layer.
첨부한 도면 제 1 도는 종래의 SOG막을 이용하여 금속 패턴간의 평탄화 방법을 나타낸 요부단면도로서, 이를 살펴보면, 금속배선(10) 상부에 절연을 목적으로한 금속 층간 절연막(IMO)을 증착한 후, 상기 금속 배선간에 SOG막을 코팅, 경화하여 금속 배선간의 공간부를 충진시키므로서 하부의 기복을 무마하였다.1 is a cross-sectional view illustrating a planarization method between metal patterns using a conventional SOG film. Referring to FIG. 1, after depositing a metal interlayer insulating film (IMO) for insulation purposes on the metal wiring 10, The SOG film was coated and cured between the metal wirings to fill the space between the metal wirings to smooth the ups and downs of the bottom.
그러나, 상기와 같이 금속 배선간에 SOG막을 충진하는 방법은 다음과 같은 문제점이 있었다.However, the method of filling the SOG film between the metal wirings as described above has the following problems.
우선, SOG 막질상에 존재하는 고질적인 문제점으로서,First of all, as a chronic problem existing on SOG film quality,
첫째, SOG 막은 다량의 수분을 함유하고 있어 콘택 공정시 금속 배선부에 수분이 유입되어 저항 성분이 증가되고, 이로 인하여 배선의 오류를 유발한다는 점과,First, the SOG film contains a large amount of water, so that moisture is introduced into the metal wiring part during the contact process, thereby increasing the resistance component, thereby causing a wiring error.
둘째, SOG 막이 보유하는 수분에 의해 실리콘 기판으로 수분이 확산되어 필드 인버젼을 일으켜 누설 전류에 의해 소자의 특성을 저하시키는 점과,Secondly, moisture is diffused into the silicon substrate by the moisture retained by the SOG film, causing field inversion, and deteriorating the characteristics of the device by leakage current;
세째, SOG막을 코팅하고 경화시키는 단계에서 막의 축소에 의한 크랙 및 보이드등이 발생한다는 점과,Third, in the step of coating and curing the SOG film, cracks and voids are generated by shrinking the film,
네째, 금속간 산화막 증착시 콘택홀의 바닥 모서리 두께가 상부 모서리의 두께보다 얇아 SOG 막의 수분이 바닥 모서리쪽으로 더욱 쉽게 침투하여 급속 배선층을 부식시키는 문제가 발생하였다.Fourth, the thickness of the bottom edge of the contact hole is thinner than the thickness of the top edge during the deposition of the intermetallic oxide film, so that the moisture of the SOG film penetrates more easily toward the bottom edge, thereby causing corrosion of the rapid wiring layer.
또한, 에치백 공정에서 발생하는 SOG 막에 의한 문제는 내부 금속층의 증착시 콘택 홀의 상부 모서리 지역에 네가티브 슬롭(negative slop)이 형성되어 SOG 막 사용은 필수적인데 에치백 공정을 실시하여도 SOG 막이 소량 남게 되므로, 수분에 의한 비아 콘택 저항 증가 문제 및 누설 전류 문제는 여전히 남아 있게 된다.In addition, the problem caused by the SOG film in the etch back process is that a negative slop is formed in the upper corner region of the contact hole during the deposition of the internal metal layer, so the use of the SOG film is essential. As it remains, the problem of increased via contact resistance and leakage current due to moisture still remains.
따라서 본 발명은 종래의 SOG 코팅 및 경화시 하부층으로 침투하는 수분에 의해 야기되는 상기 문제점들 방지하여 소자의 신뢰성을 향상시키는 것을 목적으로 한다.Accordingly, the present invention aims to improve the reliability of the device by preventing the above problems caused by moisture penetrating into the underlying layer during conventional SOG coating and curing.
이하, 본 발명의 일실시예를 첨부한 도면을 참고로 하여 설명하면 다음과 같다:Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described as follows:
제 2 도는 본 발명의 다층 금속 배선의 평탄화 공정을 순차적으로 나타낸 요부단면도이다.2 is a cross-sectional view of principal parts sequentially showing the planarization process of the multi-layered metal wiring of the present invention.
우선, 제 2 도(가)에서와 같이, 하지층 상부에 소자의 전기적 연결을 위해 금속 배선층(20)을 형성한다.First, as shown in FIG. 2A, a metal wiring layer 20 is formed on the base layer for electrical connection of the device.
이어서, 제 2 도(나)에서와 같이, 상기 금속 배선층(20) 상부에 PECVD 방식으로 증착된 얇은 플라즈마 SiO2산화막(21)을 1,000 Å 내지 2,000 Å의 두께로 증착한다. 상기 PECVD 산화막(21)은 기판 표면을 균질화시키고 후속 공정시 수분 통과를 방지하기 위한 장벽 역할을 한다.Subsequently, as shown in FIG. 2B, a thin plasma SiO 2 oxide film 21 deposited by PECVD is deposited on the metal wiring layer 20 to a thickness of 1,000 kPa to 2,000 kPa. The PECVD oxide film 21 serves as a barrier to homogenize the surface of the substrate and to prevent the passage of moisture in subsequent processes.
그 후, 제 2 도(다)에서와 같이, 상기 PECVD 산화막(21) 상부에 APCVD 방식에 의해 저농도 오존 TEOS / 오존 산화막(22)을 500 Å 내지 1,000 Å 두께로 증착한다. 이렇게하여 플라즈마 산화막 표면의 선택비를 보장하여 후속 공정시 표면의 영향을 최소화 할 수 있다. APCVD 방식으로 고농도 오존 TEOS / 오존 산화막(23)을 증착하여 상기 금속 배선(20)간의 갭을 평탄화시킨다. 이때 상기 APCVD 방식으로 고농도 오존 TEOS / 오존 산화막(23) 두께 범위는 후속 에치백되는 두께에 의해 유동적으로 증착 가능하다.Thereafter, as shown in FIG. 2C, a low concentration ozone TEOS / ozone oxide film 22 is deposited on the PECVD oxide film 21 by APCVD to a thickness of 500 kPa to 1,000 kPa. This ensures the selectivity of the surface of the plasma oxide film, thereby minimizing the influence of the surface during subsequent processing. A high concentration ozone TEOS / ozone oxide film 23 is deposited by APCVD to planarize the gap between the metal lines 20. At this time, the thickness range of the high concentration ozone TEOS / ozone oxide layer 23 may be fluidly deposited by the thickness which is subsequently etched back by the APCVD method.
이상, 본 발명은 미세마이크론급 이하의 다층 금속 구조를 갖는 반도체소자 제조시 SOG 막 대신에 3 단계 증착 기법을 이용하여 평탄화를 시킴으로써 SOG 막에 의해 야기되는 상기 문제점들을 해결하고 신뢰성이 높은 반도체 소자를 제조할 수 있게 된다.The present invention solves the problems caused by the SOG film by planarization by using a three-step deposition technique instead of the SOG film when manufacturing a semiconductor device having a multi-layered metal structure of the submicron level or less to provide a highly reliable semiconductor device. It becomes possible to manufacture.
제 1 도는 종래의 평탄화 공정에 따른 다층 금속 배선의 요부단면도.1 is a cross-sectional view of principal parts of a multi-layered metal wiring according to a conventional planarization process.
제 2 도는 본 발명의 다층 금속 배선의 평탄화 공정을 순차적으로 나타낸 요부단면도.2 is a sectional view of principal parts showing a planarization process of a multilayer metal wiring of the present invention in sequence.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10, 20 : 금속배선층 11, 11' : 금속간 산화막10, 20: metal wiring layer 11, 11 ': intermetallic oxide film
12 : SOG 막 21 : PECVD 산화막12: SOG film 21: PECVD oxide film
22 : 저농도 오존 산화막 23 : 고농도 오존 산화막22: low concentration ozone oxide film 23: high concentration ozone oxide film
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950012608A KR100333364B1 (en) | 1995-05-19 | 1995-05-19 | Method for planarizing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950012608A KR100333364B1 (en) | 1995-05-19 | 1995-05-19 | Method for planarizing semiconductor device |
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| Publication Number | Publication Date |
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| KR960043023A KR960043023A (en) | 1996-12-21 |
| KR100333364B1 true KR100333364B1 (en) | 2002-09-04 |
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| KR1019950012608A KR100333364B1 (en) | 1995-05-19 | 1995-05-19 | Method for planarizing semiconductor device |
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| KR100315446B1 (en) * | 1999-03-25 | 2001-11-28 | 황인길 | Shallow trench manufacturing method for isolating semiconductor devices |
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