KR100330579B1 - Quad flat package ic mounted pcb and soldering method thereof - Google Patents
Quad flat package ic mounted pcb and soldering method thereof Download PDFInfo
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- KR100330579B1 KR100330579B1 KR1019990036348A KR19990036348A KR100330579B1 KR 100330579 B1 KR100330579 B1 KR 100330579B1 KR 1019990036348 A KR1019990036348 A KR 1019990036348A KR 19990036348 A KR19990036348 A KR 19990036348A KR 100330579 B1 KR100330579 B1 KR 100330579B1
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- Prior art keywords
- solder
- flat package
- land
- land group
- way flat
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- 238000000034 method Methods 0.000 title claims description 15
- 238000005476 soldering Methods 0.000 title description 13
- 229910000679 solder Inorganic materials 0.000 claims abstract description 81
- 238000000576 coating method Methods 0.000 claims abstract description 22
- 239000011248 coating agent Substances 0.000 claims abstract description 15
- 239000007767 bonding agent Substances 0.000 claims description 6
- 230000006698 induction Effects 0.000 description 9
- 230000004907 flux Effects 0.000 description 4
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- XOMKZKJEJBZBJJ-UHFFFAOYSA-N 1,2-dichloro-3-phenylbenzene Chemical compound ClC1=CC=CC(C=2C=CC=CC=2)=C1Cl XOMKZKJEJBZBJJ-UHFFFAOYSA-N 0.000 description 1
- WVHNUGRFECMVLQ-UHFFFAOYSA-N 1,3-dichloro-2-(2,4-dichlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC=C1C1=C(Cl)C=CC=C1Cl WVHNUGRFECMVLQ-UHFFFAOYSA-N 0.000 description 1
- LAXBNTIAOJWAOP-UHFFFAOYSA-N 2-chlorobiphenyl Chemical compound ClC1=CC=CC=C1C1=CC=CC=C1 LAXBNTIAOJWAOP-UHFFFAOYSA-N 0.000 description 1
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 101710149812 Pyruvate carboxylase 1 Proteins 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
본 발명은, 사각판면을 가진 4방향 플랫 패키지IC의 4방향을 따라 배치되며 4방향 플랫 패키지IC의 거의 대각선방향을 따른 땜납도포방향에 대해 전방 및 후방에 위치하는 각각 한 쌍의 전방랜드군 및 후방랜드군을 갖는 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법에 관한 것이다. 본 회로기판은, 상기 땜납도포방향에 대해 경사각을 가지고 전방랜드군과 후방랜드군 사이 영역에 인접하게 돌출 배치되어 땜납을 상기 후방랜드군의 배치방향을 따라 안내하는 땜납안내리브와, 상기 한 쌍의 후방랜드군 사이에 형성되어 상기 후방랜드군으로부터의 땜납을 흡입하는 후방유도랜드를 포함하는 것을 특징으로 한다. 이에 의해, 땜납안내리브를 형성함으로써, 4방향 플랫 패키지IC의 전방랜드군과 후방랜드군 사이에서의 쇼트나 브릿지를 방지할 수 있게 된다.The present invention provides a pair of front land groups each disposed along four directions of a four-way flat package IC having a square plate surface and positioned forward and rearward with respect to the solder coating direction along a substantially diagonal direction of the four-way flat package IC. A circuit board for mounting a 4-way flat package IC having a rear land group and a solder coating method thereof. The circuit board includes a solder guide rib protrudingly disposed adjacent to an area between the front land group and the rear land group with an inclination angle with respect to the solder application direction, and guiding solder along the arrangement direction of the rear land group; It is formed between the rear land group of the rear land group, characterized in that it comprises a rear guide land for sucking the solder from the rear land group. As a result, by forming the solder guide ribs, shorts and bridges between the front land group and the rear land group of the four-way flat package IC can be prevented.
Description
본 발명은 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법에 관한 것으로서, 보다 상세하게는, 땜납도포시 쇼트를 방지하기 위한 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for mounting 4-way flat package ICs and a solder coating method thereof, and more particularly, to a circuit board for mounting 4-way flat package ICs and a solder coating method thereof in order to prevent shorts during solder coating. will be.
일반적으로 PCB의 부품실장공정은, PCB의 표면에 표면실장부품(SMD)나 삽입부품(IMD)을 납땜으로 고정하는 작업공정으로, PCB에는 표면실장부품(SMD)나 삽입부품(IMD)중 한 종류만이 실장되거나 표면실장부품과 삽입부품이 혼재 실장되며, 최근에는 표면실장부품과 삽입부품이 혼재 실장되는 경우가 많다.In general, the component mounting process of a PCB is a work process of fixing a surface mount component (SMD) or an insert component (IMD) by soldering to a surface of the PCB, and one of the surface mount component (SMD) and the insert component (IMD) is applied to the PCB. Only the type is mounted or surface-mounted parts and inserts are mixed-mounted, and recently, surface-mounted parts and inserts are often mixed-mounted.
이러한 부품실장공정은, PCB에 부품을 배열하는 단계, 플럭스(flux)를 도포하는 단계, 예열하는 단계, 땜납을 도포하는 단계, PCB를 냉각하는 단계로 구분할 수 있다.The component mounting process may be divided into arranging components on a PCB, applying flux, preheating, applying solder, and cooling the PCB.
한편, PCB에는 표면실장부품이 배치되는 위치에는 단자에 대응하는 랜드가 형성되어 있고, 삽입부품이 배치되는 위치에는 단자에 대응하는 홀이 형성되어 있으며, PCB에 부품을 배열시 표면실장부품은 칩본드의 도포에 의해 실장위치에 배치되고, 삽입부품은 홀에 단자를 관통시켜 배치된다.On the other hand, a land corresponding to the terminal is formed at the position where the surface mounting component is disposed on the PCB, and a hole corresponding to the terminal is formed at the position where the insertion component is disposed, It is arrange | positioned at a mounting position by application | coating of a bond, and an insertion part is arrange | positioned through the terminal through a hole.
이렇게 표면실장부품이나 삽입부품이 배치된 PCB에는 플럭스를 도포하며, 플럭스는 이소프로필 알코올과 송진(rosin)을 주성분으로 하는 여러 가지 화학물질들로 이루어져 PCB 상의 접합부를 세정하여 금속의 산화를 방지하고 땜납의 도포시 표면장력을 감소시키게 된다. 플럭스가 도포된 PCB는, 납땜공정시 갑작스런 온도상승으로 PCB가 휘는 것을 방지하기 위해 예열과정을 거친 다음, 땜납을 도포하는 솔더링 단계로 돌입하게 된다.Flux is applied to the PCB on which surface-mount components or inserts are placed. Flux is composed of various chemicals whose main components are isopropyl alcohol and rosin, and prevents oxidation of metal by cleaning the joints on the PCB. The application of solder reduces surface tension. The flux-coated PCB is preheated to prevent bending of the PCB due to sudden temperature rise during the soldering process, and then enters the soldering step of applying solder.
솔더링 단계에서, 표면실장부품의 실장시에는 리플로우(reflow) 솔더링 방법이 사용되고, 삽입부품의 실장시에는 플로우(flow) 솔더링 방법이 사용되며, 표면실장부품과 삽입부품이 혼재 실장된 경우에는 플로우 솔더링 방법이 주로 사용된다. 플로우 솔더링방법은, PCB를 납이 분사되는 납조를 통과시켜 표면실장부품과 삽입부품의 단자에 납땜이 이루어지도록 하는 방법으로 표면실장부품 경우 플로우솔더링에 의해 땜납이 랜드에 부착된다.In the soldering step, a reflow soldering method is used for mounting the surface mount component, a flow soldering method is used for mounting the insert, and in the case where the surface mount component and the insert are mixed Soldering method is mainly used. In the flow soldering method, the solder is attached to the land by flow soldering in the case of the surface mount component, in which the PCB is soldered to the terminals of the surface mount component and the insert component by passing the lead bath through which lead is injected.
이러한 표면실장부품중 QFP(Quad Flat Package) IC는 4방향 플랫 패키지IC라고도 하며, 정사각형이나 직사각형의 패키지를 가지고, 패키지의 네 변에 모두 리드가 형성되어 있다.Among these surface mount components, QFP (Quad Flat Package) IC is also called a 4-way flat package IC, and has a square or rectangular package, and leads are formed on all four sides of the package.
이러한 4방향 플랫 패키지IC는 PCB의 땜납도포방향을 따라 대각선 방향으로 거의 45。회전된 상태로 배치되며, PCB(51) 상에는, 도 3에 도시된 바와 같이, 4방향 플랫 패키지IC의 각 래드에 대응하는 랜드가 형성되어 있다. 여기서, 화살표는 땜납도포방향을 표시한다.The four-way flat package IC is disposed in an approximately 45 ° rotation in a diagonal direction along the solder coating direction of the PCB. On the PCB 51, as shown in FIG. Corresponding lands are formed. Here, the arrow indicates the solder coating direction.
4방향 플랫 패키지IC(55)의 랜드는, 땜납도포방향을 따라 전방에 위치하는 두 변에 형성된 각 리드에 해당하는 랜드들의 집합인 한 쌍의 전방랜드군(57)과, 땜납도포방향의 후방에 위치하는 한 쌍의 후방랜드군(59)을 포함한다. 그리고, 한 쌍의 전방랜드군(57) 사이인 선단부에는 땜납을 유도하는 전방유도랜드(58)가 형성되어 있으며, 전방유도랜드(58)는 중앙영역이 땜납도포방향을 따라 구획된 한 쌍의 랜드부분으로 이루어져 각 전방랜드군(57)으로 각각 땜납을 유도하게 된다.The land of the four-way flat package IC 55 is a pair of front land groups 57 which are sets of lands corresponding to each lead formed on two sides located forward along the solder coating direction, and the rear of the solder coating direction. It includes a pair of rear land group 59 located in. In addition, a front induction land 58 for inducing solder is formed at the tip portion between the pair of front land groups 57, and the front induction land 58 has a pair of central regions partitioned along the solder coating direction. It consists of land portions to induce solder to each of the front land groups 57, respectively.
그리고, 각 전방랜드군(57)과 후방랜드군(59) 사이의 절곡부위에는 전방랜드군(57)을 따라 유동한 땜납을 후방랜드군(59)으로 유도하기 위한 한 쌍의 측방유도랜드(60)가 형성되어 있으며, 이 측방유도랜드(60)는 그 폭이 전방랜드군(57) 및 후방랜드군(59)의 랜드폭과 동일하고, 절곡방향을 따라 완만하게 만곡된 부채꼴 형상으로 형성되어 있다. 또한, 각 후방랜드군(59)의 사이에는 후방랜드군(59)을 따라 유동된 땜납의 잔여분을 수용하는 후방유도랜드(65)가 형성되어 있고, 이 후방유도랜드(65)는 후방랜드군(59)의 말단부에 형성된 랜드들이 잔여분의 땜납으로 인해 쇼트나 브릿지가 발생하는 것을 방지하게 된다.Then, at the bent portion between the front land group 57 and the rear land group 59, a pair of side guide lands for guiding solder flowing along the front land group 57 to the rear land group 59 ( 60 is formed, and the side induction land 60 has a width equal to the land width of the front land group 57 and the rear land group 59, and is formed in a fan shape gently curved along the bending direction. It is. In addition, a rear guide land 65 is formed between each rear land group 59 to accommodate the remaining portion of the solder flowing along the rear land group 59, and the rear guide land 65 is a rear land group. Lands formed at the distal end of 59 prevent the short or bridge from occurring due to the residual solder.
그런데, 이러한 4방향 플랫 패키지IC(55)의 측방유도랜드(60)는 그 폭이 랜드의 폭과 동일하여 과도한 땜납을 유치시킴으로써, 땜납의 뭉침을 초래하고 땜납이 과다하게 사용된다는 문제점이 있다. 한편, 전방유도랜드(58)는 각 전방랜드군(57)으로 땜납을 유도하기 위해 형성되어 있으나, 땜납의 진행시 오히려 전방유도랜드(58)의 면적이 넓어 표면장력에 의해 땜납이 뭉쳐 전방랜드군(57)의 땜납진행방향 입구측에 있는 랜드들이 쇼트가 발생하게 된다.However, the side induction land 60 of the four-way flat package IC 55 has the same width as that of the land, thereby attracting excessive solder, resulting in agglomeration of solder and excessive use of solder. On the other hand, the front induction land 58 is formed to induce solder to each of the front land group 57, but rather the area of the front induction land 58 when the solder proceeds, so that the solder is agglomerated by the surface tension The lands on the inlet side of the group 57 in the soldering direction are short-circuited.
따라서 본 발명의 목적은, 4방향 플랫 패키지IC의 전방랜드군과 후방랜드군의 연결영역과, 전방랜드군의 입구측의 쇼트나 브릿지를 방지할 수 있도록 하는 4방향 플랫 패키지IC 실장용 회로기판 및 그 땜납도포방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a circuit board for mounting 4-way flat package ICs to prevent short and bridges at the inlet side of the front land group and the rear land group of the 4-way flat package IC. And a solder coating method thereof.
도 1은 본 발명의 일 실시예에 따른 회로기판의 평면도,1 is a plan view of a circuit board according to an embodiment of the present invention;
도 2는 도 1의 Ⅱ-Ⅱ선에 따른 측단면도,2 is a side cross-sectional view taken along line II-II of FIG. 1;
도 3은 종래의 회로기판의 평면도이다.3 is a plan view of a conventional circuit board.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 : PCB 5 : 4방향 플랫 패키지IC1: PCB 5: 4-way flat package IC
7 : 전방랜드군 9 : 후방랜드군7: Forward Land Force 9: Rear Land Force
10 : 땜납안내리브 15 : 후방유도랜드10: solder guide rib 15: rear guide land
상기 목적은, 본 발명에 따라, 사각판면을 가진 4방향 플랫 패키지IC의 4방향을 따라 배치되며 4방향 플랫 패키지IC의 거의 대각선방향을 따른 땜납도포방향에 대해 전방 및 후방에 위치하는 각각 한 쌍의 전방랜드군 및 후방랜드군을 갖는 4방향 플랫 패키지IC 실장용 회로기판에 있어서, 상기 땜납도포방향에 대해 경사각을 가지고 전방랜드군과 후방랜드군 사이 영역에 인접하게 돌출 배치되어 땜납을 상기 후방랜드군의 배치방향을 따라 안내하는 땜납안내리브를 포함하는 것을 특징으로 하는 회로기판에 의해 달성된다.The above object is, in accordance with the present invention, a pair disposed along the four directions of the four-way flat package IC having a square plate surface and positioned forward and rearward with respect to the solder coating direction along the substantially diagonal direction of the four-way flat package IC. A circuit board for mounting a four-way flat package IC having a front land group and a rear land group of the circuit board, wherein the circuit board has a slant angle with respect to the solder coating direction and protrudes adjacent to the area between the front land group and the rear land group. It is achieved by a circuit board comprising a solder guide rib for guiding along the arrangement direction of the land group.
여기서, 상기 땜납안내리브는 상기 후방랜드군의 배치방향에 평행하게 상기 후방랜드군과 소정의 간격을 두고 형성되는 것이 땜납의 유도를 용이하게 할 수 있다.Here, the solder guide ribs may be formed at a predetermined distance from the rear land group in parallel to the arrangement direction of the rear land group to facilitate the induction of solder.
그리고, 상기 땜납안내리브는 상기 4방향 플랫 패키지IC의 본딩을 위한 본딩제의 도포 및 경화에 의해 형성되거나 패널부품의 부착에 의해 형성될 수 있다.The solder guide ribs may be formed by applying and curing a bonding agent for bonding the four-way flat package IC or by attaching a panel component.
한편, 상기 목적은, 본 발명의 다른 분야에 따르면, 사각판면을 가진 4방향 플랫 패키지IC의 4방향을 따라 배치되며 4개의 랜드군을 갖는 4방향 플랫 패키지IC의 실장용 회로기판의 땜납도포방법에 있어서, 인접한 한 쌍의 전방랜드군과 나머지 한 쌍의 후방랜드군 사이의 영역에서 상기 후방랜드군의 배치방향과 거의 평행한 땜납안내리브를 마련하는 단계와; 상기 회로기판을 상기 전방랜드군에서 상기 후방랜드군를 연결하는 대각선 방향을 따라 땜납조에 통과시켜 땜납을 도포하는 단계를 포함하는 것을 특징으로 하는 회로기판의 회로기판의 땜납도포방법에 의해서도 달성될 수 있다.On the other hand, the above object, according to another field of the present invention, the solder coating method of the circuit board for mounting the four-way flat package IC having four land groups and arranged along the four directions of the four-way flat package IC having a rectangular plate surface Providing a solder guide rib substantially parallel to an arrangement direction of said rear land group in an area between an adjacent pair of front land groups and a pair of rear land groups; Passing the circuit board through the solder bath along the diagonal direction connecting the rear land group from the front land group, it may be achieved by the solder coating method of the circuit board of the circuit board, characterized in that it comprises the step of applying solder. .
여기서, 상기 땜납안내리브는 상기 후방랜드군과 소정의 간격을 두고 형성되며, 상기 땜납안내리브는 상기 4방향 플랫 패키지IC의 본딩을 위한 본딩제의 도포 및 경화과정에 의해 형성되는 것이 바람직하다.Here, the solder guide rib is formed at a predetermined distance from the rear land group, the solder guide rib is preferably formed by the application and curing process of the bonding agent for bonding the four-way flat package IC.
이하, 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the drawings.
도 1은 4방향 플랫 패키지IC의 실장을 위한 랜드가 형성된 PCB의 평면도이다. 4방향 플랫 패키지IC(5)는 땜납도포방향을 따라 대각선 방향으로 거의 45。회전된 상태로 배치되게 되며, 이에 따라, PCB(1) 상에는 4방향 플랫 패키지IC(5)에대응하는 랜드가 형성되어 있다. 여기서, 화살표는 땜납도포방향을 표시한다.1 is a plan view of a PCB on which lands for mounting a four-way flat package IC are formed. The four-way flat package IC 5 is disposed to be rotated almost 45 ° in the diagonal direction along the solder coating direction. Thus, lands corresponding to the four-way flat package IC 5 are formed on the PCB 1. It is. Here, the arrow indicates the solder coating direction.
4방향 플랫 패키지IC(5)의 랜드는, 땜납도포방향을 따라 전방에 위치하는 두 변에 형성된 각 리드에 해당하는 랜드들의 집합인 한 쌍의 전방랜드군(7)과, 땜납도포방향의 후방에 위치하는 한 쌍의 후방랜드군(9)을 포함한다.The land of the four-way flat package IC 5 is a pair of front land groups 7 which are sets of lands corresponding to each lead formed on two sides located forward along the solder coating direction, and the rear of the solder coating direction. It includes a pair of rear land group (9) located in.
여기서, 전방랜드군(7)과 후방랜드군(9) 사이 영역에는 후방랜드군(9)과 소정의 간격을 두고 후방랜드군(9)의 배치방향을 따라 돌출 배치된 땜납안내리브(10)가 형성되어 있으며, 이 땜납안내리브(10)는 전방랜드군(7)으로부터의 땜납과 4방향 플랫 패키지IC(5)의 측방영역으로 진행하는 땜납의 흐름을 차단하여 후방랜드군(9)으로 안내하는 역할을 하게 된다. 땜납안내리브(10)는 표면실장부품을 접착하기 위한 본딩제를 연속적으로 낙하시켜 형성할 수도 있고 패널부품을 접착하여 형성할 수도 있으며, 본딩제로 형성할 경우에는 표면실장부품의 실장전 본딩제의 도포시 함께 형성된다.Here, in the region between the front land group 7 and the rear land group 9, the solder guide rib 10 protrudingly arranged along the arrangement direction of the rear land group 9 at a predetermined distance from the rear land group 9. And the solder guide ribs 10 block the flow of the solder from the front land group 7 and the solder proceeding to the lateral region of the four-way flat package IC 5 to the rear land group 9. It serves as a guide. The solder guide ribs 10 may be formed by continuously dropping the bonding agent for bonding the surface mount component, or may be formed by adhering the panel component, and in the case of forming the bonding agent, When applied together.
한편, 각 후방랜드군(9)의 사이에는 후방랜드군(9)을 따라 유동된 땜납의 잔여분을 수용하는 후방유도랜드(15)가 형성되어 있으며, 이 후방유도랜드(65)는 후방랜드군(59)의 말단부에 형성된 랜드들이 잔여분의 땜납으로 인해 쇼트나 브릿지가 발생하는 것을 방지하게 된다.On the other hand, a rear guide land 15 is formed between each of the rear land groups 9 to accommodate the remaining portion of the solder flowing along the rear land group 9, and the rear guide lands 65 are the rear land groups. Lands formed at the distal end of 59 prevent the short or bridge from occurring due to the residual solder.
이러한 구성에 의하여, 플로우 솔더링방법에 의한 땜납도포시, 땜납이 납땜진행방향으로 진행하여 4방향 플랫 패키지IC(5)의 선단부에 도달하면, 땜납이 양 전방랜드군(7)을 따라 이동하여 각 랜드에 땜납이 도포된다. 그리고, 4방향 플랫 패키지IC(5)의 측방을 따라 흐르던 땜납은 땜납안내리브(10)에 의해 그 흐름방향이전환되어 후방랜드군(9)으로 안내된다. 이렇게 양 후방랜드군(9)으로 안내되어 유동된 땜납은 후방유도랜드(15)에 수용된다.With this configuration, when solder is applied by the flow soldering method, when the solder proceeds in the soldering progress direction and reaches the tip of the four-way flat package IC 5, the solder moves along both front land groups 7 Solder is applied to the lands. Then, the solder flowing along the side of the four-way flat package IC 5 is switched by the solder guide ribs 10 and guided to the rear land group 9. The solder guided and flown to both rear land groups 9 is received in the rear induction land 15.
이와 같이, 본 발명에서는 전방랜드군(7)과 후방랜드군(9) 사이에 땜납안내리브(10)를 형성함으로써, 4방향 플랫 패키지IC(5)의 측방영역으로 흐르던 땝납의 흐름을 후방랜드군(9)으로 안내하여 후방랜드군(9)에 충분한 땜납을 공급할 수 있다. 그리고, 종래의 측방유도랜드에 의해 발생하던 땜납 과잉으로 인한 측방유로랜드에 인접한 전방랜드군 및 후방랜드군의 쇼트나 브릿지를 방지할 수 있게 된다.As described above, in the present invention, the solder guide rib 10 is formed between the front land group 7 and the rear land group 9 so that the flow of the solder flowing to the lateral area of the four-way flat package IC 5 is reduced to the rear land. Guided to the group 9, sufficient solder can be supplied to the rear land group 9. In addition, it is possible to prevent a short or bridge between the front land group and the rear land group adjacent to the side flow land due to the excess solder caused by the conventional side guide land.
한편, 본 발명에서는 전방유도랜드를 삭제함으로써, 전방랜드군(7)의 땜납진행방향 입구측에 있는 랜드들의 쇼트를 방지할 수 있게 된다.On the other hand, in the present invention, by eliminating the front induction land, it is possible to prevent the short of the lands on the inlet side of the solder progress direction of the front land group 7.
이상에서 설명한 바와 같이, 본 발명에 따르면, 땜납안내리브를 형성함으로써, 전방랜드군과 후방랜드군의 연결영역과, 전방랜드군의 입구측의 쇼트나 브릿지를 방지할 수 있게 된다.As described above, according to the present invention, by forming the solder guide rib, it is possible to prevent the connection region between the front land group and the rear land group, and the short or bridge at the inlet side of the front land group.
Claims (7)
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| KR1019990036348A KR100330579B1 (en) | 1999-08-30 | 1999-08-30 | Quad flat package ic mounted pcb and soldering method thereof |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106744A (en) * | 1993-09-30 | 1995-04-21 | Sony Corp | Land for solder dip of four-way-lead flat package ic and dip soldering method |
| JPH07115261A (en) * | 1993-10-15 | 1995-05-02 | Toyota Motor Corp | Printed wiring board and its soldering |
| KR950024627A (en) * | 1994-01-17 | 1995-08-21 | 김광호 | Soldering Land Patterns on Printed Circuit Boards |
| JPH09181435A (en) * | 1995-12-27 | 1997-07-11 | Sharp Corp | Printed wiring board |
| JPH1084183A (en) * | 1996-09-06 | 1998-03-31 | Sumitomo Wiring Syst Ltd | Soldering jig for surface mount chip |
| JPH10163582A (en) * | 1996-11-27 | 1998-06-19 | Matsushita Electric Ind Co Ltd | Printed board for reflow soldering |
-
1999
- 1999-08-30 KR KR1019990036348A patent/KR100330579B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106744A (en) * | 1993-09-30 | 1995-04-21 | Sony Corp | Land for solder dip of four-way-lead flat package ic and dip soldering method |
| JPH07115261A (en) * | 1993-10-15 | 1995-05-02 | Toyota Motor Corp | Printed wiring board and its soldering |
| KR950024627A (en) * | 1994-01-17 | 1995-08-21 | 김광호 | Soldering Land Patterns on Printed Circuit Boards |
| JPH09181435A (en) * | 1995-12-27 | 1997-07-11 | Sharp Corp | Printed wiring board |
| JPH1084183A (en) * | 1996-09-06 | 1998-03-31 | Sumitomo Wiring Syst Ltd | Soldering jig for surface mount chip |
| JPH10163582A (en) * | 1996-11-27 | 1998-06-19 | Matsushita Electric Ind Co Ltd | Printed board for reflow soldering |
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