KR100327413B1 - Lock Detecting Method of symbol synchronization circuit in digital receiver - Google Patents

Abstract

The present invention can reduce the influence of noise by using the absolute value of the signal for detecting the lock state of the symbol synchronization circuit, the lock state of the symbol synchronization circuit in a digital receiver that can reduce the amount of calculation and the number of bits required for signal processing It relates to a detection method. The present invention is to obtain an absolute value of the BPSK signal for detecting the lock state of the symbol synchronization circuit, accumulating the absolute value by a predetermined number of times, comparing the accumulated value with a predetermined threshold value; And determining a lock state of the symbol synchronization circuit according to the comparison value.

Description

Lock Detecting Method of symbol synchronization circuit in digital receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lock detector for identifying a lock state of a symbol synchronization circuit included in a digital receiver, and more particularly, to a method for detecting a lock state of a symbol synchronization circuit having a strong characteristic against noise.

In general, a digital receiver can freely convert a scanning method of a broadcast signal, can adjust channels of television and radio to be convenient for a user, and has the advantage of receiving all digital broadcasts.

Such a digital receiver is provided with a symbol synchronization circuit for matching symbol synchronization of input data. The reason for using a symbol synchronization circuit is to correctly and accurately estimate the optimal sample point of a symbol at the receiver based on the received data sequence. Therefore, the symbol synchronization procedure is an essential step in the demodulation process of digital communication.

In the general digital communication system, the transmitter and the receiver know exactly each other's transmission rate, and therefore, a separate clock generation circuit is not required in the receiver.

However, in a wireless communication environment such as a satellite channel and a mobile channel, since the speed of a received symbol is variable, a clock generation circuit using a separate phase locking loop (PLL) must be used for accurate digital demodulation.

A digital demodulator, which is widely used now, describes a procedure for performing accurate demodulation after receiving a signal.

First, find the best sample point of a symbol through the symbol synchronization circuit. Thereafter, the carrier recovery procedure, the automatic gain control procedure, and the decoding procedure are executed in order to restore the received data to the original data.

At this time, if the symbol synchronization is wrong during operation of the receiver, all other receiver components temporarily stop the operation until the symbol synchronization by the symbol synchronization circuit is completed. Therefore, it is essential to accurately grasp the state of the symbol synchronization circuit for the smooth operation of the overall receiver. That is, it is necessary to determine whether the symbol synchronization circuit is driven by determining whether the symbol synchronization circuit is locked or unlocked. Therefore, the correct operation of the lock detector (lock detector) is required for accurate symbol synchronization.

A general lock detector serves to monitor and control the operation of a receiver. The following describes the desirable output characteristics of a lock detector for a symbol synchronization circuit.

First, it is a periodic function having a period of 0.5 for the timing error normalized to the symbol rate T, and should be a symmetric function around zero.

Second, the output of the lock detector should have a maximum value at the instant of zero timing error and be inversely proportional to the absolute value of the timing error in the range of -0.5 to 0.5.

Third, there should be no discontinuities for timing errors and the integral result of the period should be as close to zero as possible.

When accumulating a signal having the above characteristics a certain number of times, an output above a certain value appears only when a lock is applied, and a value close to zero appears when a lock is not performed. You can determine whether the current state is locked or unlocked.

On the other hand, an important consideration in the implementation of the digital receiver is to reduce the burden on the processing speed. Therefore, it is desirable to minimize the number of samples required for the operation of the symbol synchronization circuit and to adjust the condition to be independent of the carrier synchronization circuit.

Currently, the most widely used symbol synchronization circuits include Gardner and decision-oriented symbol synchronization circuits. Since the Gardner-type symbol synchronization circuit operates by using two samples per symbol, the burden on processing speed can be reduced, and the output characteristics are independent of phase offset and noise, so that symbol timing is independent of the carrier synchronization circuit. Can be recovered. Due to such characteristics, many Gardner-type symbol synchronization circuits are generally provided in the receiver.

There are two kinds of Gardner-type lock detectors known to date, represented by Equations 1 and 2 below.

First, the A-type lock detector represented by Equation 1 uses an intermediate sample of samples necessary for the timing detector operation, and shifts the output characteristic of the Gardner-type lock detector by 0.25 for a timing error normalized to the symbol rate T. Therefore, when the timing error is 0, that is, in the locked state, the maximum output value is obtained.

In addition, the B-type lock detector uses the same sample used in the timing detector, and subtracts the square of the zero crossing sample point signal from the square of the optimal sample point signal. You will get the maximum output value. These two types of lock detectors satisfy all of the requirements of the lock detectors described above, and thus exhibit excellent detection performance in connection with actual symbol synchronization circuits.

However, there are the following problems when applying this to a digital receiver by implementing this as an actual digital circuit.

First, the Type A lock detector requires four sampling operations per symbol, requiring a faster analog-to-digital converter. Equipped with a high-speed analog-to-digital converter is not only difficult to implement, but also increases the hardware complexity of the digital receiver, and also increases the price of the entire receiver.

In addition, the type B lock detector has a disadvantage that the amount of calculation is larger than the type A lock detector. That is, at least two multipliers and one subtractor are required to calculate u _k once, and the hardware complexity is increased because a very large number of bits are required for the square operation of signal and noise.

In addition, when the signal-to-noise ratio (SNR) is low, the effect of mutual noise due to noise is increased, and reliability is likely to be greatly degraded.

In such a situation, in order to implement a lock detector of a more efficient digital receiver, an improved lock detector capable of reducing not only the amount of calculation but also the number of samples per symbol is required.

An object of the present invention has been made in view of the above-mentioned problems of the prior art, by using the absolute value of the signal for detecting the lock state of the symbol synchronization circuit to reduce the effect of noise, which is required during signal processing It is an object of the present invention to provide a lock state detection method of a symbol synchronization circuit in a digital receiver capable of reducing the amount of computation and the number of bits.

According to one aspect of the present invention for achieving the above object, the present invention is to obtain an absolute value of the BPSK signal for detecting the lock state of the symbol synchronization circuit, accumulating the absolute value a predetermined number of times, Comparing the accumulated value with a set threshold value, and determining a lock state of the symbol synchronization circuit according to the comparison value.

1 is a block diagram of a general digital receiver.

2 is a block diagram of a lock detector according to the present invention;

Figure 3 is a graph showing the average characteristics of the Gardner type timing error detector.

4 is a graph showing output characteristics of a conventional detection method and a detection method according to the present invention.

5 is a graph showing output dispersion characteristics of a conventional detection method and a detection method according to the present invention.

Figure 6 is a graph showing the signal-to-noise ratio characteristics between the conventional lock detector and the output signal of the lock detector according to the present invention.

7 is a graph showing dispersion ratio characteristics in a locked state with respect to dispersion in an unlocked state between a conventional lock detector and an output signal of a lock detector according to the present invention.

8 is a graph showing a detection failure probability characteristic according to the false lock probability required at the output of the conventional lock detector and the lock detector according to the present invention.

9 is a graph showing the detection failure probability characteristics according to the observation interval M in the output of the conventional lock detector and the lock detector according to the present invention.

10 is a graph showing the detection failure probability characteristics according to the roll-off parameter α value at the output of the conventional lock detector and the lock detector according to the present invention.

* Description of the symbols for the main parts of the drawings *

10a, 10b: multiplier 20,50: voltage controlled oscillator

40a, 40b: analog-to-digital converter 60a, 60b: pulse shaping filter

70 loop filter 80 timing error detector

90 symbol synchronization circuit 100 lock detector

Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram of a general digital receiver.

1 shows a digital demodulator including a lock detector 100 in a symbol synchronization circuit. The received signal input in FIG. 1 passes through the analog / digital converters 40a and 40b after the carriers on the I and Q channels are removed through the multipliers 10a and 10b, respectively. In this process, the accurate removal of the carrier is performed by the carrier cancellation circuit, indicated as 90 after the symbol synchronization is completed. That is, carrier frequency error components (frequency offset and phase offset) are present in the signals input to the analog / digital converters 40a and 40b.

Once the carrier signal is removed, the signal is analog-digital converted and then passed through a kind of matched filter pulse shaping filters 60a and 60b to the symbol synchronization circuit 90. Here, the clock information of the analog / digital converters 40a and 40b is input through the symbol synchronization circuit 90. That is, the symbol synchronizing circuit 90 provides the sample / signal information to the analog-to-digital converters 40a and 40b, respectively, by using a phase control loop (PLL) circuit with a signal sampled at any point in time at the initial power-up of the system. do.

In the present invention, a lock detector for a Gardner type symbol synchronization circuit 90 as shown in FIG. 2 is proposed. First, the Gardner timing error detection method may be represented by Equation 3 below.

Currently sampled signal as shown in equation (3) Is a sampled signal before a symbol And then subtract that intermediate sample Is multiplied to drive the loop filter 70 of FIG. The loop filter 70 adjusts the clocks of the analog / digital converters 40a and 40b by driving a voltage-controlled oscillator (VCO) 50 according to the input timing error detector output value.

3 shows the average characteristic of the Gardner type timing error detector.

First, when the timing error normalized to the symbol rate is 0.25 as shown in FIG. 3, that is, when the sampling time point of the current analog-to-digital converters 40a and 40b is 0.25 times faster than the optimum sample time point, the timing error detector is The negative output value delays the sample time points of the analog / digital converters 40a and 40b by the timing error detector output value. On the contrary, when the timing error is -0.25, the sample time of the analog-to-digital converters 40a and 40b is advanced through the positive output value.

Also, in the absence of a timing error, i.e. at the optimum sample point, the timing error detector maintains the sample timing of the current analog-to-digital converters 40a and 40b through an output value of zero. Through the operation of the timing error detector, the sample time point of the analog / digital converters 40a and 40b can always track the optimal sample time point.

A digital demodulator, which is widely used now, describes a procedure for performing accurate demodulation after receiving a signal.

First, find the best sample point of a symbol through the symbol synchronization circuit. Thereafter, the carrier recovery procedure, the automatic gain control procedure, and the decoding procedure are executed in order to restore the received data to the original data.

At this time, if the symbol synchronization is wrong during operation of the receiver, all other receiver components temporarily stop the operation until the symbol synchronization by the symbol synchronization circuit is completed. Therefore, it is essential to accurately grasp the state of the symbol synchronization circuit for the smooth operation of the overall receiver. That is, it is necessary to determine whether the symbol synchronization circuit is driven by determining whether the symbol synchronization circuit is locked or unlocked. Therefore, the correct operation of the lock detector (lock detector) is required for accurate symbol synchronization.

The detection scheme proposed in the present invention uses absolute values to be suitable for digital circuit implementation. In addition, the same sample as the timing error detector of 2 samples per symbol eliminates the need for a high-speed analog-to-digital converter like conventional A-type lock detectors. First, the input signal is output of the proposed scheme for BPSK signals. ) Can be expressed as Equation 4 below.

Looking at the operation of the lock detector 100 here, the signal of equation (4) ( ) Is accumulated a certain number of times and the value is compared with the set threshold. At this time, when the accumulated output value is larger than the threshold value, it is determined as a locked state and when it is smaller, it is determined as an unlocked state.

In the unlocked state, the overall receiver operation is controlled by operating the symbol synchronization circuit again. However, even when the lock detector 100 is not in the locked state or is determined to be in the locked state, but if the lock detector 100 is determined to be in the unlocked state, deterioration of the performance of the system is inevitable, so a careful design is required.

Next, in the present invention, when the input signal is a QPSK signal in the modulation method most widely used in general digital communication, the lock detector output characteristic may be expressed by Equation 5 below.

Unlike the BPSK signal, in the QPSK modulation scheme in which the input received signal is a complex signal, the use of a square root function is essential to calculate the absolute value of the input complex signal. However, it is difficult to implement a square root function in hardware in a real digital signal processor (DSP). Therefore, in order to calculate the square root function, an algorithm capable of approximating the square root function is required. Such algorithms are known as LS algorithm, sector algorithm and the like. In the present invention, the LS algorithm is employed to design a lock detector suitable for the QPSK signal. First, the LS algorithm calculates the square root function through simple approximation using Equation 6 below.

From here = Represents the absolute value of the larger of I or Q values, = Represents the absolute value of the smaller of I or Q values.

The error caused by the LS algorithm is about 4.3%, and FIG. 2 shows a lock detector block diagram for a QPSK signal using a comparator using the LS algorithm. In FIG. 2 the lock detector for the QPSK signal can be implemented simply by using a comparator 103, without the use of a complex square root function.

The lock detection method for a QPSK signal according to the present invention performs a two-sample operation per symbol by using a difference in the magnitude component of the zero crossing sample from the magnitude component of the complex signal sampled at the optimum point, similarly to the BPSK signal. When the square root function is applied to the LS algorithm to calculate the absolute value in Equation 5, there are two cases where the sample at each point depends on the magnitude of the absolute value of the I-channel and Q-channel signals as in Equation 6. For the output of the lock detector using two samples, a total of four cases occur as shown in Equation 7 below.

4 and 5 show the average and dispersion characteristics of the lock detector output according to the conventional scheme and the proposed scheme according to the timing error normalized to the symbol rate T. The roll-off parameter is 0.5 and Eb / No. Is 5dB and the observation interval is 64.

It can be seen from FIG. 4 that the lock detector according to the present invention satisfies the above-mentioned desirable output characteristics of the lock detector. That is, it can be seen that the output characteristic of the lock detector according to the present invention is a right function having a period of 0.5 with respect to the normalized timing error, and the integral value of one period becomes zero. 4, the B-type lock detector method (see B2 curve) using the square of the signal has a better average characteristic than the proposed method according to the present invention (see C2 curve) using the absolute value. In terms of the dispersion characteristics, it can be seen that the method according to the present invention (see C3, D3 curve) has a much more stable performance.

The lock detector according to the present invention has better characteristics than the conventional algorithm. The reason is that the method according to the present invention uses absolute values instead of squares. Because do not receive. Here, the signal-to-noise ratio (SNR) is the average of the detector outputs in the locked state. Dispersion when doing It is defined as

Detector output variance of the scheme according to the invention as shown in FIG. 5 Is very small compared to the existing algorithm. Therefore, also in the SNR of the detector, the scheme according to the present invention has better detector SNR characteristics than the conventional scheme (see C3, D3 curves).

In FIG. 6, the method according to the present invention (see C4 curve) and the existing method (see A4 and B4 curve) according to the present invention for the case where the roll-off parameter α is 0, 5 and the observation interval is 64 is shown. SNRz, the detector SNR, was compared. As shown in FIG. 6, the SNRz of the method according to the present invention has an improvement of about 3 dB or more compared to the A-type lock detector, and about 5 dB or more compared to the B-type lock detector when Eb / No is 5 dB. When No is 15dB, it can be seen that it improves more than 4dB compared with type A lock detector and more than 6dB compared with type B lock detector.

Next, in FIG. 7, the dispersion ratio in the locked state to the dispersion in the unlocked state between the respective schemes Is showing. Dispersion ratio of the scheme according to the invention as shown by curve C5 of FIG. Is smaller than curve B5 of the type B lock detector, but somewhat larger than curve A5 of the type A lock detector. However, if the required false lock probability Pf is not very small, then the variance ratio Is a very small value compared to SNRz. Therefore, the detection probability Pd has little effect. Therefore, the overall detection performance is hardly influenced by the dispersion ratio, so the performance of the scheme according to the present invention is not a big problem.

In Fig. 8, when the loop SNR of the symbol synchronization circuit is infinite (i.e., there is no influence of the timing jitter), the detection failure probability (1-Pf) of the lock detector according to the required false lock probability Pf is shown. Is showing. The observation section is 64 and Eb / N0 = 5 dB. 9 shows the probability of failure of the lock detector according to the observation interval M when the loop SNR is infinite.

As shown in Figs. 8 and 9, the method according to the present invention shows a very good detection performance compared to existing algorithms in the same false lock probability and observation interval. This is because the detector SNR of the algorithm according to the present invention is improved compared to the conventional algorithm as shown in FIG.

Finally, FIG. 10 shows the detection failure probability according to the roll-off parameter value of the pulse shaping filter. The observation section M was 64 and Pf was 10 ^-3 . Also in FIG. 10, according to the α value, the scheme according to the present invention shows much better detection performance than the conventional schemes. In addition, when the value of α increases, the average characteristic of each system increases, so that the probability of detection becomes better when the value of α increases between the same systems.

According to the present invention as described above, when determining the lock state of the symbol synchronization circuit of the digital receiver, since the processing by using the absolute value instead of the square of the signal can reduce the effect due to the noise involved in the processing of the entire receiver It has the effect of improving system performance and increasing reliability.

In addition, the present invention uses the same sample as the symbol synchronization circuit, thereby reducing the burden on processing speed, and does not require a high speed analog-to-digital converter, and can be implemented as a simple comparator, thereby reducing hardware complexity. have.

In addition, the present invention has an effect of reducing the number of bits and the amount of calculation required for digital signal processing by using an absolute value when determining the lock state of the symbol synchronization circuit of the digital receiver.

Claims (5)

Obtaining an absolute value of the BPSK signal for detecting the locked state of the symbol synchronization circuit; Accumulating the absolute value a predetermined number of times; Comparing the accumulated value with a set threshold value; And determining a lock state of the symbol synchronizing circuit according to the comparison value. The method of claim 1, wherein an absolute value of a signal for detecting a lock state of the symbol synchronization circuit is obtained by using the following equation. 2. The method of claim 1, wherein the symbol synchronization circuit is reactivated when the symbol synchronization circuit is in an unlocked state. Obtaining an absolute value by approximating a QPSK signal for detecting a locked state of a symbol synchronization circuit; Accumulating the absolute value a predetermined number of times; Comparing the accumulated value with a set threshold value; And determining a lock state of the symbol synchronizing circuit according to the comparison value. 5. The method of claim 4, wherein the approximation is performed using the following equation. From here, = Represents the absolute value of the larger of I or Q values, = Represents the absolute value of the smaller of I or Q values.