KR100316718B1 - Skew insensitive data receiver - Google Patents

Abstract

The present invention is directed to a data receiver capable of maximizing an effective sampling interval of data without being affected by skew between input data. The data receiver includes a voltage control delay stage for delaying input data for a predetermined time, a 90 ° phase delay stage for delaying the first delay signal output from the voltage control delay stage by 90 degrees corresponding to ¼ of a clock signal cycle, and a clock signal. A phase comparator capable of comparing the phase between the first delayed signal and the second delayed signals of the phase delay stage and resetting the signal; and generating a predetermined output in response to the output signal of the phase comparator, thereby delaying the voltage control delay stage. In a semiconductor memory device having a plurality of such data receivers, the first delay signal synchronized with a clock signal is set as sampled internal data, so that sampling occurs even if skew exists between input data. The skew is removed from the internal data.

Description

Skew insensitive data receiver

The present invention relates to a semiconductor integrated circuit, and more particularly, to a data receiver capable of maximizing an effective sampling interval of data without being affected by skew between input data.

BACKGROUND ART Synchronous DRAMs, which are widely used in recent years, input data into memory cells in synchronization with a clock or output memory cell data in a valid data window. The clock signal is input to one pin and distributed throughout the device. The clock signal arriving at a portion relatively far from the input pin can be significantly delayed with respect to the clock signal at the portion immediately adjacent to the input pin. This delay makes it difficult to maintain synchronization between the parts of the synchronous DRAM. Thus, a method of synchronizing clock signals using a delayed lock loop or a phase lock loop is used.

However, even when data is output in response to a clock signal synchronized by the clock synchronizing circuit, due to the physical distance difference between the data lines on which the output data are loaded, the data that is inevitably input first or late is inevitably received at the receiving side. Are present and skew occurs between them. This skew is especially valid for data input in response to rising and falling edges of the clock signal with 18 data pins with a bandwidth of 800 Mbps per data pin, such as RAMBUS DRAM. To make) smaller. In addition, in the case of data having large skew, the effective sampling interval may be out of range. Accordingly, there is a problem that the system operation is unstable due to skew between data in a memory system in which data is exchanged.

Therefore, there is a need for a method that can stabilize system operation by maximizing an effective sampling interval between these data even if skew exists between the data. Therefore, there is a need for a data receiver capable of maximizing the effective sampling interval between these data without being affected by skew between input data.

An object of the present invention is to provide a data receiver capable of maximizing the effective sampling interval of data without being affected by skew between input data.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a data receiver according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an operation timing diagram of FIG. 1.

3 is a diagram illustrating the phase detector of FIG. 1 in detail.

4 is a diagram illustrating an operation timing diagram of FIG. 3.

5 is a view showing in detail the charge pump unit of FIG.

6 is a diagram illustrating a transfer function between the phase comparator and the charge pump unit of FIG. 1.

The present invention provides a semiconductor memory device having a plurality of data receivers for receiving input data in synchronization with a clock signal, the data receiver comprising: a voltage control delay stage for delaying the input data by a predetermined time; A 90 ° phase delay stage for delaying the first delay signal, which is the output of the voltage control delay stage, by 90 ° phases corresponding to ¼ of the clock signal cycle; A phase comparator capable of comparing and resetting a phase between the clock signal, the first delayed signal, and second delayed signals which are outputs of the phase delay stage; And a charge pump unit configured to generate a predetermined output in response to the output signal of the phase comparator to vary the delay time of the voltage control delay stage, wherein the first delay signal synchronized with the clock signal is sampled. By setting the data, the skew is removed from the sampled internal data even though skew exists between the input data.

Preferably, the phase comparator generates a down signal as an output signal of the phase delay stage when the second delayed signal precedes the clock signal after the transition of the first delayed signal, and then moves up when the second delayed signal precedes the clock signal. The charge pump unit locks the average charge pumping current when the phase difference between the second delayed signal and the clock signal is 0, that is, when the phase difference between the clock signal and the first delayed signal is 90 °. (locking)

As such, the present invention can maximize the effective sampling interval by eliminating skew even if skew exists between the input data, thereby increasing the reliability of data transmission. In addition, system cost can be reduced because it can be solved in the data receiver of the present invention without the need for precise trimming or complex synchronization circuitry on the PCB board to reduce skew between input data.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements. The present invention is directed to a data receiver capable of eliminating this skew phenomenon even if skew exists between data inputted in a system where data is exchanged.

1 is a diagram illustrating a data receiver according to an embodiment of the present invention. 1 includes a plurality of data receivers 10, 11, and 12, and each data receiver 10, 11, 1 includes a clock for transmitting input data DATA_0, DATA_1, and DATA_N and a reception clock signal R_CLK. The clock signal clk1 generated in the buffer 2 is connected. For convenience of description, one data receiver 10 will be described.

The data receiver 10 outputs the voltage control delay stage 20 and the voltage control delay stage 20 for delaying the connected input data DATA_0 by a predetermined time according to the output voltage v_ctrl of the charge pump 70. 90 ° phase delay stage 30 for delaying d1) to the phase of 90 ° (T _clk / 4), output of voltage control delay stage 20, d1 and output of 90 ° phase delay stage 30, d2 A converter for converting the two complementary data (d1, / d1, d2, / d2) generated for each to one data to generate the first delay signal (d1_s) and the second delay signal (d2_s), respectively ( 40 and 50, the phase comparator 60 for comparing the phases of the clock signal clk1 with the first delay signal d1_s and the second delay signal d2_s, the output up signal UP of the phase comparator 60, and A charge pump 70 which generates an output voltage in response to the down signal DOWN and controls the delay time of the voltage control delay stage 20 connected to the output voltage, that is, the voltage control signal v_ctrl, and a clock signal. respond to (clk) Includes more than a first delay signal (d1_s) to latch the sampled output signal (Sampled DATA_0) D- flip-flop 80 for generating a.

Here, the voltage control delay stage 20 is a variable delay stage composed of a plurality of general inverter chains. When the output voltage v_ctrl of the charge pump 70 is increased, the delay time of the first delay signal d1 is gradually increased. In the direction of shortening, if it is lowered, the delay time of the first delay signal d1 is set to be longer. Alternatively, the reverse case may be set.

The operation of the data receiver 10 of FIG. 1 is shown in a timing diagram as shown in FIG. 2. FIG. 2 internally synchronizes the input data DATA_0 received in a phase different from that of the reception clock signal R_CLK with the clock signal clk1 and the second delayed signal d2_s, thereby allowing the clock signal clk1 and the first delayed signal. The phase difference from (d1_s) to 90 ° is shown by the operation. That is, the reception clock signal R_CLK generates the clock signal clk1 delayed by the delay time t _clkbuf of the clock buffer 2 (1). The received input data DATA_0 generates a first delay signal d1_s delayed by the variable delay time t _vcdl indicated by the voltage control delay stage 20 (②). Thereafter, the first delay signal d1_s generates a second delay time d2_s delayed by 90 ° phase (t ₉₀ = T _clk / 4) through the 90 ° phase delay end 30 (3). As a result, the second delay signal d2_s is synchronized with the clock signal clk1, and the first delay time d1_s is 90 ° ahead of the clock signal clk1.

Therefore, even though a plurality of input data DATA_0, DATA1, DATA_N (FIG. 1) are received with skew, the second delay signals (synchronized to the clock signal clk1 internally of the respective data receivers 10, 11, 12). Since d2_s is generated to generate the first delay time d1_s that is 90 ° ahead of the clock signal clk1, it is possible to prevent a reduction in the effective sampling interval caused by skew unlike in the prior art. In order to clearly support this operation, internal components of the data receiver 10 will be described in detail.

The phase comparator 60 is shown in FIG. 3 and has an odd number of inverters 61 connected in series with the clock signal clk1 in order to provide a predetermined pulse whenever there is a transition of the clock signal clk1. An exclusive negative OR (XNOR) 64 of the output of the data lines 62 and 63 generates the clock edge signal clk1_edge. Similarly, the first delayed edge signal d1_edge is generated for the first delayed signal d1_s, and the second delayed edge signal d2_edge is also generated for the second delayed signal d2_s.

The phase comparator 60 is composed of two flip-flop parts 65 and 66 and a reset part 67. Each flip-flop portion 65, 66 is a flip-flop that can be reset consisting of six transistors. The operation will be described in connection with the timing diagram of FIG. 4 showing the operation of the phase comparator 60. A second delay time d2_s is generated after a 90 ° phase delay t ₉₀ with respect to the first delay signal d1_s, and the first delay edge signal d1_edge is generated for each transition period of the first delay signal d1_s. The second delay edge signal d2_edge is generated for each transition period of the second delay signal d2_s.

If the reset signal provided by the reset unit 67 is a logic 'high level', the node NA in the flip-flop unit 65 becomes a logic 'low level', and the node NB becomes a logic 'high level' and the up signal ( UP) becomes a logic low level. In the flip-flop unit 66, the node NC becomes a logic low level, the node ND becomes a logic high level, and the down signal DOWN becomes a logic low level for a reset signal of logic 'high level'. 'Becomes. In response to any one of the node NB and the node ND of the logic 'high level' and in response to a pulse of the logic 'high level' of the first delayed edge signal d1_edge, the reset signal in the reset unit 67 may reset the logic ' Low level '(ⓐ).

The phase comparator 60 generates a down signal DOWN when the second delayed edge signal d2_egde precedes the clock edge signal clk1_edge when the reset signal resets to a logic 'low level'. Generate an up signal UP. That is, the node NC has a logic 'high level' with respect to the logic 'low level' of the second delayed edge signal d2_s. After that, in response to the node NC maintaining the logic 'high level' and the previous logic 'high level' of the second delay edge signal d2_s, the node ND has a logic 'low level' and the down signal DOWN has a logic 'high'. Level '(ⓑ). In response to the clock edge signal clk1_edge logic 'high level', the up signal UP becomes a logic 'high level' (©), and does not have a pulse width that is recognized as a signal. In the period where both the up signal UP and the down signal DOWN become logic 'high level', the PMOS transistors TP1 and TP2 of the reset unit 67 respond to this because the node NB and the node ND are logic 'low level'. ) Is 'turned on' so that the reset signal resets to a logic 'high level' (ⓓ). A reset signal of logic 'high level' makes the up signal UP and the down signal DOWN a logic 'low level'. Therefore, the phase comparator 60 has a second delay edge signal d2_edge prior to the clock delay signal clk1_edge while the reset signal resets to a logic 'low level' after the transition of the first delay signal d1_s. Therefore, a down signal DOWN is generated and then reset by a logic 'high level' reset signal.

Similarly, the phase comparator 60 has a second delay edge signal d2_edge behind the clock delay signal clk1_edge while the reset signal resets to a logic low level after the transition of the first delay signal d1_s. In this case, an up signal UP is generated and then reset by a logic 'high level' reset signal (ⓕⓖⓗⓘⓙ). In order to avoid duplication of explanation, detailed operation descriptions are omitted.

Since the phase comparator 60 has a short reset time, high-speed operation is possible and operation is performed only when there is a transition of input data, thereby reducing power consumption.

5 is a view showing the charge pump unit 70. Referring to this, the charge pump unit 70 charges and discharges the capacitor Cap in response to the up / down signal UP / DOWN of the phase comparator 60 described above. The charge pump unit 70 has a plurality of current mirrors, and is provided by a transistor MP2 in response to an up signal UP and a transistor MN2 in response to an inverted down signal / dn. The capacitor Cap is charged and discharged by quickly switching the transistors MP1 and MN1. The output voltage v_ctrl appearing on the capacitor Cap charged and discharged is used to adjust the delay time of the voltage control delay stage 20.

The transfer function of the phase comparator 60 of FIG. 3 and the charge pump unit 70 of FIG. 5 is shown in FIG. 6. In the graph of FIG. 6, the X axis represents the phase difference between the second delay signal d2_s and the clock signal clk1 in the phase comparator 60, and the Y axis represents the average charge pumping current in the charge pump unit 70. When the phase difference between the second delay time d2_s and the clock signal clk1 is 0, in other words, when the phase difference between the clock signal clk1 and the first delay signal d1_s is 90 °, the average charge pumping current is 0. This means that it is locked. Thus, at this time, the first delayed signal d1_s latched by the D-flip-flop 80 corresponding to the clock signal clk1 is output as the sampled output signal Sampled DATA_0.

This operation is also performed by the plurality of data receivers 10, 11, and 12 to convert the first delayed signal d1_s synchronized with the clock signal clk1 to the respective sampled output signals Sampled DATA_0, Sampled DATA_1, and Sampled DATA_N. Occurs. Therefore, even though there is skew between the input data DATA_0, DATA_1, and DATA_N received by the data receivers 10, 11 and 12, the sampled output signals generated by the data receivers 10, 11 and 12 are sampled. There is no skew between Sampled DATA_1 and Sampled DATA_N). Thus, it is possible to maximize the effective sampling interval by overcoming the phenomenon that the effective sampling interval is reduced in the conventional data transmission. Accordingly, the reliability of data transmission can be improved.

In addition, the data receiver of the present invention can reduce the system cost because it can be solved in the data receiver without the need for precise trimming or complex synchronization circuitry on the PCB board to reduce skew between the data.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the data receiver of the present invention described above, even if there is skew between the input data, the effective sampling period can be maximized by eliminating the skew, thereby increasing the reliability of data transmission.

In addition, system cost can be reduced because it can be solved in the data receiver of the present invention without the need for precise trimming or complex synchronization circuitry on the PCB board to reduce skew between input data.

Claims (3)

A semiconductor memory device having a plurality of data receivers for receiving input data in synchronization with a clock signal, the data receiver comprising: A voltage control delay stage for delaying the input data by a predetermined time; A 90 ° phase delay stage for delaying the first delay signal, which is the output of the voltage control delay stage, by 90 ° phases corresponding to ¼ of the clock signal cycle; A phase comparator capable of comparing and resetting a phase between the clock signal, the first delayed signal, and second delayed signals which are outputs of the phase delay stage; And A charge pump unit for generating a predetermined output in response to an output signal of the phase comparator to vary the delay time of the voltage control delay stage, The first delay signal synchronized with the clock signal is set as sampled internal data, so that skew is removed from the sampled internal data even though skew exists between the input data. The method of claim 1, wherein the phase comparator After the transition of the first delay signal, when the second delay signal precedes the clock signal, a down signal is generated as an output signal of the phase delay stage; Data receiver. According to claim 1, wherein the charge pump unit The average charge pumping current is locked when the phase difference between the second delayed signal and the clock signal is zero, that is, when the phase difference between the clocked signal and the first delayed signal is 90 °. .