KR100290485B1 - Clock cycle conversion circuit - Google Patents

Abstract

The present invention relates to a clock period converting circuit, and more particularly, to a clock period converting circuit capable of extending one reference clock period in a multiple of 2 or generating the original reference clock period.

The present invention provides a flip-flop means for inputting a clock signal, first logic means for outputting a first control signal according to an output signal and a clock period control signal of the flip-flop means, an output signal of the flip-flop means, and A second logic means for outputting a second control signal according to a clock signal, and a cycle of a clock signal output through an output terminal according to the output signals of the first and second logic means and the clock period control signal; Provided is a clock period converting circuit comprising an output means for outputting a clock signal that is twice the signal or a clock signal having the same period as the clock signal.

Description

Clock cycle conversion circuit

The present invention relates to a clock period converting circuit, and more particularly, to a clock period converting circuit capable of extending one reference clock period in a multiple of 2 or generating the original reference clock period.

In general, as the degree of integration of memory devices increases and high speed is required, mass storage devices having smaller design rules have been developed. These memory devices use clocks having different clock cycles in a program, erase, or read operation.

Therefore, the conventional circuit requires a clock generation circuit corresponding to each clock in order to generate different clock periods during a program, erase, or read operation of the memory device, which results in a complicated circuit.

Accordingly, an object of the present invention is to provide a clock period conversion circuit capable of eliminating the above-mentioned disadvantages by allowing one reference clock period to be extended in the form of a multiple of two or to generate the original reference clock period.

The clock cycle conversion circuit according to the present invention for achieving the above object comprises a flip-flop means for inputting a clock signal and a first control signal for outputting a first control signal according to an output signal and a clock period control signal of the flip-flop means. First logic means, second logic means for outputting a second control signal according to the output signal and the clock signal of the flip-flop means, and output signals of the first and second logic means and the clock cycle control signal And output means for outputting a period of a clock signal output through the output terminal as a clock signal having a period equal to twice the clock signal or a clock signal having the same period as the clock signal.

The present invention can generate a clock 2 ⁿ T having a period of a basic clock and various kinds of periods from one reference clock.

1 is a clock cycle conversion circuit diagram in accordance with the present invention.

2 is an input and output waveform diagram for explaining the present invention.

3 is an embodiment of a circuit configuration for generating various clock cycles by applying the present invention.

<Explanation of symbols for the main parts of the drawings>

1: flip-flop means 2, 3: first and second logic means

4: inverter 5: output means

P1 to P4: PMOS transistors

N1 and N2: NMOS Transistors

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a clock cycle converting circuit diagram according to the present invention, wherein a clock signal CLK is supplied to the flip-flop means 1. The output signal Q and the clock period control signal X1 of the flip-flop means 1 are supplied to the NAND gate, which is the first logic means 2, to output the first control signal X2. The output signal Q and the clock signal CLK of the flip-flop means 1 are supplied to the NAND gate which is the second logic means 3 to output the second control signal X2. The output signals X2 and X3 and the clock period control signal X1 of the first and second logic means 2 and 3 are supplied to the output means 5 and output through the output terminal OUT. The period of is outputted as a clock signal that is twice the clock signal or a clock signal having the same period as the clock signal.

The output means 5 includes a first PMOS transistor P1 and the first input terminal which input the clock period control signal X1 via the inverter 4 between the power supply terminal Vcc and the output terminal OUT. The second PMOS transistor P2 which receives the control signal X2 as an input is connected in series. Between the output terminal OUT and the ground terminal Vss, a first NMOS transistor N1 having the clock period control signal X1 as the input and a second NMOS transistor having the second control signal X3 as the input ( N2) is connected in series. Further, between the power supply terminal Vcc and the output terminal OUT, a third PMOS transistor P3 for inputting the clock period control signal X1 and a fourth PMOS for inputting the second control signal X3 are input. Transistor P4 is connected in series.

The operation of the clock period conversion circuit according to the present invention configured as described above will be described with reference to FIG.

According to the present invention, a clock signal whose period T is equal to or doubles the clock signal CLK according to the clock signal CLK and the clock period control signal X1 is output through the output terminal OUT.

For example, when the clock signal CLK and the clock period control signal X1 are both in a high state (t1 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1 that inputs the clock period control signal X1 through the inverter 4 is turned on, and the third PMOS transistor P3 is turned off. At this time, the output signal Q of the flip-flop means 1 which takes the clock signal CLK as an input becomes a low state. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1 respectively becomes a high state. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1 respectively becomes a high state.

Accordingly, the current pass formed by the third and fourth PMOS transistors P3 and P4 is disabled, and the current pass formed by the first and second PMOS transistors P1 and P2. Is enabled. At this time, the first and second NMOS transistors N1 and N2 which input the output signals X2 and X3 of the first and second logic means 2 and 3, respectively, are turned on. Therefore, the signal output through the output terminal OUT is output in the low state.

Subsequently, when the clock signal CLK is in a low state and the clock period control signal X1 is in a high state (t2 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1, which receives the clock period control signal X1 through the inverter 4, is turned on, and the third PMOS transistor P3 is turned off. At this time, the output signal Q of the flip-flop means 1 which takes the clock signal CLK as an input maintains a low state. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1, respectively, is kept high. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1, respectively, is kept high.

Accordingly, the current pass formed by the first and second PMOS transistors P1 and P2 and the current pass formed by the third and fourth PMOS transistors P3 and P4 are both disabled ( Disable). Therefore, the signal output through the output terminal (OUT) is kept low.

Subsequently, when the clock signal CLK becomes high again and the clock period control signal X1 is high (t3 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1, which receives the clock period control signal X1 through the inverter 4, is turned on, and the third PMOS transistor P3 is turned off. At this time, the output signal Q of the flip-flop means 1 which takes the clock signal CLK as an input becomes high. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1 respectively becomes a low state. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1, respectively, becomes a low state.

Accordingly, the current pass formed by the third and fourth PMOS transistors P3 and P4 is disabled, and the current pass formed by the first and second PMOS transistors P1 and P2. Is enabled. At this time, the first and second NMOS transistors N1 and N2 which input the output signals X2 and X3 of the first and second logic means 2 and 3, respectively, are turned off. Therefore, the signal output through the output terminal OUT is output in the high state.

Subsequently, when the clock signal CLK goes low again and the clock period control signal X1 is high (t4 time in FIG. 2), the operation will be described below.

The first PMOS transistor P1, which receives the clock period control signal X1 through the inverter 4, is turned on, and the third PMOS transistor P3 is turned off. At this time, the output signal Q of the flip-flop means 1 which receives the clock signal CLK is kept high. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1, respectively, is kept low. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1 respectively becomes a high state.

Accordingly, the current pass formed by the third and fourth PMOS transistors P3 and P4 is disabled, and the current pass formed by the first and second PMOS transistors P1 and P2 is Able to be. At this time, the first NMOS transistor N1, which inputs the output signal X2 of the first logic means 2, is turned on, but the input signal X3 of the second logic means 3 is input. 2 NMOS transistor N2 is turned off. Therefore, the signal output through the output terminal (OUT) is kept high.

Subsequently, when the clock signal CLK becomes high again and the clock period control signal X1 is high (t5 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1, which receives the clock period control signal X1 through the inverter 4, is turned on, and the third PMOS transistor P3 is turned off. At this time, the output signal Q of the flip-flop means 1 which takes the clock signal CLK as an input becomes low. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1 respectively becomes a high state. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1, respectively, is kept high.

Accordingly, the current pass formed by the first and second PMOS transistors P1 and P2 and the current pass formed by the third and fourth PMOS transistors P3 and P4 are both disabled ( Disable). At this time, both of the first and second NMOS transistors N1 and N2 which input the output signals X2 and X3 of the first and second logic means 2 and 3, respectively, are turned on. Therefore, the signal output through the output terminal OUT is output in the low state.

Subsequently, when the clock signal CLK becomes low again and the clock period control signal X1 is high (t6 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1, which receives the clock period control signal X1 through the inverter 4, is turned on, and the third PMOS transistor P3 is turned off. At this time, the output signal Q of the flip-flop means 1 which receives the clock signal CLK is kept low. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1, respectively, is kept high. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1, respectively, is kept high.

Accordingly, the current pass formed by the first and second PMOS transistors P1 and P2 and the current pass formed by the third and fourth PMOS transistors P3 and P4 are both disabled ( Disable). At this time, both of the first and second NMOS transistors N1 and N2 which input the output signals X2 and X3 of the first and second logic means 2 and 3, respectively, are turned on. Therefore, the signal output through the output terminal (OUT) is kept low.

Subsequently, when the clock signal CLK becomes high again and the clock period control signal X1 is high (t7 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1, which receives the clock period control signal X1 through the inverter 4, is turned on, and the third PMOS transistor P3 is turned off. At this time, the output signal Q of the flip-flop means 1 which takes the clock signal CLK as an input becomes high. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1 respectively becomes a low state. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1, respectively, becomes a low state.

Accordingly, the current pass formed by the third and fourth PMOS transistors P3 and P4 is disabled, and the current pass formed by the first and second PMOS transistors P1 and P2 is Able to be. At this time, the first and second NMOS transistors N1 and N2 which input the output signals X2 and X3 of the first and second logic means 2 and 3, respectively, are turned off. Therefore, the signal output through the output terminal OUT is output in the high state.

Subsequently, when both the clock signal CLK and the clock period control signal X1 go low (time t8 in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1 that receives the clock period control signal X1 through the inverter 4 is turned off, and the third PMOS transistor P3 is turned on. At this time, the output signal Q of the flip-flop means 1 which receives the clock signal CLK is kept high. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1 respectively becomes a high state. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1 respectively becomes a high state.

Accordingly, the current pass formed by the first and second PMOS transistors P1 and P2 and the current pass formed by the third and fourth PMOS transistors P3 and P4 are both disabled ( Disable). At this time, both of the first and second NMOS transistors N1 and N2 which input the output signals X2 and X3 of the first and second logic means 2 and 3, respectively, are turned on. Therefore, the signal output through the output terminal OUT goes low.

Subsequently, when the clock signal CLK becomes high again and the clock period control signal X1 is low (t9 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1 that receives the clock period control signal X1 through the inverter 4 is turned off, and the third PMOS transistor P3 is turned on. At this time, the output signal Q of the flip-flop means 1 which receives the clock signal CLK is kept high. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1, respectively, is kept high. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1, respectively, becomes a low state.

Thus, current paths formed by the third and fourth PMOS transistors P3 and P4 are enabled, and current paths formed by the first and second PMOS transistors P1 and P2 are disabled. At this time, the first NMOS transistor N1, which inputs the output signal X2 of the first logic means 2, is turned on, but the input signal X3 of the second logic means 3 is input. 2 NMOS transistor N2 is turned off. Therefore, the signal output through the output terminal OUT is output in the high state.

Subsequently, when the clock signal CLK becomes low again and the clock period control signal X1 is low (t10 time in FIG. 2), the operation will be described as follows.

The first PMOS transistor P1 that receives the clock period control signal X1 through the inverter 4 is turned off, and the third PMOS transistor P3 is turned on. At this time, the output signal Q of the flip-flop means 1 which receives the clock signal CLK is kept high. Therefore, the output signal X2 of the first logic means 2 which inputs the clock period control signal X1 and the output signal Q of the flip-flop means 1, respectively, is kept high. In addition, the output signal X3 of the second logic means 3 which inputs the clock signal CLK and the output signal Q of the flip-flop means 1 respectively becomes a high state.

Thus, both the current paths formed by the first and second PMOS transistors P1 and P2 and the current paths formed by the third and fourth PMOS transistors P3 and P4 are disabled. At this time, the first and second NMOS transistors N1 and N2 which input the output signals X2 and X3 of the first and second logic means 2 and 3, respectively, are turned on. Therefore, the signal output through the output terminal OUT is output in the low state.

That is, when the clock period control signal X1 is in the high state, the flip-flop means 1 toggles the output signal Q inverted at each high edge of the clock signal CLK. the output signal Q of the flip-flop means 1 has a period twice that of the clock signal CLK, and the output signal X2 of the first logic means 2 The output signal Q has an inverted value.

When the output signal Q of the flip-flop means 1 is in a high state, the output signal X2 of the first logic means 2 is in a low state and the first NMOS transistor N1 is turned off. At this time, since the current pass formed by the third and fourth PMOS transistors P3 and P4 is disabled, the output is independent of the output signal X3 of the second logic means 3. The signal output through the terminal OUT goes high.

On the contrary, if the output signal Q of the flip-flop means 1 is in the low state, the output signals X2 and X3 of the first and second logic means 2 and 3 are both in a high state and the first And the second NMOS transistors N1 and N2 are turned on. Therefore, the output terminal OUT is outputted in a low state by forming a current path through the first and second NMOS transistors N1 and N2 to the ground terminal Vss. Therefore, when the clock period control signal X1 is high, the signal output through the output terminal OUT becomes equal to the period of the output signal Q of the flip-flop means 1. That is, since the period of the output signal Q of the flip-flop means 1 is twice the period of the clock signal CLK, the signal period output through the output terminal OUT is the period of the clock signal CLK period. It becomes 2 times (2T) (t1-t5 time of FIG. 2).

On the other hand, when the clock period control signal X1 is in the low state, the output signal Q of the flip-flop means 1 is kept high and the output signal X2 of the first logic means 2 is maintained. ) Will remain high. Therefore, the signal period output through the output terminal OUT is output in synchronization with the same period T as the clock signal CLK (t8 to t10 time in FIG. 2).

3 is a diagram illustrating an embodiment of a circuit configuration for generating various clock cycles by applying the present invention.

Each of the blocks 11 to N operates to have a period 2T equal to or twice the period T of the input clock signal according to the clock period control signal X1. The period of the final output OUTCLK is determined according to the number of clock period control signals X1 in the high state. Therefore, the period Tout of the final output OUTCLK is Tout = ²ⁿ × T. Here, T is a clock period and n is the number of clock period control signals X1 in a high state. Therefore, by controlling the clock period control signal X1, a clock signal of a desired period can be obtained.

The present invention described above can be variously substituted, modified and changed within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains and the accompanying drawings. It is not limited to.

As described above, according to the present invention, one reference clock period can be extended in a multiple of 2 or the original reference clock period can be generated to separately use a clock generation circuit corresponding to a clock having each period in the circuit design. There is no need to have an excellent effect to optimize the circuit.

Claims (5)

Flip-flop means for inputting a clock signal; First logic means for outputting a first control signal in accordance with an output signal of the flip-flop means and a clock period control signal; Second logic means for outputting a second control signal in accordance with an output signal and a clock signal of the flip-flop means; A clock signal having a period equal to that of the clock signal or a clock signal that is doubled as the clock signal by a period of a clock signal output through an output terminal according to the output signal of the first and second logic means and the clock period control signal. Clock cycle conversion circuit comprising an output means for outputting to. The method of claim 1, And said first logic means comprises a NAND gate as an input of an output signal and a clock period control signal of said flip-flop means, respectively. The method of claim 1, And the second logic means comprises a NAND gate that receives an output signal and a clock signal of the flip-flop means, respectively. The method of claim 1, The output means is connected between a power supply terminal and an output terminal in series and includes first and second PMOS transistors for inputting the clock period control signal and the first control signal through an inverter, respectively; First and second NMOS transistors connected in series between the output terminal and the ground terminal and inputting the clock period control signal and the second control signal, respectively; And a third and a fourth PMOS transistor connected in series between the power supply terminal and the output terminal and configured to input the clock period control signal and the second control signal, respectively. The method of claim 1, A plurality of clock period conversion circuits are connected in series so that the final output period of the clock period conversion circuit is determined by Equation 1 according to the number of high state input signals of the clock period control signal. Clock cycle conversion circuit.