KR100299560B1 - 리드프레임리드와도전성트레이스를조합한고밀도집적회로어셈블리 - Google Patents
리드프레임리드와도전성트레이스를조합한고밀도집적회로어셈블리 Download PDFInfo
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- KR100299560B1 KR100299560B1 KR1019960706590A KR19960706590A KR100299560B1 KR 100299560 B1 KR100299560 B1 KR 100299560B1 KR 1019960706590 A KR1019960706590 A KR 1019960706590A KR 19960706590 A KR19960706590 A KR 19960706590A KR 100299560 B1 KR100299560 B1 KR 100299560B1
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- Prior art keywords
- chip
- substrate
- conductive
- electrically
- conductive traces
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- 239000000758 substrate Substances 0.000 claims abstract description 74
- 229910000679 solder Inorganic materials 0.000 claims abstract description 22
- 239000004020 conductor Substances 0.000 claims abstract 3
- 230000008878 coupling Effects 0.000 claims abstract 3
- 238000010168 coupling process Methods 0.000 claims abstract 3
- 238000005859 coupling reaction Methods 0.000 claims abstract 3
- 238000009429 electrical wiring Methods 0.000 claims description 11
- 239000011810 insulating material Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
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Abstract
Description
Claims (13)
- a) 제 1 표면상에 소정 어레이의 전기 도전성 트레이스가 형성된 절연기판;b) 상기 기판에 의해 지지되며, 상기 도전성 트레이스로부터 전기적으로 절연된 복수의 리드프레임 리드;c) 상기 기판에 의해 상기 제 1 표면상에 지지되며, 일련의 입/출력 패드를 구비하는 IC 칩; 및d) 상기 IC 칩이 상기 도전성 트레이스 및 리드프레임 리드를 통해 소정의 방식으로 외부 소자에 접속될 수 있도록, 상기 IC 칩의 입/출력 패드 중 소정의 패드를 상기 도전성 트레이스 각각에 각각 전기적으로 접속시키는 일련의 제 1 본딩 와이어, 및 상기 IC 칩의 입/출력 패드 중 다른 패드를 상기 리드프레임 리드 각각에 각각 전기적으로 접속시키는 일련의 제 2 본딩 와이어를 구비하며,e) 상기 기판은, 적어도 상기 IC 칩과 상기 리드프레임 리드를 지지하는 제 1 표면, 및 제 2 반대 표면을 더 구비하며, 상기 기판은, 또한 소정 위치에서 상기 제 2 표면에 부착된 복수의 연장된 전도성 부재를 더 구비하며,상기 도전성 트레이스는 상기 제 1 표면으로부터 상기 제 2 표면까지 연장되며, 상기 도전성 트레이스 각각은 상기 연장된 전도성 부재 중 관련된 부재에 전기적으로 접속되어 있는 것을 특징으로 하는 집적회로 어셈블리.
- 제1항에 있어서, 상기 연장된 부재는 상기 제 2 표면에 소정의 그리드 어레이로 부착되어 있는 것을 특징으로 하는 집적회로 어셈블리.
- 제1항에 있어서, 상기 연장된 부재 각각은 솔더 칼럼인 것을 특징으로 하는 집적회로 어셈블리.
- 제1항에 있어서, 상기 연장된 부재 각각은 부착핀인 것을 특징으로 하는 집적회로 어셈블리.
- a) 소정 어레이의 도전성 트레이스를 구비하는 절연기판으로서, 대향하는 제 1 표면 및 제 2 표면을 더 구비하여 상기 도전성 트레이스가 상기 제 1 표면으로부터 상기 제 2 표면까지 연장되고, 상기 제 2 표면의 소정 위치에 부착되는 복수의 연장 부재를 또한 더 구비하며, 상기 각 연장 부재가 상기 도전성 트레이스 각각에 전기적으로 접속되어 있는, 상기 절연기판;b) 상기 기판의 상기 제 1 표면에 의해 지지되는 복수의 리드프레임 리드로서, 상기 복수의 리드프레임 리드 중 적어도 일부가 상기 도전성 트레이스 상에 놓이는, 상기 복수의 리드프레임 리드;c) 상기 기판의 상기 제 1 표면상에 지지되며, 일련의 입/출력 패드, 하나 이상의 전력단자 및 하나 이상의 접지단자를 구비하는 IC 칩;d) 상기 IC 칩의 상기 입/출력 패드 중 소정의 패드를 상기 제 1 표면상의 상기 도전성 트레이스 각각에 전기적으로 접속시키는 일련의 제 1 본딩 와이어, 및 상기 IC 칩의 입/출력 패드 중 소정의 다른 패드를 상기 제 1 표면상의 상기 리드프레임 리드 각각에 전기적으로 접속시키는 일련의 제 2 본딩 와이어;e) 상기 기판 상에 서로에 대해 스택된 관계로 위치되며 상기 리드프레임 리드 중 적어도 일부 위에 놓여지며, 전력면 또는 접지면으로서 각각 선택적으로 기능하는 제 1 및 제 2 전기 도전층;f) 상기 도전층을 서로 전기적으로 절연시키고, 그 아래의 상기 리드프레임 리드로부터도 전기적으로 절연시키는 수단; 및g) 상기 제 1 및 제 2 도전층을 특정한 상기 리드프레임 리드 또는 상기 도전성 트레이스에 전기적으로 접속시키고, 상기 제 1 및 제 2 도전층을 상기 IC 칩상의 각 전력단자 및 접지단자에 전기적으로 접속시킴으로써, 상기 IC 칩의 전기적인 배선을 위한 전력면 및 접지면을 제공하는 수단을 구비하는 것을 특징으로 하는 집적회로 어셈블리.
- 제5항에 있어서, 상기 연장 부재 각각은 솔더 칼럼인 것을 특징으로 하는 집적회로 어셈블리.
- 제5항에 있어서, 상기 연장 부재 각각은 부착핀인 것을 특징으로 하는 집적회로 어셈블리.
- a) 소정 어레이의 전기 도전성 트레이스를 구비하고, 상기 도전성 트레이스가 제 1 표면으로부터 제 2 표면까지 확장되도록 대향하는 제 1 표면 및 제 2 표면을 더 구비하며, 각 연장 부재가 상기 도전성 트레이스 각각에 전기적으로 접속되도록 소정 위치에서 상기 제 2 표면에 부착된 복수의 연장 부재를 더 구비하는 절연기판;b) 상기 기판의 상기 제 1 표면에 의해 지지되며, 적어도 일부가 상기 도전성 트레이스 상에 놓여지는 복수의 리드프레임 리드;c) 상기 기판의 제 1 표면상에 지지되며, 일련의 입/출력 패드, 하나 이상의 전력단자, 및 하나 이상의 접지단자를 구비하는 IC 칩;d) 상기 IC 칩을 소정 방식으로 외부에 전기적으로 접속시키기 위하여 상기 IC 칩의 임의의 입/출력 패드를 상기 제 1 표면상의 상기 도전성 트레이스에 각각 전기적으로 접속시키는 제 1 어레이의 본딩 와이어 및 상기 IC 칩의 다른 입/출력 패드를 상기 제 1 표면상의 상기 리드프레임 리드에 각각 전기적으로 접속시키는 제 2 어레이의 본딩 와이어;e) 상기 기판 상에서 상호간에 스택 형태로 위치되어 상기 리드프레임 리드의 적어도 일부상에 놓여지고, 전력면 및 접지면으로 각각 선택적으로 기능하는 제 1 및 제 2 도전층;f) 상기 제 1 및 제 2 도전층을 서로 전기적으로 절연시키고 또한 그 아래의 상기 리드프레임 리드와 전기적으로 절연시키며, 상기 도전층을 서로 결합시키고 또한 상기 기판과 결합시키는 절연 수단;g) 상기 IC 칩의 전기적 상호접속을 위해 소정의 전력면 및 접지면을 제공하도록 상기 제 1 및 제 2 도전층을 특정한 상기 리드프레임 리드 또는 상기 도전성 트레이스에 전기적으로 접속시키는 일련의 제 1 본딩 와이어 및 상기 제 1 및 제 2 도전층을 상기 IC 칩상의 소정 전력단자 또는 접지단자에 전기적으로 접속시키는 일련의 제 2 본딩 와이어; 및h) 상기 집적회로 어셈블리의 적어도 일부를 캡슐화하는 절연재료를 구비하는 것을 특징으로 하는 집적회로 어셈블리.
- 제8항에 있어서, 상기 연장 부재 각각은 솔더 컬럼인 것을 특징으로 하는 집적회로 어셈블리.
- 제8항에 있어서, 상기 연장 부재 각각은 부착핀인 것을 특징으로 하는 집적회로 어셈블리.
- a) 소정 어레이의 전기 도전성 트레이스를 구비하고, 상기 도전성 트레이스가 제 1 표면에서 제 2 표면까지 확장되도록 대향하는 제 1 표면 및 제 2 표면을 더 구비하며, 각 부재가 상기 도전성 트레이스 각각에 전기적으로 접속되도록 그리드 어레이로 상기 제 2 표면에 부착된 복수의 연장 부재를 더 구비하 절연기판;b) 상기 기판의 상기 제 1 표면에 의해 지지되며, 적어도 일부가 상기 도전성 트레이스 상에 놓여지는 복수의 리드프레임 리드;c) 상기 기판의 제 1 표면상에서 지지되며, 일련의 입/출력 패드를 구비하며 부가 단자를 더 구비하는 IC 칩;d) 상기 IC 칩의 입/출력 패드 중 소정의 패드를 상기 제 1 표면의 상기 도전성 트레이스에 각각 전기적으로 접속시키는 제 1 어레이의 본딩 와이어 및 상기 IC 칩의 입/출력 패드 중 다른 패드를 상기 제 1 표면상의 상기 리드프레임 리드에 각각 전기적으로 접속하는 제 2 어레이의 본딩 와이어;e) 상기 기판 상에서 상호간에 스택 형태로 위치하고 상기 리드프레임 리드의 적어도 일부 위에 놓여지며 소정의 회로설계에 따라 상기 IC 칩에 각각 소정의 전기 접속용 전도면으로서 선택적으로 기능하는 제 1 및 제2 도전층;f) 상기 제 1 제 2 도전층을 서로 전기적으로 절연시키고 또한 그 아래의 상기 리드프레임 리드와 전기적으로 절연시키며, 상기 도전층을 서로 결합시키고 또한 기판과 결합시키는 절연 수단;g) 상기 IC 칩의 소정의 전기적 상호접속을 제공하기 위해 상기 제 1 및 제 2 도전층을 특정한 상기 리드프레임 리드 또는 상기 도전성 트레이스에 전기적으로 접속시키는 일련의 제 1 본딩 와이어 및 상기 제 1 및 제 2 도전층을 상기 IC 칩상의 상기 부가 단자에 전기적으로 접속시키는 일련의 제 2 본딩 와이어; 및h) 상기 집적회로 어셈블리의 적어도 일부를 캡슐화하는 절연재료를 구비하는 것을 특징으로 하는 집적회로 어셈블리.
- 제11항에 있어서, 상기 연장 부재 각각은 솔더 컬럼인 것을 특징으로 하는 집적회로 어셈블리.
- 제11항에 있어서, 상기 연장 부재 각각은 부착핀인 것을 특징으로 하는 집적회로 어셈블리.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/406,726 US5569955A (en) | 1994-09-16 | 1995-03-20 | High density integrated circuit assembly combining leadframe leads with conductive traces |
US08/406,726 | 1995-03-20 | ||
PCT/US1996/003770 WO1996029737A1 (en) | 1995-03-20 | 1996-03-20 | A high density integrated circuit assembly combining leadframe leads with conductive traces |
Publications (2)
Publication Number | Publication Date |
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KR970703617A KR970703617A (ko) | 1997-07-03 |
KR100299560B1 true KR100299560B1 (ko) | 2001-11-22 |
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KR1019960706590A KR100299560B1 (ko) | 1995-03-20 | 1996-03-20 | 리드프레임리드와도전성트레이스를조합한고밀도집적회로어셈블리 |
Country Status (5)
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US (1) | US5569955A (ko) |
EP (1) | EP0760164B1 (ko) |
KR (1) | KR100299560B1 (ko) |
DE (1) | DE69618872T2 (ko) |
WO (1) | WO1996029737A1 (ko) |
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US5854512A (en) * | 1996-09-20 | 1998-12-29 | Vlsi Technology, Inc. | High density leaded ball-grid array package |
US5859801A (en) * | 1997-03-28 | 1999-01-12 | Siemens Aktiengesellschaft | Flexible fuse placement in redundant semiconductor memory |
EP0930653B1 (en) * | 1998-01-13 | 2008-06-11 | Lucent Technologies Inc. | High frequency semiconductor device |
TW434760B (en) * | 1998-02-20 | 2001-05-16 | United Microelectronics Corp | Interlaced grid type package structure and its manufacturing method |
KR100290784B1 (ko) | 1998-09-15 | 2001-07-12 | 박종섭 | 스택 패키지 및 그 제조방법 |
US6261869B1 (en) * | 1999-07-30 | 2001-07-17 | Hewlett-Packard Company | Hybrid BGA and QFP chip package assembly and process for same |
US6391687B1 (en) * | 2000-10-31 | 2002-05-21 | Fairchild Semiconductor Corporation | Column ball grid array package |
US7315000B2 (en) * | 2003-07-27 | 2008-01-01 | Sandisk Il Ltd. | Electronic module with dual connectivity |
US7741158B2 (en) * | 2006-06-08 | 2010-06-22 | Unisem (Mauritius) Holdings Limited | Method of making thermally enhanced substrate-base package |
US8786063B2 (en) * | 2009-05-15 | 2014-07-22 | Stats Chippac Ltd. | Integrated circuit packaging system with leads and transposer and method of manufacture thereof |
DE102014111931B4 (de) * | 2014-08-20 | 2021-07-08 | Infineon Technologies Ag | Niederinduktive Schaltungsanordnung mit Laststromsammelleiterbahn |
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- 1996-03-20 EP EP96911346A patent/EP0760164B1/en not_active Expired - Lifetime
- 1996-03-20 KR KR1019960706590A patent/KR100299560B1/ko not_active IP Right Cessation
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---|---|---|---|---|
JPH05283460A (ja) * | 1992-04-02 | 1993-10-29 | Shinko Electric Ind Co Ltd | 半導体装置 |
JPH0697307A (ja) * | 1992-09-16 | 1994-04-08 | Hitachi Ltd | 半導体集積回路装置 |
Also Published As
Publication number | Publication date |
---|---|
DE69618872T2 (de) | 2002-11-28 |
EP0760164A1 (en) | 1997-03-05 |
EP0760164B1 (en) | 2002-01-30 |
DE69618872D1 (de) | 2002-03-14 |
US5569955A (en) | 1996-10-29 |
WO1996029737A1 (en) | 1996-09-26 |
KR970703617A (ko) | 1997-07-03 |
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