KR100294639B1 - A cache apparatus for multi-access - Google Patents

Abstract

PURPOSE: A multiple access cache device is provided to read multiple units of sequential commands and data at a predesignated prefetch buffer at one time, to enable one processing block to make an access to while other processing block is processing the commands and the data stored in the prefetch buffer, and to prevent a cache access collision by using an interface block so it can enable a plurality of processing blocks to share one cache. CONSTITUTION: The device comprises a cache memory(100), a plurality of processing blocks(106, 107, 108, 109), a cache controller(101), a plurality of prefetch buffers(102, 103, 104, 105), and an address and data selector(110). The cache memory(100) stores commands and data. The processing blocks(106, 107, 108, 109) makes an access to the data stored in the cache memory(100) and performs corresponding process operations. The cache controller(101) prevents a cache access collision among the processing blocks(106, 107, 108, 109). The prefetch buffers stores the data read from the cache memory(100) and outputs the data to the processing blocks(106, 107, 108, 109). The selector(110) outputs the address and data of each processing block(106, 107, 108, 109) to the cache memory(100) in response to a control signal of the cache controller(101). The prefetch buffers(102, 103, 104, 105) store the data read from the cache memory, and enables the processing blocks(106, 107, 108, 109) to process the data though not accessing the cache memory(100) for a plurality of cycles.

Description

A cache apparatus for multi-access

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to microprocessors and, more particularly, to cache devices capable of multi-access processing.

As is well known, cache devices cannot employ many because of the area occupied by RAM and peripheral logic, but are indispensable in the implementation of high performance microprocessors for fast access to instructions and data.

In accordance with the recent trend of high integration of high-performance systems (microprocessors or microcontrollers), not only a cache device but also several processing blocks executed by instructions are integrated in one chip, and cached by several processing blocks. It happens that memory is accessed at the same time.

In this case, the conventional cache device supports one read / write port so that multiple accesses are not possible to implement multiple ports or use another cache memory. Such a method may be used for decoding and related implementation. The addition of logic increases the overall chip area.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the object of the present invention is to provide a multiple access cache apparatus capable of multiple access operations by various processing blocks and improving an area with an optimal implementation.

1 is a block diagram conceptually illustrating a multiple access cache device of the present invention;

* Description of the main parts of the drawing

100: cache memory 101: cache controller

102 to 105: prefetch buffer

106 to 109: processing block

110: address and data multiplexer

113: access conflict resolver

The present invention for achieving the above object is a cache memory for storing data; A plurality of processing means for accessing data stored in the cache memory to perform respective processing operations; A cache controller for preventing a cache access collision between the respective processing means for accessing the cache memory; A plurality of prefetch buffering means for storing data read from the cache memory and outputting the data to the processing means; And address and data selecting means for outputting address and data output from each processing means to the cache memory in response to a control signal output from the cache controller, wherein the prefetch buffering means comprises: the cache memory; A plurality of data is received from and stored by the processing block to process the data without accessing the cache memory for a plurality of cycles.

The present invention also provides a cache memory for storing instructions; A plurality of processing means for accessing instructions stored in the cache memory to perform respective processing operations; A cache controller for preventing a cache access collision between the respective processing means for accessing the cache memory; A plurality of prefetch buffering means for storing instructions read from the cache memory and outputting the instructions to the processing means; And address selection means for outputting an address output from each processing means to the cache memory in response to a control signal output from the cache controller, wherein the prefetch buffering means comprises a plurality of instructions from the cache memory. The input block stores and processes the instruction without accessing the cache memory for multiple cycles.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, when instructions or data stored in a cache have a sequential property, a plurality of units are read into a prefetch buffer at a time to process information in one processing block in the prefetch buffer. Configure other processing blocks to access the cache during the process, and also set up an interface block that can resolve conflicts and send and receive access signals between caches and processing blocks to avoid cache access conflicts. Blocks share a single cache so that they can use it efficiently.

1 is a block diagram conceptually illustrating a multiple access cache apparatus according to an exemplary embodiment of the present invention, wherein the cache memory 100 storing data or instructions and the data or instructions stored in the cache memory 100 are accessed respectively. Between the first, second, third and fourth processing blocks 106, 107, 108, 109 and each processing block 106, 107, 108, 109 accessing the cache memory 100 to perform a processing operation of the memory. First, second, third and fourth prefetch buffers 102 and 103 which store data or instructions read from the cache memory 101 and the cache memory 100 that serve as interfaces to prevent cache access conflicts of the cache. , 104, 105, and an address and data multiplexer 110 for sending an address or data output from the processing block to the cache memory 100 in response to a control signal output from the cache controller 101.

Specifically, the cache memory 100 is a data cache or an instruction cache, and outputs the stored contents to each prefetch buffer in response to a control signal output from the cache controller 101.

The first, second, third and fourth processing blocks 106 to 109 each request a request 111 to the cache controller 101 to access the cache memory 100 and write an instruction or data. And wait for an acknowledgment 112 signal from the cache controller 101. Subsequently, an access operation for the cache requested by each processing block is processed, and when necessary instructions or data arrive at the prefetch buffers 102 to 105, the instructions or data in the prefetch buffers 102 to 105 are read and used. Here, since the sizes of the prefetch buffers 102 to 105 are larger than the size of one instruction or data, the instruction or data may be processed without accessing the cache for several cycles, in which another processing block accesses the cache. Will be performed.

Next, the cache controller 101 determines an access conflict resolver which determines which processing block to first access the cache access requests of the various processing blocks 106 to 109 according to the priority. And the cache access rank according to the state or use urgency of each processing block, and then send a control signal to the cache memory 100 to read an instruction or data and at the same time recognize the signal 112 in the corresponding block. To generate an instruction or data from the cache memory 100 in a prefetch buffer corresponding to the corresponding processing block.

Next, the address and data multiplexer 110 selects the address or data provided to the cache memory 100 in response to the selection signal generated by the access conflict resolution unit 113 for the address or data generated in the various blocks. . In this case, the data multiplexer is not necessary in the case of the instruction cache.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention made as described above enables the multiple access operation of the cache memory at the same speed as the conventional cache device, and also enables the implementation of a highly integrated and high performance cache device by reducing the implementation area of the cache device for the multiple access. do.

Claims (6)

A cache memory for storing data; A plurality of processing means for accessing data stored in the cache memory to perform respective processing operations; A cache controller for preventing a cache access collision between the respective processing means for accessing the cache memory; A plurality of prefetch buffering means for storing data read from the cache memory and outputting the data to the processing means; And Address and data selection means for outputting the address and data output from each processing means to the cache memory in response to a control signal output from the cache controller, The prefetch buffering means, And receiving and storing a plurality of data from the cache memory so that the processing block can process data without accessing the cache memory for a plurality of cycles. The method of claim 1, wherein the processing means, And transmitting a request signal to the cache controller for data access, receiving a recognition signal from the cache controller, and reading and processing data from the prefetch buffering means. The method of claim 1, wherein the cache controller, Access conflict resolution means for determining an access order according to the priority of the cache access request of each processing means; Multiple access data cache device comprising a. A cache memory for storing instructions; A plurality of processing means for accessing instructions stored in the cache memory to perform respective processing operations; A cache controller for preventing a cache access collision between the respective processing means for accessing the cache memory; A plurality of prefetch buffering means for storing instructions read from the cache memory and outputting the instructions to the processing means; And Address selection means for outputting the address output from each processing means to the cache memory in response to a control signal output from the cache controller, The prefetch buffering means, And receiving and storing a plurality of instructions from the cache memory so that the processing block can process the instructions without accessing the cache memory for a plurality of cycles. The method of claim 4, wherein the processing means, And a request signal to the cache controller for command access, a recognition signal from the cache controller, and a command read from the prefetch buffering means for processing. The method of claim 4, wherein the cache controller, Access conflict resolution means for determining an access order according to the priority of the cache access request of each processing means; Multiple access instruction cache device comprising a.

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