KR100283047B1 - Surface planarization method using double resist coating - Google Patents
Surface planarization method using double resist coating Download PDFInfo
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- KR100283047B1 KR100283047B1 KR1019980056649A KR19980056649A KR100283047B1 KR 100283047 B1 KR100283047 B1 KR 100283047B1 KR 1019980056649 A KR1019980056649 A KR 1019980056649A KR 19980056649 A KR19980056649 A KR 19980056649A KR 100283047 B1 KR100283047 B1 KR 100283047B1
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000000576 coating method Methods 0.000 title claims abstract description 22
- 239000011248 coating agent Substances 0.000 title claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 79
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 28
- 238000005137 deposition process Methods 0.000 claims abstract description 21
- 238000000206 photolithography Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 3
- 238000005452 bending Methods 0.000 claims abstract 2
- 238000000151 deposition Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
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Abstract
본 발명은 칩의 표면을 평탄하게 하기 위한 표면 평탄화 방법에 관한 것으로, 특히 다른 코팅 조건을 갖는 포토레지스트를 이용하여 용이하게 평탄화를 수행하기 위한 이중 레지스트 코팅을 이용한 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface planarization method for planarizing a surface of a chip, and more particularly, to a planarization method using a double resist coating for easily planarization using photoresists having different coating conditions.
이를 위해 본 발명은 패턴(11)이 형성된 기판(10) 상에 SiO₂ 층(12)을 형성하는 SiO₂ 증착 공정, 상기 형성된 SiO₂층(12) 상에 점도가 높은 포토레지스트로 포토레지스트층(13)을 형성하는 제1 포토레지스트 증착 공정, 상기 제1 포토레지스트층(13) 중 상기 패턴(11)에 의해 굴곡이 형성된 부분의 포토레지스트층(14)을 사진 식각하여 제거하는 사진 식각 공정, 상기 사진 식각에 의해 형성된 SiO₂층(12)과 포토레지스트층(13) 사이의 공간을 점도가 낮은 포토레지스트로 증착하는 제2 포토레지스트 증착 공정로 이루어진다.To this end, in the present invention, the SiO2 deposition process of forming the SiO2 layer 12 on the substrate 10 on which the pattern 11 is formed, the photoresist layer 13 as a photoresist having a high viscosity on the formed SiO₂12 12 A first photoresist deposition process of forming a photoresist, a photolithography process of photo-etching and removing the photoresist layer 14 of the portion of the first photoresist layer 13 formed by the pattern 11 by bending, the photo A second photoresist deposition process is performed in which a space between the SiO 2 layer 12 and the photoresist layer 13 formed by etching is deposited with a low viscosity photoresist.
따라서 본 발명은 서로 다른 점성이나 코팅 조건을 갖는 포토레지스트를 사용하여 표면을 용이하게 평탄화할 수 있다.Therefore, the present invention can easily planarize the surface by using photoresist having different viscosity or coating conditions.
Description
본 발명은 칩의 표면을 평탄하게 하기 위한 표면 평탄화 방법에 관한 것으로, 특히 다른 코팅 조건을 갖는 포토레지스트를 이용하여 용이하게 평탄화를 수행하기 위한 이중 레지스트 코팅을 이용한 평탄화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface planarization method for planarizing a surface of a chip, and more particularly, to a planarization method using a double resist coating for easily planarization using photoresists having different coating conditions.
일반적으로 칩의 표면을 평탄화하는 것은 이후의 상부층 형성을 용이하게 하기 위해서이다. 예를 들어 도선을 형성하기 위해 상부층에 도선 물질을 증착하기 위해서는 패턴화된 물질을 평탄화해야 한다.Generally, planarizing the surface of the chip is intended to facilitate subsequent top layer formation. For example, in order to deposit the lead material on the top layer to form the lead, the patterned material must be planarized.
이오 같이 표면을 평탄화 하기 위한 종래의 평탄화 방법은 도 1 에 도시한 바와 같이 SiO₂ 층 코팅 공정, 포토레지스트 코팅 공정, 및 에치백(Etch Back) 공정에 의해 수행되는데 이를 세부적으로 설명하면 다음과 같다.As described above, the conventional planarization method for planarizing the surface is performed by a SiO 2 layer coating process, a photoresist coating process, and an etch back process as illustrated in FIG. 1.
도 1a 에 도시한 바와 같이 기판(1) 상에 패턴화된 물질(2)이 형성된 상태에서 도 1b 에 도시한 바와 같이 SiO₂를 코팅하여 SiO₂층(3)을 형성하고, 도 1c 에 도시한 바와 같이 상기 SiO₂층(3) 위에 포토레지스트를 코팅하여 포토레지스트층(4)을 형성한다.In the state in which the patterned material 2 is formed on the substrate 1 as shown in FIG. 1A, as shown in FIG. 1B, SiO 2 is coated to form a SiO 2 layer 3, as shown in FIG. 1C. A photoresist layer 4 is formed by coating a photoresist on the SiO 2 layer 3 as described above.
이와 같이 패턴화된 물질(2)위에 SiO₂층(3)과 포토레지스트층(4)을 형성한후에는 도 1d 에 도시한 바와 같이 에치백 공정을 수행하여 패턴(2)에 SiO₂층(3)이 평탄화된 상태로 만든다.After the SiO 2 layer 3 and the photoresist layer 4 are formed on the patterned material 2, the SiO 2 layer 3 is formed on the pattern 2 by performing an etch back process as shown in FIG. 1D. Make it flattened.
이때, 상기 포토레지스트층(4)과 SiO₂층(3)을 식각하기 위해서는 O₂의 농도를 조절하면서 CF₄O₂ 플라즈마 RIE(Reactive Ion Etching)를 수행한다.In this case, in order to etch the photoresist layer 4 and the SiO 2 layer 3, CF₄O₂ plasma reactive ion etching (RIE) is performed while controlling the concentration of O 2.
그러나 종래의 평탄화 방법은 점성이 높은 포토레지스트를 사용하면 상부가 균일하지 않게 되어 평탄하지 않게 되고, 점성이 적은 포토레지스트를 사용하면 포토레지스트층의 증착 두께가 얇아 여러 차례의 반벅 공정이 필요하며 특히 하부 패턴의 두께가 큰 경우에는 평탄화가 거의 불가능한 문제점이 있었다.However, in the conventional planarization method, when the highly viscous photoresist is used, the upper part becomes uneven and becomes uneven. When the less viscous photoresist is used, the deposition thickness of the photoresist layer is thin, requiring several half-buckling processes. If the thickness of the lower pattern is large, there is a problem that the planarization is almost impossible.
상기 문제점을 개선하기 위해 본 발명은 서로 다른 코팅 조건을 갖는 포토레지스트를 사용하여 용이하게 표면을 평탄화하기 위한 이중 레지스트 코팅을 이용한 평탄화 방법을 제공함에 그 목적이 있다.In order to improve the above problems, an object of the present invention is to provide a planarization method using a double resist coating to easily planarize a surface by using photoresists having different coating conditions.
상기 목적을 달성하기 위해 본 발명은 패턴이 형성된 기판 상에 SiO₂ 층을 형성하는 SiO₂ 증착 공정, 상기 형성된 SiO₂층 상에 점도가 높은 포토레지스트로 포토레지스트층을 형성하는 제1 포토레지스트 증착 공정, 상기 제1 포토레지스트층 중 상기 패턴에 의해 굴곡이 형성된 부분의 포토레지스트층을 사진 식각하여 제거하는 사진 식각 공정, 상기 사진 식각에 의해 형성된 SiO₂층과 포토레지스트층 사이의 공간을 점도가 낮은 포토레지스트로 증착하는 제2 포토레지스트 증착 공정로 이루어짐을 특징으로 하는 이중 레지스트 코팅을 이용한 표면 평탄화 방법을 제공한다.In order to achieve the above object, the present invention provides a SiO ₂ deposition process for forming a SiO ₂ layer on a patterned substrate, a first photoresist deposition process for forming a photoresist layer with a high photoresist on the formed SiO ₂ layer, the A photolithography process of removing the photoresist layer of the portion of the first photoresist layer formed by the pattern by photolithography, and removing the space between the SiO 2 layer and the photoresist layer formed by the photolithography with a low viscosity photoresist. It provides a surface planarization method using a dual resist coating, characterized in that consisting of a second photoresist deposition process to deposit.
도 1 은 종래의 표면 평탄화 방법을 설명하기 위한 도면1 is a view for explaining a conventional surface planarization method
도 2 는 O2가스에 대한 포토레지스트와 SiO2의 에칭율 특성도2 is an etching rate characteristic diagram of photoresist and SiO 2 for O 2 gas;
도 3 은 본 발명에 의한 표면 평탄화 방법을 설명하기 위한 도면3 is a view for explaining a surface planarization method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1, 10 : 기판 2, 11 : 패턴1, 10: substrate 2, 11: pattern
3, 12 : SiO₂층 4, 13, 15 : 포토레지스트3, 12: SiO 2 layer 4, 13, 15: photoresist
14 : 식각 제거된 포토레지스트14 photoetched photoresist
이하 첨부한 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 의한 이중 레지스트 코팅을 이용한 표면 평탄화 방법은 도 3 에 도시한 바와 같이 패턴(11)이 형성된 기판(10) 상에 SiO₂ 층(12)을 형성하는 SiO₂ 증착 공정(도 3b), 상기 형성된 SiO₂층(12) 상에 점도가 높은 포토레지스트로 포토레지스트층(13)을 형성하는 제1 포토레지스트 증착 공정(도 3c), 상기 제1 포토레지스트층(13) 중 상기 패턴(11)에 의해 굴곡이 형성된 부분의 포토레지스트층(14)을 사진 식각하여 제거하는 사진 식각 공정(도 3d), 상기 사진 식각에 의해 형성된 SiO₂층(12)과 포토레지스트층(13) 사이의 공간을 점도가 낮은 포토레지스트로 증착하는 제2 포토레지스트 증착 공정(도 3e)로 이루어진다.In the surface planarization method using the double resist coating according to the present invention, as shown in FIG. 3, the SiO₂ deposition process of forming the SiO 2 layer 12 on the substrate 10 on which the pattern 11 is formed (FIG. 3B), the formed A first photoresist deposition process (FIG. 3C) of forming a photoresist layer 13 with a highly viscous photoresist on the SiO 2 layer 12, by the pattern 11 of the first photoresist layer 13. Photolithography process of removing the photoresist layer 14 of the bent portion by photolithography (FIG. 3D), the space between the SiO 2 layer 12 and the photoresist layer 13 formed by the photolithography has a low viscosity It consists of a 2nd photoresist deposition process (FIG. 3E) which deposits with a photoresist.
여기서, 상기 제1 포토레지스트 증착 공정은 낮은 속도의 회전 코팅에 의해 이루어지고, 상기 제2 포토레지스트 증착 공정은 높은 속도의 회전 코팅에 의해 이루어진다.Here, the first photoresist deposition process is made by a low speed rotational coating, and the second photoresist deposition process is made by a high speed rotational coating.
이와 같이 이루어지는 본 발명에 의한 표면 평탄화 방법을 세부적으로 설명한다.The surface planarization method according to the present invention thus made will be described in detail.
먼저, 도 3a 에 도시한 바와 같이 기판(10) 상에 패턴(11)을 형성하고, 도 3b 에 도시한 바와 같이 SiO₂ 증착 공정을 수행하여 패턴(11)이 형성된 기판(10) 상에 전체적으로 SiO₂를 증착하여 SiO₂ 층(12)을 형성한다.First, as shown in FIG. 3A, the pattern 11 is formed on the substrate 10, and as illustrated in FIG. 3B, the SiO 2 deposition process is performed to form SiO 2 as a whole on the substrate 10 on which the pattern 11 is formed. Is deposited to form a SiO 2 layer 12.
이와 같이 SiO₂ 증착 공정을 수행한후에는 도 3c 에 도시한 바와 같이 제1 CVD 또는 PVD를 사용하여 포토레지스트 증착 공정을 수행하여 상기 SiO₂층(12) 상에 점도가 높은 포토레지스트로 포토레지스트층(13)을 형성한다.After performing the SiO 2 deposition process as described above, as shown in FIG. 3C, the photoresist deposition process is performed by using the first CVD or PVD to form a photoresist layer 13 having a high viscosity photoresist on the SiO 2 layer 12. ).
이때, 포토레지스트층(13)을 형성하는 포토레지스트의 점도가 떨어지는 경우에는 낮은 속도로 회전 코팅하여 포토레지스트층(13)이 높게 형성되도록 한다.At this time, when the viscosity of the photoresist forming the photoresist layer 13 is low, the coating is rotated at a low speed so that the photoresist layer 13 is formed high.
이와 같이 제1 포토레지스트 증착 공정을 수행한후에는 도 3d 에 도시한 바와 같이 사진 식각 공정을 수행하여 상기 제1 포토레지스트층(13) 중 상기 패턴(11)에 의해 굴곡이 형성된 부분의 포토레지스트층(14)을 사진 식각하여 제거한다.After performing the first photoresist deposition process as shown in FIG. 3D, a photolithography process is performed to perform a photolithography process on the portion of the first photoresist layer 13 formed by the pattern 11. (14) is removed by photo etching.
즉, 포토레지스트층(13)의 평탄한 부분만을 남기고 나머지 굴곡이 있는 부분(14)을 제거한다.That is, the remaining curved portion 14 is removed while leaving only the flat portion of the photoresist layer 13.
이와 같이 사진 식각 공정을 수행하여 굴곡이 있는 부분의 포토레지스트를 제거한후에는 도 3d 에 도시한 바와 같이 제2 포토레지스트 증착 공정을 수행하여 상기 사진 식각에 의해 형성된 SiO₂층(12)과 포토레지스트층(13) 사이의 공간을 점도가 낮은 포토레지스트(15)로 증착한다.After removing the photoresist of the curved portion by performing a photolithography process as described above, as shown in FIG. 3D, a second photoresist deposition process is performed to form the SiO 2 layer 12 and the photoresist layer formed by the photolithography. The space between the (13) is deposited by the photoresist 15 having a low viscosity.
상기 포토레지스트는 점성이 낮으므로 튀어나온 포토레지스트층(13)과 SiO₂층(12)에는 증착되지 못하고 들어간 부분에만 증착되어 메워지게 된다.Since the photoresist is low in viscosity, the photoresist layer 13 and the SiO 2 layer 12 are not deposited on the protruding photoresist layer 13 and are deposited only on the portion of the photoresist.
이때 포토레지스트층(15)을 형성하는 포토레지스트의 점도가 낮지 않은 경우에는 높은 속도로 회전 코팅하여 포토레지스트(15)가 들어간 부분에만 메워지도록 한다.At this time, when the viscosity of the photoresist forming the photoresist layer 15 is not low, the coating is rotated at a high speed so as to be filled only in the portion into which the photoresist 15 has entered.
한편, 포토레지스트의 점도는 솔벤트(Solvent)로 조절 가능하므로 포토레지스트층(13)은 높은 점도를 갖도록 솔벤트의 양을 적게 하고 포토레지스트(15)는 낮은 점도를 갖도록 솔벤트의 양을 많이 한다.On the other hand, since the viscosity of the photoresist can be adjusted by the solvent (Solvent), the photoresist layer 13 reduces the amount of solvent to have a high viscosity, and the photoresist 15 increases the amount of solvent to have a low viscosity.
또한, 동일한 포토레지스트를 사용하는 경우에는 포토레지스트(13)를 증착하는 때에는 회전 속도를 낮게하고 포토레지스트(15)를 증착하는 때에는 회전 속도를 높게한다.In the case of using the same photoresist, the rotation speed is lowered when the photoresist 13 is deposited, and the rotation speed is increased when the photoresist 15 is deposited.
이상에서 설명한 바와 같이 본 발명에 의한 이중 레지스트 코팅을 이용한 표면 평탄화 방법은 서로 다른 점성이나 코팅 조건을 갖는 포토레지스트를 사용하여 표면을 용이하게 평탄화할 수 있다.As described above, the surface planarization method using the double resist coating according to the present invention can easily planarize the surface by using photoresists having different viscosity or coating conditions.
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