KR100289838B1 - Semiconductor device including electrostatic discharge circuit and manufacturing method thereof - Google Patents

Abstract

A semiconductor device comprising a static discharge circuit for protecting a semiconductor internal circuit formed on a silicon on insulator (SOI) substrate structure having a buried insulating layer and a semiconductor layer of single crystal silicon, comprising: a first device connected to a first voltage terminal; A conductive semiconductor substrate, a gate insulating film formed by patterning the buried insulating layer on the semiconductor substrate, a dummy gate formed by patterning the semiconductor layer on the gate insulating film, and connected to the first voltage terminal, and the semiconductor substrate And a source and a drain region of a second conductivity type formed on both sides of the dummy gate and connected to the first and second voltage terminals, respectively. Therefore, the internal circuit portion and the ESD circuit portion are formed on the SOI substrate structure so that the step is reduced only to the thickness of the gate of the internal circuit portion, so that the flatness of the device is increased, and the first and second gates are formed after forming the dummy gate in the ESD circuit portion. Is formed in the internal circuit portion without the step, so that the patterning is easy and the length can be accurately defined. Also, since the first and second gates are formed in the internal circuit portion, the upper semiconductor layer and the buried insulating layer are patterned after forming the first and second gates in the internal circuit portion. When the first and second gates are patterned, it is possible to prevent the polysilicon, the oxide, and the like from remaining in the ESD circuit unit.

Description

Semiconductor device including electrostatic discharge circuit and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an electrostatic discharage (hereinafter referred to as ESD) circuit which discharges an electrostatic charage applied from the outside to prevent damage to a semiconductor internal circuit. It relates to a semiconductor device comprising and a method of manufacturing the same.

In general, when a semiconductor device is momentarily applied with excessive static charge through an input pad, an output pad, or an input / output pad (I / O pad), excessive current flows in an internal circuit. This excessive current generates heat, which destroys the internal circuitry of the device and renders it unusable. Therefore, there is a need for an ESD circuit to prevent excessive current from flowing into the internal circuit and discharge it to protect the internal circuit of the device when excessive static charge is applied.

Meanwhile, the silicon on insulator (SOI) mode forms individual elements on a thin film silicon layer on an insulating substrate, thereby eliminating latch-up and reducing parasitic capacitance due to junction capacitance and the like. SOI devices with reduced parasitic capacitance have significantly increased operating speeds compared to devices having the same size on conventional bulk silicon substrates. Therefore, many techniques for forming devices on SOI substrates have been developed.

However, when the semiconductor device including the electrostatic discharge circuit for protecting the SOI circuit is formed on the SOI substrate, the device characteristics of the internal circuit drive element are improved, such as an increase in the operating speed, but the ESD circuit has a buried insulating layer under the thin film silicon layer. The thermal conductivity is so bad that the ESD characteristics are degraded.

Therefore, Mansun Chan et al., Developed a technique for preventing the degradation of ESD characteristics while increasing the operating speed of the internal circuit by forming the internal circuit on the SOI substrate and the ESD circuit on the bulk silicon substrate. ESD Protection Capability of SOI and BULK CMOS Output Buffers, '' published in IEEE 1994 / IRPS, pp. 292-298.

1 is a cross-sectional view of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to the prior art.

A semiconductor device including an ESD circuit according to the prior art includes a P-type semiconductor substrate 100 including an internal circuit portion I1 and an ESD circuit portion E1. A buried insulating layer 101 is formed on the internal circuit portion I1 of the semiconductor substrate 100, and the first and second semiconductor layers (N and P type single crystal layers) are formed on the buried insulating layer 101. 107 and 109 are formed. In the above, the internal circuit part I1 forms an SOI substrate structure including the semiconductor substrate 100, the buried insulating layer 101, and the first and second semiconductor layers 107 and 109, and the ESD circuit part E1 is formed of a semiconductor substrate ( 100) to form a bulk substrate structure consisting of only.

A first device isolation region 105 for separating devices is formed between the buried insulating layer 101 between the first and second semiconductor layers 107 and 109 of the internal circuit portion I1. First and second gates 113 and 115 are formed on the first and second semiconductor layers 107 and 109 with the gate insulating layer 111 interposed therebetween. The first source and the first drain regions 121 and 123 doped with P-type impurities at high concentration are formed on both sides of the first gate 113 in the first semiconductor layer 107, and the second semiconductor layer ( Second and second drain regions 129 and 131 doped with N-type impurities at a high concentration are formed on both sides of the second gate 115 in 109.

The first gate 113, the first source, and the first drain region 121 and 123 form a PMOS transistor 140. The first gate 113 of the first semiconductor layer 107 is formed. The lower part becomes the channel region of the PMOS transistor 140. The second gate 115, the second source, and the second drain regions 129 and 131 form an NMOS transistor 142. The second gate 115 of the second semiconductor layer 109 is formed. ) Is a channel region of the NMOS transistor 142. The PMOS transistor 140 and the NMOS transistor 142 form a C MOS transistor (CMOS), and the CMOS is formed on the SOI substrate structure.

A third gate 117 is formed on the semiconductor substrate 100 of the ESD circuit unit E1 with the gate insulating layer 111 interposed therebetween, and the N-type gates are formed on both sides of the third gate 117 in the semiconductor substrate 100. A third source and a third drain region 133 and 135 doped with a high concentration of impurities are formed. In this case, the third source and the third drain regions 133 and 135 constitute the NMOS transistor 144 together with the third gate 117. The third source and the third drain regions 133 and 135 are formed. The semiconductor substrate 100 therebetween becomes a channel region of the NMOS transistor 144. When the NMOS transistor 144 formed in the ESD circuit unit E1 is instantaneously inputted with excessive static charge through an input / output pad (I / O pad) 137 as an ESD protection circuit, excessive current is not input to the internal circuit unit I1. This prevents the elements formed in the internal circuit portion I1 from being destroyed.

In addition, a substrate contact region 125 in which the P-type impurities are heavily doped is formed in the semiconductor substrate 100, and the second device isolation region is formed between the substrate contact region 125 and the third source region 133. 106 is formed.

In the semiconductor device having the above-described structure, in the CMOS transistor formed in the internal circuit unit I1, an input terminal Vin is connected to the first and second gates 113 and 115, and the first and second drain regions 123 ( The output terminal Vout is connected to 131, and the first source 121 and the second source 129 are connected to a power supply voltage terminal Vdd and a ground terminal Vss, respectively. That is, the CMOS transistor formed in the internal circuit section I1 performs a conventional CMOS inverter structure and operation.

In addition, the ESD circuit unit E1 has the third gate 117, the third source region 133, and the substrate contact region 125 of the NMOS transistor 144 connected to the ground terminal Vss, and the third drain region 237. ) Is connected to the input / output pad 137.

In the above-described ESD circuit unit E1, when a voltage higher than that applied to the ground terminal Vss is applied to the input / output pad 137, that is, an overvoltage of a positive pulse is applied, the third drain region 135, The NPN parasitic bipolar operation of the semiconductor substrate 100 and the third source region 133 is performed. Therefore, current flows from the third drain region 135 to the third source region 133 and discharges.

However, when a voltage lower than the voltage applied to the ground terminal Vss, that is, an overvoltage of a negative pulse is applied to the input / output pad 137, the substrate contact region 125 and the third drain region 135 are formed. Acts as a forward diode so that current is discharged through the substrate contact region 125.

2 to 5 are manufacturing process diagrams of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to the prior art.

Referring to FIG. 2, an internal circuit portion I1 and an ESD circuit portion E1 are included and electrically spaced apart from the P-type upper semiconductor layer 103 by the buried insulating layer 101, that is, having a SOI structure. Type semiconductor substrate 100. The semiconductor substrate 100 is exposed by patterning the upper semiconductor layer 103 and the buried insulating layer 101 of the ESD circuit portion E1 except for the internal circuit portion I1 by photolithography. In other words, the ESD circuit portion E1 is brought to a normal bulk state.

Referring to FIG. 3, the first device isolation region 105 is formed in the upper semiconductor layer 103 of the internal circuit part I1 to be in contact with the buried insulating layer 101. At this time, the second device isolation region 106 is also formed in the semiconductor substrate 100 of the ESD circuit unit E1. The first and second device isolation regions 105 and 106 may be formed by a shallow trench isolation (STI) method or a local oxidation of silicon (LOCOS) method.

N-type impurities are ion-implanted into the upper semiconductor layer 103 to form the first semiconductor layer 107. At this time, the portion of the upper semiconductor layer 103 into which the impurities are not injected becomes the P-type second semiconductor layer 109. The first and second semiconductor layers 107 and 109 are formed in an island shape by the buried insulating layer 101 and the first device isolation region 105 to electrically insulate each other.

The gate insulating film 111 is formed on the first and second semiconductor layers 107 and 109 and the semiconductor substrate 100. Polysilicon is deposited on the first and second device isolation regions 105 and 106 and the gate insulating layer 111. Then, the polysilicon is patterned by photolithography such that the first and second semiconductor layers 107 and 109 and the semiconductor substrate 100 are exposed to form the first, second and third gates 113 and 115 ( 117).

Referring to FIG. 4, after applying the first photosensitive film 119 to the above-described structure, the first semiconductor layer 107 is patterned to be exposed. At this time, a portion where the third gate 117 of the semiconductor substrate 100 of the ESD circuit unit E1 is not formed is exposed.

P-type impurities are implanted with a high dose using the first photoresist layer 119 and the first gate 113 as a mask to form a PMOS together with the first gate 113 in the first semiconductor layer 107. One source and first drain regions 121 and 123 are formed. At this time, the exposed portion of the ESD circuit portion E1 of the semiconductor substrate 100 is ion-implanted with the dopant having high P-type impurities to form the substrate contact region 125.

Referring to FIG. 5, the first photosensitive film 119 is removed. The second photosensitive film 127 is coated on the entire surface of the above-described structure, and then patterned to expose the second semiconductor layer 109. At this time, a portion where the third gate 117 of the semiconductor substrate 100 of the ESD circuit unit E1 is formed is also exposed.

N-type impurities are implanted with a high dose using the second photosensitive film 127 and the second gate 115 as a mask to form an NMOS together with the second gate 115 in the second semiconductor layer 109. Second source and second drain regions 129 and 131 are formed. At this time, both sides of the exposed third gate 117 of the ESD circuit unit E1 of the semiconductor substrate 100 are ion-implanted with a high dose of N-type impurities to form a third source and a third drain region 133 (135). ). In this case, the third source and the third drain regions 133 and 135 together with the third gate 117 form an NMOS forming an ESD circuit.

After this, although not shown, the second photosensitive film 127 is removed.

As described above, in the semiconductor device including the electrostatic discharge circuit for protecting the SOI circuit according to the prior art, since the internal circuit portion is formed on the SOI substrate structure, device characteristics such as an increase in operating speed are improved, and the ESD circuit portion has thermal conductivity characteristics. Since the semiconductor substrate is formed on a bulk semiconductor substrate without a buried insulating layer, the ESD characteristics can be prevented from deteriorating.

However, in the semiconductor device including the electrostatic discharge circuit for protecting the SOI circuit according to the related art, the buried insulating layer is formed between the internal circuit portion formed on the SOI substrate structure and the ESD circuit portion formed on the bulk semiconductor substrate without the buried insulating layer. And since the level difference is generated by the thickness of the upper semiconductor layer there is a problem that the flatness of the device is lowered. In addition, there is a problem that it is difficult to accurately pattern the first and second gates and the third gate because there is a step difference between the SOI substrate structure and the bulk semiconductor substrate. The worse it gets, the worse it gets. In addition, when the first and second gates and the third gate are patterned, there is a problem in that residues such as polycrystalline silicon are generated at portions where a step between the internal circuit portion and the ESD circuit portion occurs.

Accordingly, an object of the present invention is to provide an electrostatic discharge circuit for protecting an SOI circuit, which can improve flatness of a device by preventing a step from occurring between an internal circuit portion and an ESD circuit portion.

Another object of the present invention is to provide a method of manufacturing an electrostatic discharge circuit for protecting an SOI circuit, which can easily pattern each gate and precisely define a length thereof in an internal circuit portion and an ESD circuit portion.

Still another object of the present invention is to provide a method of manufacturing an electrostatic discharge circuit for protecting an SOI circuit, which can prevent generation of residues such as polysilicon for forming a gate in an ESD circuit unit.

SOI circuit protection electrostatic discharge circuit according to the present invention for achieving the above object includes a static discharge circuit for protecting a semiconductor internal circuit formed on a silicon on insulator (SOI) substrate structure having a buried insulating layer and a semiconductor layer of single crystal silicon A semiconductor device comprising: a first conductive semiconductor substrate connected to a first voltage terminal, a gate insulating film formed by patterning the buried insulating layer on the semiconductor substrate, and a patterned semiconductor layer formed on the gate insulating film And a dummy gate connected to the first voltage terminal, and a source and drain region of a second conductivity type formed at both sides of the dummy gate of the semiconductor substrate and connected to the first voltage terminal and the second voltage terminal, respectively.

The SOI circuit protection electrostatic discharge circuit according to the present invention for achieving the above object is a first conductive semiconductor substrate having an internal circuit portion and the electrostatic discharge portion, a buried insulating layer formed on the internal circuit portion on the semiconductor substrate, and the buried insulation First and second semiconductor layers of a second and first conductivity type formed of single crystal silicon on the layer, first and second gates formed on the first and second semiconductor layers through a gate insulating film, and the second A first source and a first drain region of a first conductivity type formed on both sides of the first gate of the first semiconductor layer, and a second source and second of a second conductivity type formed on both sides of the second gate of the second semiconductor layer. An internal circuit including a drain region; A gate insulating layer formed of the buried insulating layer on the electrostatic discharge portion on the semiconductor substrate, a dummy gate formed of the single crystal silicon on the gate insulating layer, and a second conductive type formed on both sides of the dummy gate of the semiconductor substrate. And an electrostatic discharge circuit including a third source and a third drain region, and a substrate contact region of a first conductivity type formed in a predetermined portion of the semiconductor substrate.

According to another aspect of the present invention, there is provided a method of manufacturing an electrostatic discharge circuit for protecting an SOI circuit, the method including: protecting a semiconductor internal circuit formed on a silicon on insulator (SOI) substrate structure having a buried insulating layer and a semiconductor layer of single crystal silicon; In the method of manufacturing a semiconductor device including an electrostatic discharge circuit, the buried insulating layer and the semiconductor layer are patterned to expose the first conductive semiconductor substrate, thereby forming a gate insulating layer and a dummy gate, and simultaneously forming an isolation insulating layer and a separation space region. Forming a source and drain region by ion implanting a second conductivity type impurity into an exposed portion of the semiconductor substrate using the dummy gate as a mask; and separating the insulating insulating layer and the separation space of the semiconductor substrate. Forming a substrate contact region on one side of the region.

In accordance with another aspect of the present invention, there is provided a method of manufacturing an electrostatic discharge circuit for protecting an SOI circuit, comprising: a first conductive semiconductor substrate having an internal circuit portion and an electrostatic discharge portion; and an SOI having an upper semiconductor layer composed of a buried insulating layer and single crystal silicon. (Silicon On Insulator) preparing a substrate, and patterning the buried insulating layer and the single crystal silicon of the electrostatic discharge part to expose the semiconductor substrate to form a gate insulating film and a dummy gate on a predetermined portion of the electrostatic discharge part, and Simultaneously forming a separation space region, forming a device isolation region in contact with the buried insulating layer in the upper semiconductor layer of the internal circuit portion, and forming a second conductive type in a predetermined portion of the upper semiconductor layer of the internal circuit portion. The remaining portion is limited to the second semiconductor layer while ion implantation of impurities to form the first semiconductor layer. Forming first and second gates on the first and second semiconductor layers by interposing a gate insulating layer; and forming a first source and a first drain region of a first conductivity type in the first semiconductor layer. Forming a substrate contact region on one side of the gate insulating film and the dummy gate of the semiconductor substrate, and forming a second source and a second drain region of a second conductivity type in the second semiconductor layer; And forming a third source and a third drain region of the second conductivity type in the exposed portion of the electrostatic discharge portion.

According to another aspect of the present invention, there is provided a method of manufacturing an electrostatic discharge circuit for protecting an SOI circuit, the method including: a first conductive semiconductor substrate having an internal circuit portion and an electrostatic discharge portion; Preparing a silicon on insulator (SOI) substrate, forming a device isolation region in contact with the buried insulating layer in the upper semiconductor layer of the internal circuit part, and forming a second conductive layer in a predetermined portion of the upper semiconductor layer of the internal circuit part Defining a remaining portion of the upper semiconductor layer of the internal circuit portion as the second semiconductor layer while forming a first semiconductor layer by ion implantation of impurities of a type; and interposing a gate insulating film on the first and second semiconductor layers. Forming first and second gates, and depositing the buried insulating layer and the single crystal silicon of the electrostatic discharge unit. Forming a gate insulating layer and a dummy gate at a predetermined portion of the electrostatic discharge unit simultaneously to form a separation insulating layer and a separation space region, and forming a first source and a first source of a first conductivity type in the first semiconductor layer. Forming a substrate contact region on one side of the gate insulating film and the dummy gate of the semiconductor substrate while forming a drain region, and forming a second source and second drain region of a second conductivity type in the second semiconductor layer; And forming a third source and a third drain region of a second conductivity type in the exposed portion of the electrostatic discharge portion of the electrostatic discharge circuit.

1 is a cross-sectional view of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to the prior art.

2 to 5 are manufacturing process diagrams of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to the prior art.

6 is a cross-sectional view of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to the present invention.

7 to 10 are manufacturing process diagrams of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to an embodiment of the present invention.

11 to 12 are manufacturing process diagrams of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to another embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

6 is a cross-sectional view of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to the present invention.

In a semiconductor device including an ESD circuit according to the present invention, an SOI substrate having a buried insulating layer 201 and a single crystal silicon layer formed on a P-type semiconductor substrate 200 including an internal circuit portion I2 and an ESD circuit portion E2. It is formed on the structure. The single crystal silicon layer may include the N and P type first and second semiconductor layers 211 and 213 of the internal circuit portion I2, the dummy gate 205 and the isolation space region 207 of the ESD circuit portion E2. ).

In the internal circuit unit I2, the first and second semiconductor layers 211 and 213 are electrically separated from the semiconductor substrate 200 by the buried insulating layer 201, and an isolation region for separating elements therebetween. 209 is formed. The device isolation region 209 is formed to be in contact with the buried insulating layer 201 by the STI method or the LOCOS method so that the first and second semiconductor layers 211 and 213 are electrically separated from each other in the horizontal direction. Therefore, each of the first and second semiconductor layers 211 and 213 are electrically separated completely.

First and second gates 217 and 219 are formed on the first and second semiconductor layers 211 and 213 with the gate insulating layer 215 interposed therebetween. The first source and the first drain regions 223 and 225 doped with P-type impurities at high concentration are formed on both sides of the first gate 215 of the first semiconductor layer 211, and the second semiconductor layer ( Second and second drain regions 231 and 233 doped with N-type impurities at a high concentration are formed on both sides of the second gate 219 of 213.

The first gate 217, the first source, and the first drain regions 223 and 225 form a PMOS transistor 240, and a lower portion of the first gate 217 of the first semiconductor layer 211 is a PMOS. It becomes a channel region of the transistor 240. The second gate 219, the second source, and the second drain regions 231 and 233 form an NMOS transistor 242. The lower portion of the second gate 219 of the second semiconductor layer 213 is NMOS. It becomes a channel region of the transistor 242. In the above, the PMOS transistor 240 and the NMOS transistor 242 form a CMOS to configure an internal circuit.

In the ESD circuit unit E2, the dummy gate 205 and the isolation space region 207 are formed by interposing a buried insulating layer 201 in a predetermined portion on the semiconductor substrate 200. In the above, the buried insulating layer 201 is used as the gate insulating layer formed under the dummy gate 205, and the buried insulating layer 201 is used as the insulating insulating layer under the separation space region 207.

Using the dummy gate 205 and the separation space region 207 as a mask on the semiconductor substrate 200, the third source and third drain regions 235 and 237 and the P-type doped with N-type impurities are highly doped. The substrate contact region 227 is heavily doped with impurities. In this case, the third source and the third drain regions 235 and 237 constitute the NMOS transistor 244 together with the dummy gate 205, and between the third source and the third drain regions 235 and 237. The semiconductor substrate 200 is a channel region of the NMOS transistor 244.

In the semiconductor device having the above-described structure, in the CMOS transistor formed in the internal circuit unit I2, an input terminal Vin is connected to the first and second gates 217 and 219, and the first and second drain regions 225 ( The output terminal Vout is connected to 233, and the first source 223 and the second source 231 are connected to the power supply voltage terminal Vdd and the ground terminal Vss, respectively.

In the ESD circuit unit E2, the dummy gate 205, the third source region 235, and the substrate contact region 227 of the NMOS transistor 244 are connected to the ground terminal Vss, and the third drain region 237. Is connected to the input / output pad 239.

In the semiconductor device described above, the CMOS transistor of the internal circuit part I2 has a conventional CMOS inverter structure and operates normally when a normal voltage is applied. The parasitic capacitance is reduced by the buried insulating layer 201, thereby improving the operation speed of the device. do.

However, when an overvoltage is applied to the semiconductor device through the input / output pad 239, the ESD circuit unit E2 performs the NPN parasitic bipolar operation including the third drain region 237, the semiconductor substrate 200, and the third source region 235. Alternatively, the substrate contact region 227 and the third drain region 237 act as forward diodes to discharge current to block the flow to the internal circuit unit C2. That is, when a voltage higher than that applied to the ground terminal Vss, that is, an overvoltage of a positive pulse is applied to the input / output pad 239, the third drain region 237, the semiconductor substrate 200, and the like. An NPN parasitic bipolar consisting of the third source region 235 is generated to discharge current through the third source region 235.

In addition, when a voltage lower than that applied to the ground terminal Vss, that is, an overvoltage of a positive pulse is applied to the input / output pad 239, the substrate contact region 227 and the third drain region 237. Acts as a forward diode so that current is discharged through the substrate contact region 125.

Therefore, when the ESD circuit unit E2 instantaneously receives excessive static charge through the input / output pad 239, the ESD circuit unit E2 discharges excessive current so that the elements formed in the internal circuit unit I2 are destroyed. prevent. At this time, since the ESD circuit unit E2 is formed on the semiconductor substrate 200 in the bulk state, the thermal conductivity is improved to improve the ESD characteristic.

In addition, in the semiconductor device including the electrostatic discharge circuit for protecting the SOI circuit according to the present invention, the internal circuit portion I2 and the ESD circuit portion E2 are formed on the SOI substrate structure so that only the first and second gates 217 ( The flatness of the device is increased because it is reduced to the thickness of 219.

7 to 10 are manufacturing process diagrams of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to an embodiment of the present invention.

Referring to FIG. 7, there is an SOI substrate structure in which a buried insulating layer 201 and a P-type single crystal silicon layer are formed on a P-type semiconductor substrate 200 including an internal circuit portion I2 and an ESD circuit portion E2. . The semiconductor substrate 200 is exposed by patterning the single crystal silicon layer and the buried insulating layer 201 of the predetermined portion of the ESD circuit unit E2 by a photolithography method.

The portion remaining in the internal circuit portion I2 of the P-type single crystal silicon layer is the upper semiconductor layer 203, and the portion remaining in the ESD circuit portion E2 is the dummy gate 205 and the isolation space region 207. Becomes The buried insulating layer 201 is a gate insulating layer remaining under the dummy gate 205 and a remaining insulating layer under the separation space region 207.

Referring to FIG. 8, the device isolation region 209 is formed in the upper semiconductor layer 203 of the internal circuit part I2 to be in contact with the buried insulating layer 201. The device isolation region 209 is formed by the STI method or the LOCOS method.

The first semiconductor layer 211 is formed by ion implanting N-type impurities into a predetermined portion of the upper semiconductor layer 203. At this time, the portion of the upper semiconductor layer 203 where the impurities are not injected is the second semiconductor layer 213. In the above description, the first and second semiconductor layers 211 and 213 are formed in an island shape by the buried insulating layer 201 and the device isolation region 209 to be electrically insulated.

A gate insulating film 215 is formed on the first and second semiconductor layers 211 and 213, and polysilicon is deposited on the device isolation region 209 and the gate insulating film 215. Then, the polysilicon and the gate insulating layer 215 are patterned by photolithography so as to expose the first and second semiconductor layers 211 and 213 to form the first and second gates 217 and 219. At this time, since there is no step between the first and second semiconductor layers 211 and 213, not only the patterning of the first and second gates 217 and 219 can be easily defined, but also the length can be precisely defined.

Referring to FIG. 9, after applying the first photosensitive film 221 to the above-described structure, the first semiconductor layer 211 is patterned to be exposed. In this case, an exposed portion of the ESD circuit portion E2 of the semiconductor substrate 200, that is, a portion of one side of the separation space region 207 is also exposed.

P-type impurities are implanted with a high dose using the first photoresist layer 221 and the first gate 217 as a mask to form a PMOS together with the first gate 217 in the first semiconductor layer 211. One source and first drain regions 223 and 225 are formed. At this time, the exposed portion of the ESD circuit portion E2 of the semiconductor substrate 200 is ion-implanted with the dopant having high P-type impurities to form the substrate contact region 227.

Referring to FIG. 10, the first photosensitive film 221 is removed. The second photosensitive film 229 is coated on the entire surface of the above-described structure, and then patterned to expose the second semiconductor layer 213. At this time, a portion where the dummy gate 205 of the semiconductor substrate 200 of the ESD circuit unit E2 is formed is also exposed.

N-type impurities are implanted with a high dose using the second photoresist film 229 and the second gate 219 as a mask to form an NMOS together with the second gate 219 in the second semiconductor layer 213. Second source and second drain regions 231 and 233 are formed. At this time, both sides of the exposed dummy gate 205 of the ESD circuit unit E2 of the semiconductor substrate 200 are ion-implanted with a doped N-type impurity to form a third source and a third drain region 235 and 237. To form. The third source and the third drain regions 235 and 237 together with the dummy gate 205 form an NMOS forming an ESD circuit.

After this, although not shown, the second photosensitive film 229 is removed.

11 to 13 are manufacturing process diagrams of a semiconductor device including an electrostatic discharge circuit for protecting an SOI circuit according to another exemplary embodiment of the present invention.

Referring to FIG. 11, an SOI substrate having a buried insulating layer 201 and a P-type upper semiconductor layer 203 formed on a P-type semiconductor substrate 200 including an internal circuit portion I2 and an ESD circuit portion E2. There is a structure.

The device isolation region 209 is formed in contact with the buried insulating layer 201 in a predetermined portion of the internal circuit portion I2 of the upper semiconductor layer 203. The device isolation region 209 is formed by the STI method or the LOCOS method.

Referring to FIG. 12, a first semiconductor layer 211 is formed by ion implanting N-type impurities into a predetermined portion of the internal circuit portion I2 of the upper semiconductor layer 203. At this time, the portion of the upper semiconductor layer 203 where the impurities of the internal circuit portion I2 is not injected is the second semiconductor layer 213. In the above description, the first and second semiconductor layers 211 and 213 are formed in an island shape by the buried insulating layer 201 and the device isolation region 209 to be electrically insulated.

A gate insulating film 215 is formed on the first and second semiconductor layers 211 and 213, and polysilicon is deposited on the device isolation region 209 and the gate insulating film 215. The polysilicon and gate insulating film 215 is photolithographic so as to expose the first and second semiconductor layers 211 and 213 of the internal circuit portion I2 and the upper semiconductor layer 203 of the ESD circuit portion E2. Patterning to form the first and second gates 217 and 219. In this case, since there is no step between the internal circuit portion I2 and the ESD circuit portion E2, the patterning of the first and second gates 217 and 219 may be easy, and the length may be accurately defined.

Referring to FIG. 13, the upper semiconductor layer 203 and the buried insulating layer 201 of a predetermined portion of the ESD circuit unit E2 are patterned by photolithography to expose the semiconductor substrate 200.

The portion remaining in the ESD circuit portion E2 of the upper semiconductor layer 203 becomes the dummy gate 205 and the isolation space region 207. The buried insulating layer 201 is a gate insulating layer remaining under the dummy gate 205 and a remaining insulating layer under the separation space region 207.

In the above, the first and second gates 217 and 219 are formed on the first and second semiconductor layers 211 and 213 of the internal circuit part I2 through the gate insulating film 215, and then the ESD circuit part ( The upper semiconductor layer 203 and the buried insulating layer 201 of E2 are patterned to expose the semiconductor substrate 200, thereby forming the dummy gate 205 and the isolation space region 207, thereby forming an ESD circuit portion of the semiconductor substrate 200. It is possible to prevent the remaining of polycrystalline silicon and oxide in the exposed portion of (E2).

Accordingly, the present invention has the advantage that the flatness of the device is increased because the internal circuit portion and the ESD circuit portion are formed on the SOI substrate structure so that the step is reduced only to the thickness of the gate of the internal circuit portion. In addition, since the dummy gate is formed in the ESD circuit part, the first and second gates are formed in the internal circuit part having no step, so that the patterning is easy and the length can be accurately defined. After the first and second gates are formed in the internal circuit part, the upper semiconductor layer and the buried insulating layer are patterned in the ESD circuit part, so that polycrystalline silicon, oxide, etc. remain in the ESD circuit part when the first and second gates are patterned. There is an advantage to avoid.

Claims (7)

A semiconductor device comprising an electrostatic discharge circuit for protecting a semiconductor internal circuit formed on a silicon on insulator (SOI) substrate structure having a buried insulating layer and a semiconductor layer of single crystal silicon. A first conductive semiconductor substrate connected to the first voltage terminal; A gate insulating film formed by patterning the buried insulating layer on the semiconductor substrate; A dummy gate formed by patterning the semiconductor layer on the gate insulating layer and connected to the first voltage terminal; And a static discharge circuit formed on both sides of the dummy gate of the semiconductor substrate, the electrostatic discharge circuit including a source and a drain region of a second conductivity type connected to the first voltage terminal and the second voltage terminal, respectively. The semiconductor device of claim 1, further comprising an electrostatic discharge circuit formed on the semiconductor substrate by being heavily doped with impurities of a first conductivity type and further comprising a substrate contact region connected to the first voltage terminal. 3. The semiconductor device according to claim 2, wherein the first voltage terminal is a ground terminal and the second voltage terminal is an electrostatic discharge circuit. A first conductive semiconductor substrate having an internal circuit portion and an electrostatic discharge portion, A buried insulating layer formed on the internal circuit portion on the semiconductor substrate; First and second semiconductor layers of second and first conductivity types formed of single crystal silicon on the buried insulating layer; First and second gates formed on the first and second semiconductor layers via gate insulating films; A first source and a first drain region of a first conductivity type formed on both sides of the first gate of the first semiconductor layer; An internal circuit including a second source and a second drain region of a second conductivity type formed on both sides of the second gate of the second semiconductor layer; A gate insulating layer formed of the buried insulating layer on the electrostatic discharge portion on the semiconductor substrate; A dummy gate formed of the single crystal silicon on the gate insulating layer; A third source and a third drain region of a second conductivity type formed on both sides of the dummy gate of the semiconductor substrate; An electrostatic discharge circuit including a first contact type substrate contact region formed in a predetermined portion of the semiconductor substrate; A semiconductor device comprising an electrostatic discharge circuit. A method for manufacturing a semiconductor device comprising an electrostatic discharge circuit for protecting a semiconductor internal circuit formed on a silicon on insulator (SOI) substrate structure having a buried insulating layer and a semiconductor layer of single crystal silicon, Patterning the buried insulating layer and the semiconductor layer to expose a first conductive semiconductor substrate to form a gate insulating layer and a dummy gate while simultaneously forming an isolation insulating layer and a separation space region; Forming source and drain regions by ion implanting impurities of a second conductivity type into the exposed portions of the semiconductor substrate using the dummy gate as a mask; And forming a substrate contact region on one side of the isolation insulating layer and the separation space region of the semiconductor substrate. Preparing a silicon on insulator (SOI) substrate having a first conductive semiconductor substrate having an internal circuit portion and an electrostatic discharge portion and an upper semiconductor layer made of a buried insulating layer and single crystal silicon; Patterning the buried insulating layer and the single crystal silicon of the electrostatic discharge part so as to expose the semiconductor substrate to simultaneously form the insulating insulating layer and the separation space region while forming a gate insulating film and a dummy gate in a predetermined portion of the electrostatic discharge part; Forming a device isolation region in contact with the buried insulating layer in the upper semiconductor layer of the internal circuit part; Defining a remaining portion as a second semiconductor layer while forming a first semiconductor layer by implanting a second conductivity type impurity into a predetermined portion of the upper semiconductor layer of the internal circuit portion; Forming first and second gates on the first and second semiconductor layers by interposing a gate insulating film; Forming a substrate contact region on one side of the gate insulating film and the dummy gate of the semiconductor substrate while forming a first source and a first drain region of a first conductivity type in the first semiconductor layer; A second conductive third source and a third drain region are formed on the exposed portion of the electrostatic discharge portion of the semiconductor substrate while the second source and second drain regions of the second conductive type are formed in the second semiconductor layer. A manufacturing method of a semiconductor device comprising an electrostatic discharge circuit having the step of. Preparing a silicon on insulator (SOI) substrate having a first conductive semiconductor substrate having an internal circuit portion and an electrostatic discharge portion and an upper semiconductor layer made of a buried insulating layer and single crystal silicon; Forming a device isolation region in contact with the buried insulating layer in the upper semiconductor layer of the internal circuit part; Defining a remaining portion of the upper semiconductor layer of the inner circuit portion as a second semiconductor layer while forming a first semiconductor layer by ion implanting a second conductivity type impurity into a predetermined portion of the upper semiconductor layer of the inner circuit portion; Forming first and second gates on the first and second semiconductor layers by interposing a gate insulating film; Patterning the buried insulating layer and the single crystal silicon of the electrostatic discharge part to expose the semiconductor substrate to simultaneously form a isolation insulating layer and a separation space region while forming a gate insulating film and a dummy gate in a predetermined portion of the electrostatic discharge part; , Forming a substrate contact region on one side of the gate insulating film and the dummy gate of the semiconductor substrate while forming a first source and a first drain region of a first conductivity type in the first semiconductor layer; A second conductive third source and a third drain region are formed on the exposed portion of the electrostatic discharge portion of the semiconductor substrate while the second source and second drain regions of the second conductive type are formed in the second semiconductor layer. A manufacturing method of a semiconductor device comprising an electrostatic discharge circuit further comprising the step of: