KR100285967B1 - Data storage device and method using flash memory - Google Patents

Abstract

The present invention simultaneously controls the flash memory unit separated for each input channel, by using a plurality of flash memory elements constituting each flash memory unit as a single device, a flash that can process a large amount of data, such as a video signal faster It is an object of the present invention to provide a data storage device and method using the memory.

According to the present invention, a data storage device which receives an access command and a write command of a central processing unit applied to each flash memory device, and stores data signals input through a plurality of channels in a flash memory unit allocated to each channel. A buffer memory unit allocated for each channel for converting the data signal input from any one channel into a bus size of a system bus; A data path selection circuit unit for transmitting the size-converted data signal output from the buffer memory unit to a flash memory unit allocated to each channel and simultaneously transmitting an access command and a write command of the central processing unit to each of the flash memory units; The flash memory unit allocated to each channel for storing the size-converted data signal inputted through the data path selection circuit unit; And a buffer memory unit allocated to each channel, a data path selection circuit unit, and a controller for applying a control signal to each channel.

Description

Data storage device and method using flash memory

The present invention relates to a data storage device, and more particularly, to a data storage device and a data storage method using a flash memory.

Flash memory is an advanced semiconductor in which stored data is preserved even when the power is turned off, unlike ordinary RAM, which stores stored data when the power is turned off. Due to the characteristics of the flash memory, the flash memory has been widely used in data storage devices such as electronic notebooks in which data should be stably stored even when the battery is exhausted.

In general, a flash memory is composed of a plurality of pages, each page is composed of a plurality of columns, and each column stores one byte or two bytes of data. Therefore, in order to store data in the flash memory, address information for storing data is provided together with data information to be stored, and such address information includes a column address and a page address.

Such a conventional data storage device using a flash memory is described in detail in Korean Patent Publication No. 96-86675, "Real Time Processing Method and Apparatus Using a Flash Memory," as shown in FIG.

That is, it uses a time division technique, and includes a first register unit 10, a multi-stage register unit 20, a multi-stage first-in first-out memory unit 30, a multi-stage flash memory unit 40, and a clock divider unit 50. It is composed of

The first register unit 10 receives the continuously input video signal and the data clock and synchronizes the video signal with the data clock. The data clock has a frequency suitable for time division processing of the video signal. The multi-stage register unit 20 is composed of a plurality of registers connected in parallel, the plurality of registers are sequentially operated by the divided data clock output from the clock divider 50. While a plurality of registers constituting the multi-stage register unit 20 are sequentially operated, the moving picture signal synchronized with the data clock is sequentially stored in the multi-stage first-in-first-out memory unit 30.

The reason why the video signal is divided and stored in the first-in first-out memory unit is that the flash memory cannot process the high-speed video signal in real time. Therefore, the multi-stage register unit 20 divides the video signal, and stores the divided video signal in the multi-stage flash memory unit 40 through the multi-stage first-in first-out memory unit 30.

The multi-stage first-in first-out memory unit 30 is configured by first-in-first-out (FIFO) memories corresponding to each register of the multi-stage register unit 20 connected in series. A divided video signal input through each register of the multi-stage register unit 20 is received and temporarily stored in each first-in first-out memory.

The multi-stage flash memory unit 40 is composed of flash memories corresponding to respective first-in first-out memory of the multi-stage first-in first-out memory unit 30, and is output from each first-in first-out memory of the multi-stage first-in first-out memory unit 30. The divided video signals are sequentially received in each flash memory.

At this time, each flash memory constituting the multi-stage flash memory unit 40 is driven under the control of a central processing unit (not shown). That is, when an access command is applied from the CPU to the flash memory, the flash memory writes one page of the divided video signal temporarily stored in the first-in first-out memory into the internal page buffer. Then, when a write command is applied from the central processing unit, the flash memory moves and records the moving picture signal stored in the internal page buffer to the memory cell of the flash memory. The clock divider 50 provides a data clock to the first register 10 and sequentially outputs the divided data clock to each register of the multi-stage register unit 20.

The conventional data storage device divides an input video signal using a time division technique and temporarily stores the first moving image signal in the multi-first-in first-out memory unit 30. Then, in order to store the moving picture signal temporarily stored in the multi-first-in first-out memory unit 30 in the multi-stage flash memory unit, first, one page worth of video signal is stored in the internal page buffer of the flash memory, and then the internal page buffer. Wait until the moving picture signal stored in the memory cell moves into the flash memory.

At this time, the time when the moving picture signal is written from the first-in first-out memory into the internal page buffer of the flash memory is called the access time, and the time recorded by moving from the internal page buffer of the flash memory to the memory cell is recorded. Due to the nature of the flash memory, the write time is very long compared to the access time, and the central processing unit waits without performing other control during the write time.

Therefore, in the above-described conventional technique, even if a high speed video signal continuously inputted is divided by a time division technique and subsequently input to the first-in, first-out memory, the internal page buffer of the flash memory is to be written to the memory cells of the flash memory. It must wait until it is recorded in the memory cell before moving to the memory cell. As a result, a conventional data storage device using a flash memory has a problem in that it cannot process a video signal having a large capacity over a specific input speed.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, by simultaneously controlling the flash memory unit separated for each input channel, by using a plurality of flash memory constituting each flash memory unit as one element, It is an object of the present invention to provide a data storage device and method using a flash memory that can process and store a large data signal such as a video signal continuously input.

1 is a block diagram of a data storage device using a flash memory according to the prior art;

2 is a block diagram of a data storage device using a flash memory according to an embodiment of the present invention;

3 is a detailed block diagram of a buffer memory unit shown in FIG. 2;

4 is a detailed block diagram of the data path selection circuit shown in FIG. 2;

FIG. 5 is a detailed configuration diagram of the virtual flash memory shown in FIG. 4.

* Explanation of symbols for the main parts of the drawings *

100: buffer memory section 110: extended buffer memory section

130: bus expansion clock generator 200: data path selection circuit unit

230: common bus 300: flash memory unit

400: control unit 500: central processing unit

600: control clock generator

A data storage device using a flash memory according to the present invention for achieving the above object, by receiving an access command and a write command of the central processing unit applied to each flash memory device, and receives a data signal input through a plurality of channels A data storage device for storing a flash memory unit allocated to each channel, comprising: a buffer memory unit allocated to each channel for converting the data signal input from any one channel into a bus size of a system bus; A data path selection circuit unit for transmitting the size-converted data signal output from the buffer memory unit to a flash memory unit allocated to each channel and simultaneously transmitting an access command and a write command of the central processing unit to each of the flash memory units; The flash memory unit allocated to each channel to sequentially record the size-converted data signal input through the data path selection circuit unit in a plurality of flash memory devices allocated to the channel, and then move and store the same in a memory cell; And a control unit connected to a buffer memory unit allocated to each channel, a data path selection circuit unit, and a flash memory unit allocated to each channel through a common bus to apply a control signal.

In addition, the data storage method using a flash memory according to the present invention, in the data storage method for storing a data signal input through a plurality of channels in the flash memory unit allocated to each channel, the data input from any one channel Converting a signal into a bus size of a system bus; A second step of writing the size-converted data signal into an internal page buffer of an arbitrary flash memory device connected to the channel, and then applying a write command to move the data written in the page buffer to a memory cell for storage; While the data is moved to the memory cell of the arbitrary flash memory device in the second step, after writing data to the internal page buffer of another flash memory device, data is written to the page buffer by applying a write command to the memory cell. Moving to and storing in the third step; A fourth step of repeatedly performing the second to third steps to continuously store data signals input from the channels in the plurality of flash memory devices; And a fifth step of simultaneously performing the first to fourth steps with respect to each channel to simultaneously store data input through all channels.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, a data storage device using a flash memory according to an embodiment of the present invention may include a buffer memory unit 100 allocated to each channel, a data path selection circuit unit 200, and a channel allocated to each channel. Flash memory unit 300, and the control unit 400. In an embodiment of the present invention, it is assumed that data signals input through n channels are stored in a flash memory unit allocated to each channel.

The buffer memory unit 100 allocated to each channel receives a data signal and a clock for each channel, and an output terminal thereof is connected to an input terminal of the data path selection circuit unit 200. An output terminal of the data path selection circuit unit 200 is connected to an input terminal of the flash memory unit 300. The control unit 400 is connected to the buffer memory unit 100, the data path selection circuit unit 200, and the flash memory unit 300 allocated to each channel through the common bus 230, respectively. The control signal is output so that the data signal input through the channel is simultaneously recorded in the flash memory unit 300 allocated to each channel. However, when reading the data stored in the flash memory unit 300, the control signal is output so that the data stored in each flash memory unit is separately output.

As shown in FIG. 3, the buffer memory unit 100 includes an expansion buffer memory unit 110 and a bus expansion clock generator 130. In the embodiment of the present invention, it is assumed that the size of the data signal input from each channel is 8 bits, and the bus size of the system bus is 16 bits. At this time, the extended buffer memory unit 110 is composed of an upper 8-bit buffer and a lower 8-bit buffer allocated for each channel. The data signal input for each channel is sequentially stored in the upper 8-bit buffer and the lower 8-bit buffer. The 16-bit data is output to the data path selection circuit unit 200.

As illustrated in FIG. 4, the data path selection circuit unit 200 includes a bus driver 210 and a bus transceiver 220. The bus driver 210 is composed of n bus drivers formed in a parallel structure, the input terminal of which is connected to the output terminal of the buffer memory unit 100, and the output terminal of the bus driver unit 210 is connected to the input terminal of the flash memory unit 300. Connected.

The bus transceiver unit 220 is composed of n bus transceivers (Bus Transceivers) formed in a parallel structure, which is connected to the common bus 230 between the flash memory unit 300 and the central processing unit 500. The flash memory unit 300 is composed of k virtual flash memories allocated for each channel. Each virtual flash memory is composed of m flash memory devices as shown in FIG. 5, where m flash memory devices operate as one device. In order to operate one virtual flash memory as one device, the CPU 500 outputs address information including m device addresses together with column and page addresses to each virtual flash memory.

The operation of a data storage device using a flash memory having such a configuration will be described below.

The present invention has two features. First, since data signals input through n channels are simultaneously controlled and stored in the flash memory unit 300 allocated to each channel, the data throughput that can be controlled by one central processing unit 500 is increased by n times. do. Second, k virtual flash memories are allocated to each channel, and each virtual flash memory is composed of m flash memory devices but operates like a single device.

First, a process of simultaneously controlling data signals respectively input through n channels will be described.

When an 8-bit data signal is input to the expansion buffer memory unit 110 through any one channel (for example, the first channel), the expansion buffer memory unit 110 scales the data signal into a 16-bit data signal. Convert and output That is, when the bus extension clock generator 130 sequentially outputs a write clock to the upper 8-bit buffer and the lower 8-bit buffer allocated to channel 1 according to the data clock, the 8-bit buffer into which the write clock is input. The two 8-bit data signals input through channel 1 are sequentially written to the upper 8-bit buffer and the lower 8-bit buffer. After that, when the control unit 500 outputs a read clock to the expansion buffer memory unit 110, data signals respectively stored in the upper 8-bit buffer and the lower 8-bit buffer are simultaneously output, and the data signal is converted into 16 bits. Is input to the data path selection circuitry 200.

As such, while the data signal input through the channel 1 is size-converted and input to the data path selection circuit unit 200, the data signals input through the channel 2 through the channel n are respectively the upper 8-bit buffers allocated to the respective channels. The size is converted into 16 bits by the lower 8-bit buffer and input to the data path selection circuit unit 200.

That is, the 8-bit data signal input for each channel is combined with two 8-bit signals by two 8-bit buffers, and is converted into 16 bits, which is the size of the system bus, and is input to the bus driver 210 of the data path selection circuit unit 200. In this case, if the size of the system bus is 32 bits, the expansion buffer memory unit 110 should be configured to allocate four 8-bit buffers for each channel.

The data signal size-converted into 16 bits as described above is applied to each bus driver 210 corresponding to n channels. The bus driver 210 is turned on or off so as not to transmit or transmit the data signal to the flash memory unit 300, and is switched on by receiving an enable signal output from the control clock generator 600. .

Meanwhile, the central processing unit 500 controls an access command and a write command through the common bus 230 to collectively control each flash memory unit 300 allocated to each channel. The command signal is output to the bus transceiver 220, and the command signal is simultaneously input to each flash memory unit corresponding to each channel through the bus transceiver 220. FIG. That is, the central processing unit 500 may simultaneously control the data signals inputted for each channel at the same time, and write them to the flash memory unit 300 allocated for each channel.

As such, while the command signal is transmitted from the central processing unit 500 to the flash memory unit 300, the bus transceiver 220 operates in an 'on' state so that the command signal is transmitted to the flash memory unit 300. Meanwhile, while the data signal converted in size from the buffer memory unit 100 is transmitted to the flash memory unit 300 through the bus driver 210, the bus transceiver 220 operates in an 'off' state to operate the flash memory unit ( The data signal to be transmitted to the 300 is prevented from flowing toward the common bus 230.

The control clock generator 600 outputs the read control clock to the buffer memory unit 100 and outputs the write control clock to the flash memory unit 300. At the same time, the control clock generator 600 applies an enable signal for an on / off operation to the bus driver 210 and an enable signal for a switching operation to the bus transceiver 220, respectively. The data signal to be stored in the flash memory unit 300 directly accesses each flash memory of the flash memory unit 300 without passing through the central processing unit 500 through the buffer memory unit 100 corresponding to each channel. It is directly transmitted and stored by (Direct Memory Access) method.

By such an operation, data signals input for each channel are simultaneously controlled and simultaneously recorded in the flash memory unit 300 allocated to each channel.

Next, the CPU 500 controls the k virtual flash memories allocated to each channel to record and store data signals.

First, when a data signal is input from any one channel, the buffer memory unit 100 converts the data signal into the bus size of the system bus. In this embodiment, it is assumed that an 8-bit data signal is input from one channel and converted into a 16-bit data signal in the buffer memory unit 100.

The central processing unit 500 controls the virtual flash memory composed of m flash memory devices as one device. In detail, the CPU 500 applies an access command to the first flash memory device of the virtual flash memory and applies address information including the device address to convert the 16-bit data signal into the first flash memory. Write to the device's page buffer. When the page buffer of the first flash memory device is full, the CPU 500 applies a write command to the first flash memory device so that the data written to the page buffer is moved to the first memory cell of the first flash memory device. To be stored.

After that, to write new data to the page buffer of the first flash memory device, it is necessary to wait until the data written to the page buffer moves to the first memory cell. However, the central processing unit 500 of the present invention applies an access command to the second flash memory device without waiting time and provides address information so that the next data signal is written to the page buffer of the second flash memory device. When the page buffer of the second flash memory device is full, the CPU 500 applies a write command to the second flash memory device so that the data written in the page buffer is moved to and stored in the first memory cell.

Next, the CPU 500 repeats the above operation to the m flash memory devices constituting the virtual flash memory. After performing the above operation on the m th flash memory device, the first flash memory device is performed. Rewrite one page's worth of data into the internal page buffer. At this time, since all data previously written to the page buffer of the first flash memory device is moved to the memory cell, the CPU applies the access command to the page buffer of the first flash memory device without waiting for the page buffer. The data signal can be recorded in the.

In this way, the CPU can continuously record data without waiting time by using a plurality of flash memory elements constituting the virtual flash memory. That is, after writing data to an internal page buffer of one flash memory device, a write command is applied, and new data is continuously written to the internal page buffer of another flash memory device while data written to the page buffer is transferred to the memory cell. Record it.

As such, the address information of the flash memory provided to record a data signal in the virtual flash memory includes a column address, m flash memory device addresses, and a page address, and includes one virtual flash memory allocated to each channel. Can be used like a flash memory device.

The data storage device using the flash memory of the present invention described above has the effect of processing a large data signal faster because the buffer memory unit and the flash memory unit allocated to each input channel are simultaneously controlled for all channels.

In addition, since a plurality of flash memory devices allocated to each channel are used as one device, a large data signal such as a video signal continuously input can be easily and quickly stored.

Claims (7)

A data storage device which receives an access command and a write command of a central processing unit applied to each flash memory device, and stores data signals input through a plurality of channels in a flash memory unit allocated to each channel. A buffer memory unit allocated to each channel for converting the data signal inputted from any one channel into a bus size of a system bus; A data path selection circuit unit for transmitting the size-converted data signal output from the buffer memory unit to a flash memory unit allocated to each channel and simultaneously transmitting an access command and a write command of the central processing unit to each of the flash memory units; The flash memory unit allocated to each channel to sequentially record the size-converted data signal input through the data path selection circuit unit in a plurality of flash memory devices allocated to the channel, and then move and store the same in a memory cell; And And a control unit connected to a buffer memory unit allocated to each channel, a data path selection circuit unit, and a flash memory unit allocated to each channel through a common bus to apply a control signal. The method of claim 1, wherein the buffer memory unit allocated to each channel, An extended buffer memory unit including a plurality of buffers for temporarily storing data signals inputted from any one channel sequentially and simultaneously outputting data signals having a size corresponding to the bus size of the system bus; And a bus expansion clock generator for sequentially applying a write clock to each buffer constituting the expansion buffer memory unit according to the data clock of the data signal. The method of claim 1, wherein the data path selection circuit unit, A bus driver allocated to each channel for turning on / off according to a control signal output from the controller to output a size-converted data signal output from a buffer memory unit to the flash memory unit; It is connected between the flash memory unit and the central processing unit through a common bus, and is 'off' during transmission of the size-converted data signal from the bus driver to the flash memory unit, and access command from the central processing unit to the flash memory unit is performed. A data storage device using a flash memory, characterized in that it comprises a bus transceiver allocated to each channel operating 'on' while a write command is transmitted. The data storage device of claim 1, wherein a read control clock is output to the buffer memory unit and a write control clock is output to the flash memory unit so that the size-converted data signal output from the buffer memory unit is directly accessed. And a control clock generator for writing the flash memory to the flash memory. A data storage method for storing data signals input through a plurality of channels in a flash memory unit allocated to each channel, A first step of converting a data signal input from any one channel into a bus size of a system bus; A second step of writing the size-converted data signal into an internal page buffer of an arbitrary flash memory device connected to the channel, and then applying a write command to move the data written in the page buffer to a memory cell for storage; While the data is moved to the memory cell of the arbitrary flash memory device in the second step, after writing data to the internal page buffer of another flash memory device, data is written to the page buffer by applying a write command to the memory cell. Moving to and storing in the third step; A fourth step of repeatedly performing the second to third steps to continuously store data signals input from the channels in the plurality of flash memory devices; And And a fifth step of simultaneously performing the first to fourth steps with respect to each channel to simultaneously store data input through all channels. 6. The method of claim 5, wherein the second to third steps include providing the same address information to the flash memory unit of each channel, and writing the size-converted data signal to the flash memory device of the corresponding address. Data storage method using a flash memory. 7. The method of claim 6, wherein the address information includes a column address, a device address, and a page address of the flash memory device.