KR100276772B1 - Digital television signal receiver decimates baseband digital television signals before channel lighting - Google Patents

Abstract

The present invention provides a radio receiver using the same tuner to receive a selected DTV signal regardless of whether the digital television (DTV) signal to be received is a quadrature amplitude modulation (QAM) signal or a residual sideband (VSB) signal. In the radio receiver of the present invention, the final IF signal is digitized at a rate corresponding to a multiple of both symbol frequencies of the QAM and VSB signals so that they can be synchronized to the base. The carrier frequencies of the QAM and VSB final IF signals are adjusted to be multiples of multiples of both symbol frequencies of the QAM and VSB signals by applying an automatic frequency and phase control (AFPC) signal generated in a digital circuit to the local oscillator of the tuner. . The baseband DTV signals obtained by synchronizing the final IF signals have a sample rate higher than the symbol rate to facilitate symbol synchronization. The baseband DTV signals are decimated at symbol rate before performing channel equalization to reduce the number of multipliers required in the channel equalization filter.

Description

Digital television signal receiver decimating baseband digital television signals before channel lighting

The present invention relates to digital television (DTV), such as digital high definition television (HDTV) signals transmitted using quadrature amplitude modulation (QAM) or vestigial sideband (VSB) amplitude modulation of the main carrier. A wireless receiver having a reception function for a signal.

The digital television standard, published by the Advanced Television Systems Committee (ATSC) on September 16, 1995, is an example of the 6 MHz bandwidth television channel currently used for wireless broadcasting of National Television System Committe (NTSC) analog television signals in the United States. Remaining sideband (VSB) signals used for the transmission of digital television (DTV) signals are specified. The VSB DTV signal is designed so that its spectrum is easily interleaved with the spectrum of the co-channel interfering NTSC analog TV signal, which designates the main amplitude modulation sideband frequency of the pilot carrier and DTV signal horizontally. Between even multiples of a quarter of the scan line speed are located at odd multiples of one quarter of the horizontal scan line speed of the NTSC analog TV signal. In this regard, most of the energy of the luminance and chromatic components of the co-channel interfering NTSC analog TV signal is present in the even multiples. The video carrier of the NTSC analog TV signal is offset by 1.25 MHz from the lower limit frequency of the television channel. Further, the carrier of the DTV signal is offset from the video carrier of the NTSC analog TV signal as described above by 59.75 times the horizontal scanning line speed of the NTSC analog TV signal, and is located about 309,877.6 Hz away from the lower limit frequency of the television channel. Thus, the carrier of the DTV signal is located about 2,690,122.4 Hz away from the center frequency of the television channel. The exact symbol rate according to the digital television standard is 684/286 times the sound carrier offset by 4.5 MHz from the video carrier of the NTSC analog TV signal. Here, "684" represents the number of symbols per horizontal scan line of the NTSC analog TV signal, and "286" represents the horizontal scan line speed of the NTSC analog TV signal so as to obtain an audio carrier offset by 4.5 MHz from the video carrier of the NTSC analog TV signal. Represents an argument that is multiplied by. The symbol rate is a symbol rate corresponding to 10.762238 * 10 ⁶ symbols per second, and the symbol rate may be included in a VSB signal extending by 5.38119 MHz from the DTV signal carrier. That is, the VSB signal can be limited to a band extending by 5.690997 MHz from the lower limit frequency of the television channel.

According to the ATSC specification for digital HDTV signal terrestrial broadcasting in the United States, either of two high definition television (HDTV) formats having a 16: 9 aspect ratio can be transmitted. One HDTV format is a 2: 1 field interlaced scan method, which uses 1,920 samples per scan line and 1,080 effective horizontal scan lines per 30 Hz frame. Another HDTV format is sequential scanning, which uses 1,280 luminance samples per scan line and 720 sequential scan lines of television images per 60 Hz frame. The ATSC standard also allows transmission of DTV formats other than HDTV format, such as parallel transmission of four television signals with normal clarity compared to NTSC analog television signals.

DTV signals transmitted by residual sideband (VSB) amplitude modulation (AM) for terrestrial broadcasting in the United States are a sequence of data fields with time continuity, including 313 data segments, each with continuity in time. It contains them. There are 832 symbols in each data segment. Thus, with a symbol rate of 10.76 MHz, each data segment has a duration of 77.3 microseconds (ms). Each data segment starts with a four symbol line synchronization codegroup with successive + S, -S, -S and + S values. The value + S is one level below the maximum positive data regression point, and the value -S is one level above the maximum negative data regression point. The initial line of each data field contains a field sync code group that encodes the training signal used for channel equalization and multipath suppression. The training signal consists of one 511-sample pseudonoise sequence ("PN sequence") followed by three 63-sample PN sequences. The middle of the 63-sample PN sequences has a complementary relationship of 1 with respect to the first logic rule in the first line of each odd-numbered data field and with respect to the first logic rule in the first line of each even-numbered data field. Having a second logic definition. The remaining two 63-sample PN sequences and the 511-sample PN sequences are sent according to the same logic specification in all data fields.

The data in the data lines are trellis coded using 12 interleaved trellis codes, which are two-third rate trellis codes each with one uncoded bit. The interleaved trellis code is processed with a Reed-Solomon forward error correction coding scheme, which provides for correction of burst errors from noise sources such as automotive ignition systems, which are almost non-blocking in terms of noise. Will be. The Reed-Solomon coding result is transmitted as a symbol code of 8-level (3 bits / symbol) one-dimensional structure in the case of radio transmission, which is performed without precoding symbols separately from the trellis coding procedure. In addition, the Reed-Solomon coding result is transmitted as a symbol code of 16-level (4-bit / symbol) one-dimensional structure for cable broadcasting, in which case the transmission is performed without precoding. The VSB signal has a unique carrier whose amplitude will vary with the percentage of suppressed modulation.

The unique carrier is replaced with a pilot carrier of constant amplitude corresponding to a predetermined modulation percentage. This constant amplitude pilot carrier is generated by shifting, i.e., shifting, the direct current component of the modulation voltage applied to the balance modulator that generates the amplitude modulated sideband signal. The amplitude modulated sideband signal is provided to a filter which supplies a VSB signal as a response signal. If eight levels of the 3-bit symbol code have a normalization value of −7, -5, -3, -1, + 1, + 3, + 5, and +7 in the carrier modulated signal, then the pilot carrier is equal to 1.25. It has a normalization value. In this case, the normalized value of + S is +5, and the normalized value of -S is -5.

VSB signals using 8-level symbol coding may be used in wireless broadcasting systems in the United States, and VSB signals using 16-level symbol coding may be used in wireless narrowband broadcasting systems or cable broadcasting systems. However, in the case of predetermined cable broadcasting, broadcasting is easily performed using a suppressed carrier quadrature amplitude modulation (QAM) signal instead of using a VSB signal. Accordingly, television receiver designers must solve the problem of designing a receiver capable of receiving all types of transmission signals and automatically selecting a receiver suitable for the type of transmission currently being received.

Assume that the data format provided for symbol coding is the same for both the VSB DTV signal transmitter and the QAM DTV signal transmitter. VSB DTV signals modulate the amplitude of only one phase of the carrier at a symbol rate equivalent to 10.76 * 10 ⁶ symbols per second to provide a real signal that is not accompanied by an imaginary signal. The real signal is in the 6 MHz band because of the VSB characteristic of placing the carrier at the edge of the band. Thus, QAM DTV signals that modulate two quadrature phases of a carrier to provide a complex signal consisting of real and imaginary signal components are designed to have a symbol rate corresponding to 5.38 * 10 ⁶ symbols per second. The complex signal is in the 6 MHz band due to the QAM characteristic that places the carrier in the middle of the band.

Assuming that the data format provided for symbol coding is the same in both the VSB DTV signal transmitter and the QAM DTV signal transmitter, processing after symbol decoding is performed in a similar manner in both the receiver for the USB DTV signal and the receiver for the QAM DTV signal. The data reconstructed by symbol decoding is supplied as an input signal to a data deinterleaver, and the deinterleaved data is supplied to a Reed-Solomon decoder. The error corrected data is applied to a data de-randomizer that reproduces the data packet for the packet decoder. Some selected ones of the data packets are used to play the audio portion of the DTV program, and some other selected packets are used to play the video portion of the DTV program.

Among the zero intermediate frequency (ZIF) receivers performing amplification and channel selection in the baseband, receivers used to receive a QAM DTV signal are not suitable for receiving a VSB DTV signal. This is because there is a problem in ensuring proper adjacent channel rejection of the ZIF receiver, which must be done when the carrier is not located at the center frequency of the channel. If the receivers are in superheterodyne form, the tuners used for the receiver for the VSB DTV signal and for the receiver of the QAM DTV signal are quite similar to each other when the receivers are in the super heterodyne form. These receivers differ in the syncrodyning process and the symbol decoding process used to convert the final IF signal to baseband. Designing a receiver that can receive both VSB DTV signals and QAM DTV signals, unless duplicated the similar tuner circuits used prior to base synchro- ning and the symbol receiver circuits used following the symbol decoding circuitry. Is more economic. In this case, the problem is to optimally configure the circuit for base synchro- dinning and symbol decoding for both relevant DTV transmission criteria, and to automatically select an appropriate reception mode for the currently received DTV transmission signal. It is.

DTV signal wireless receivers have been used in field testing of HDTV systems used in the development of the ATSC standard, and are known to use a double conversion in a tuner with synchronization detection. For such a receiver, the first local oscillation frequency generated by the frequency synthesizer is heterodyned with the received USB DTV signal to generate a first intermediate frequency (e.g., comprising a 920 MHz center frequency and a 922.69 MHz carrier). . The first intermediate frequencies are selected from the image frequencies by a passive LC bandpass filter and then amplified by a first intermediate frequency amplifier, the amplified first intermediate frequency ceramic resonant filter removing adjacent channel signals. Is filtered by. The first intermediate frequency is heterodyned with a second local oscillation frequency to generate a second intermediate frequency (eg, comprising a 46.69 MHz carrier). The second intermediate frequency is selected from the remaining adjacent channel response signals of the corresponding image frequencies by a filter which may be a surface acoustic wave (SAW) type, and then amplified by the second intermediate frequency amplifier. The response signal from the second intermediate frequency amplifier is supplied to the third mixer and synchronized to the base with the third local oscillation signal of a fixed frequency. The third local oscillation signal of the fixed frequency may be supplied in phases of 0 ° and 90 °, so that in-phase and quadrature synchronous detection operations are separately performed during synchro-dinning. Here, synchro-dining mixes the modulated signal with a wave having the same fundamental frequency as the carrier of the modulated signal and whose frequency and phase are locked, and low-pass filtering the result of the mixing, The process of restoring a modulated signal at the baseband extending from frequency to the highest frequency of the modulated signal.

Digitizing the in-phase and quadrature-phase synch detection results generated by the analog system separately causes a problem of satisfactorily tracking the synch detection results after the digitization process. A prominent phase error, which is considered to occur, is generated. These problems can be avoided in the case of DTV signal radio receivers in the form of in-phase and quadrature synchronous detection processes in digital systems. For example, when the response signal of the first intermediate frequency amplifier is digitized at a rate corresponding to twice the Nyquist rate of symbol coding, successive numbers of samples are sequentially numbered according to their generation order. The samples are then divided into odd and even samples to produce corresponding in-phase (or real) and quadrature (or imaginary) synchronous detection results. Quadrature phase (or imaginary) synchronous detection is performed after Hilbert transforming a series of samples using appropriate finite-impulse-response (FIR) digital filtering, Phase (or real) synchronous detection is performed after delaying the samples for a time equal to the delay time of the Hilbert transform filter. The methods of locking the frequency and phase of synchronization detection and the methods of locking the frequency and phase of symbol coding in the VSB DTV receiver and the QAM DTV receivers are different.

In the known DTV signal radio receivers of this type, there are some problems with the design of the receiver tuner part because the carrier frequencies of the VSB DTV signal and the QAM DTV signal are not the same. That is, the carrier frequency of the QAM DTV signal is located at the center of a 6 MHz wide TV channel, but the carrier frequency of the VSB DTV signal is about 310 kHz higher than the lower limit frequency of the TV channel. The third local oscillation signal of a predetermined frequency used for the purpose of differentiating the frequency when the QAM DTV signals are synchronized with the base and the VSB DTV signal is synchronized with the base is required. The difference between the two carrier frequencies is 2.69 MHz, which is greater than the frequency difference that can be adjusted by applying automatic frequency and phase control to the third local oscillator. Thus, in practice it is necessary to use a third oscillator that can switch between two frequency stabilized crystals. Of course, for this configuration, the tuner circuit is also modified to include a configuration for automatic selection of an appropriate reception mode for the currently received DTV transmission signal. However, the reliability of the tuner is reduced because of the radio switching function required as described above. In addition, the cost of the tuner is increased because of the high frequency switching for the second oscillator and the additional frequency stabilizing crystal.

Digital television signal wireless receivers whose final intermediate frequency signals are not in the baseband but in the 1-8 MHz range are cited herein and are referred to herein as "DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER, AS FOR INCLUSION IN AN HDTV RECEIVER". Mr. B. granted 26 characters per month. And those described in US Pat. No. 5,479,449 to C.B. Patel. Reference is made herein to the use of infinite impulse response filters for generating complex digital carriers in such receivers and referred to herein as "DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING RADER FILTERS, AS FOR USE IN AN HDTV RECEIVER" 1996 Mr. B., granted August 20, US Pat. No. 5,548,617 to C.B. Patel. Regarding use in finite impulse response filters for generating complex digital carriers in such receivers, incorporated herein by reference and entitled "DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING NG FILTERS, AS FOR USE IN AN HDTV RECEIVER" C. B. filed December 22, 1995. US Pat. Appl. No. 08 / 577,469 to Mr. Patel. A design for a QAM / VSB receiver that is capable of processing both QAM and VSB signals through the same intermediate frequency amplified receivers is referred to herein and described as "HDTV SIGNAL RECEIVER WITH IMAGINARY-SAMPLE-PRESENCE DETECTOR FOR QAM / VSB". C.B., patented April 25, 1996 under the name of MODE SELECTION. US Pat. No. 5,606,579 to C.B. Patel. In addition, C.B., issued February 25, 1997, under the name "DIGITAL VSB DETECTOR WITH FINAL IF CARRIER AT SUBMULTIPLE OF SYMBOL RATE, AS FOR HDTV RECEIVER". US Pat. No. 5,606,579 to C.B. Patel. In addition, the present specification, C. B., patented as "DIGITAL TV DETECTOR RESPONDING TO FINAL-IF SIGNAL WITH VESTIGIAL SIDEBAND BELOW FULL SIDEBAND IN FREQUENCY". US Pat. No. 5,659,372 to C.B. Patel is cited. In addition, in the present specification, a C. B. patent filed on June 28, 1994 under the name "RADIO RECEIVER FOR RECEIVING BOTH VSB AND QAM DIGITAL HDTV SIGNALS". United States Patent Application No. 08 / 266,753 by Mr. Patel is cited. In addition, the specification, "RADIO RECEIVERS FOR RECEIVING BOTH VSB AND QAM DIGITAL HDTV SIGNALS", is incorporated herein by reference. US Pat. No. 5,715,012 to C.B. Patel. All of the above patents and patent applications are already assigned to Samsung Electronics (Samsung Electronics, Co., Ltd.) under the employment invention contract at the time the inventions described therein are completed.

For the QAM / VSB radio receivers described in US Pat. Nos. 5,506,636 and 5,715,012, the final intermediate frequency signal is digitized, and the synchro- dining processes to obtain baseband samples are performed in a digital scheme. The tuner embedded in the receiver selects one of the channels corresponding to the different positions of the frequency band used to transmit the DTV signals, and the final received intermediate-frequency signal of the selected channel. A series of mixers for multiple conversion into a (IF) signal, frequency selector amplifiers respectively located between mixers adjacent to each other in the processing sequence among the mixers, and a local supplying oscillation signal to each of the mixers. It contains oscillators. The local oscillators each supply an oscillation signal of approximately the same frequency regardless of whether the selected DTV signal is a QAM signal or a VSB signal. The final IF signal is digitized, and in this state, there is a difference in signal processing depending on whether the selected DTV signal is a QAM signal or a VSB signal. To be controlled at. If the final digitized IF signal is a QAM signal, the QAM synchro-dining circuit synchronizes the final IF signal to the base. If the final digitized IF signal is not a QAM signal, the final IF signal should be synchronized to the base. The final IF signal is processed differently as being a QAM signal to generate real and imaginary sample streams of interleaved QAM symbol codes. If the final digitized IF signal is a VSB signal, the VSB synchro- dinning circuit synchronizes the final IF signal as a base. If the final digitized IF signal is not a VSB signal, the final IF signal should be synchronized as a base. The final IF signal is processed differently as a VSB signal to generate a real sample stream of the interleaved VSB symbol code. The detector detects the presence of a pilot carrier accompanying the VSB-type DTV signal and determines whether the final IF signal is a VSB signal, and if the final IF signal is not clearly a VSB signal, the detector returns to the first state. And the final IF signal is clearly a VSB signal, generating a control signal that is in the second state. The radio receiver is automatically switched to operate in the QAM signal reception mode in response to the control signal in the first state, and automatically switched to operate in the VSB signal reception mode in response to the control signal in the second state.

U.S. Patent No. 5,506,636, U.S. Patent Application No. 08 / 266,753, and U.S. Patent Application No. 08 / 614,417, as previously proposed by the ATSC subcommittee, increase the carrier frequency of the VSB DTV signal by 625 kHz above the lowest channel frequency. The assumption is high. This specification assumes that the carrier frequency of the VSB DTV signal is 310 KHz above the lowest channel frequency, as specified in Appendix A of the Digital Television Standard, published September 16, 1995.

Preferably, the carrier of the final IF signal is a predetermined subharmonics of a multiple of symbol frequencies of both the QAM signal and the VSB signals when the selected DTV signal is a QAM signal, and when the selected DTV signal is a VSB signal. Other predetermined harmonics (subharmonics) of the multiples. When the carrier frequency of the VSB DTV signal is nominally higher by 310 KHz than the lowest channel frequency, the predetermined low harmonics should have a frequency difference of approximately 2.69 MHz. Digitizing the final IF signal at this multiple of the symbol frequencies of both the QAM and VSB signals can facilitate the generation of a digital carrier used to base-synchronize the QAM and VSB final IF signals as a basis. This multiple of the symbol frequencies of both the QAM signal and the VSB signals should be low enough to effect digitization, but preferably higher than the Nyquist rate.

In one form of such QAM / VSB radio receivers, the predetermined low harmonic of a multiple of the symbol frequency of the QAM signal is actually higher in frequency by 2.69 MHz than the predetermined low harmonic of the multiple of the symbol frequency of the VSB signal. In the preferred receiver, the QAM carrier frequency in the final IF signal is 5.38 MHz, the first harmonic is 10.76 MHz, and the VSB signal carrier frequency in the final IF signal is 2.69 MHz. The third harmonic is 10.76 MHz.

In another form of such QAM / VSB radio receivers, the predetermined low harmonic of a multiple of the symbol frequency of the QAM signal is actually lower in frequency by 2.69 MHz than the predetermined low harmonic of the multiple of the symbol frequency of the VSB signal. According to embodiments of the present invention, a VSB signal whose full sideband is lower than the carrier frequency of the final IF signal is sampled to improve resolution. In a preferred embodiment of the present invention, the VSB carrier of the final IF signal has a frequency of 5.38 MHz, the first low harmonic has a frequency of 10.76 MHz, the QAM signal carrier of the final IF signal has a frequency of 8.07 MHz, and the third harmonic. The third harmonic of has a frequency of 10.76 MHz.

When performing synchro-dinning in a digital system, the final IF signal of both the QAM and VSB signals can be digitized at a sampling rate that is a multiple of the symbol rates for the QAM and VSB signals. Carrier generation can be easily performed. Accordingly, it is also possible to easily phase lock the frequency of the carrier used to synchronize the carrier of the QAM signal and the VSB signals to the base.

Digitizing the QAM and VSB signals at multiples of their symbol rates can facilitate symbol synchronization, whether performed in the digital scheme proposed by Patel or in the analog scheme. In order to perform symbol synchronization satisfactorily, digital samples must be provided at a sample rate that is at least twice the symbol rate. Supplying digital samples at a rate higher than the symbol rate increases the number of taps in the digital filters used for channel equalization of the baseband DTV signal, because sampling at any particular ghost This is because the number of times increases in direct proportion to the ratio of the sampling rate to the symbol rate. When digitizing a QAM or VSB DTV signal at a multiple of MN times its symbol rate, where M is a positive integer greater than or equal to 1 and N is a positive integer greater than or equal to 2, the digital DTV baseband signal is N: 1 decibeled before its channel equalization. In this case, the decimated digital signal must satisfy the Nyquist criterion for symbol transmission.

According to one aspect of the invention, the digitized DTV signal is decimated before its channel equalization, thereby reducing the number of samples in the kernel of digital filters for performing channel equalization, thereby substantially reducing the cost of the DTV receiver. Will decrease.

If the digitized VSB signal is decimated at a sampling rate less than twice its symbol rate (especially the same sampling rate as the symbol rate), the symbol synchronization is performed before the decimation process so that symbol information is not lost during the decimation process. Need to be achieved. One feature of the present invention is to perform symbol synchronization before such decimation process. Another aspect of the present invention is to extract a signal related to the required symbol rate and timing from the baseband DTV data, the frequency between the extracted signal and the sampling rate of the analog-to-digital converter included in the radio receiver of the DTV receiver and Detecting a phase error, applying the detected frequency and phase error to the controlled oscillator as an automatic frequency and phase control signal, and determining a sampling rate of the analog / digital converter from the oscillation signal of the controlled oscillator. A method of symbol synchronization comprising generating a signal.

The present invention selects a reception channel, converts the DTV signal into an intermediate frequency for filtering and amplifying the selected channel, and synchronizes the analog final intermediate frequency output signal outputted as a result of the filtering and amplification as a base to generate a baseband signal. It is implemented in a DTV receiver including a radio receiver for generating. The DTV receiver may be designed to receive a QAM DTV signal, a VSB DTV signal, or both types of DTV signal. The wireless receiver includes an analog / digital converter (ADC) for sampling and digitizing one of the signals, so that the wireless receiver supplies a baseband signal as a first digital sample stream representing the baseband signal. It is supposed to be done. The radio receiver also includes a sample clock generator for supplying a sample clock signal for timing sampling by the ADC, whereby the first digital sample stream is a predetermined multiple of MN times the symbol rate of the DTV signal. Have approximately the same sample rate. Here, MN is the product of one or more positive numbers M and two or more positive integers N. The radio receiver also receives the first digital sample stream and, in response, only every Nth digital samples of the first digital sample stream at a sample rate corresponding to 1 / N of the sample rate of the first digital sample stream. A decimator for generating the second digital sample stream to be reproduced is included. The number of taps required to generate a channel equalization response signal in the channel equalizer performing channel equalization is reduced by the N: 1 decimation process of the second digital sample stream. As a result, the number of digital multipliers is reduced, providing significant advantages in terms of cost and reliability. The DTV receiver also includes a symbol synchronizer for correcting a symbol phase error in the response signal of the channel equalizer, and decodes the symbols in the response signal of the channel equalizer while decoding the symbol phase error while correcting the symbol phase error. It includes a symbol decoder that restores the corresponding bit groups.

In a preferred embodiment of this type of DTV receiver, the sample clock generator generates an oscillation signal for supplying an oscillation signal at a frequency controlled by an automatic frequency and phase control signal, and generates the sample clock signal at a rate responsive to the oscillation frequency. Wherein the symbol synchronizer comprises: an FIR filter for selecting only a signal of a predetermined symbol rate low frequency from the first digital sample stream; and the predetermined symbol rate low selected from a sampling rate of an ADC and a response signal of the FIR filter. It includes an automatic frequency and phase control detector for detecting the frequency and phase error of the wave.

According to another aspect of the invention, an automatic frequency and phase control (AFPC) signal is sent for a controlled oscillator used to timing the samples supplied from the sample clock generator. Generating from a symbol code without a frequency, the controlled oscillator can synchronize with the symbols of the baseband DTV signal. This is accomplished by applying the baseband DTV signal symbol code to a narrowband finite impulse response (FIR) filter that is timed by the samples supplied from the sample clock generator. Narrowband FIR digital filters are added with a nonlinear process to generate second harmonics, such as squaring, to reproduce the complementary frequency with noise spectrum. An error in the oscillation frequency of the controlled oscillator is detected for the complementary frequency reproduced by the automatic frequency and phase control detector, which provides a low pass filtered response signal for the error signal applied to the controlled oscillator as an AFPC signal. .

1 includes a circuit for detecting symbols in a QAM-type DTV signal, a circuit for detecting symbols in a VSB-type DTV signal, and an amplitude and group delay equalizer for symbols selected from the two detection circuits. A block diagram showing ultra-short ends of a DTV receiver of a type that can implement the invention,

FIG. 2 is a block diagram showing the remaining portions of the DTV receiver, although not shown in FIG.

3 are circuits used in the DTV signal radio receiver of the type shown in FIGS. 1 and 2, a digital circuit for synchronizing QAM DTV signals as a base, and a digital circuit for synchronizing VSB DTV signals as a base; A detailed block diagram of the circuits involved in the application of input signals to the two digital circuits,

4 is a circuit included in certain DTV signal radio receivers of a type that can implement the present invention, which is used to synchronize a sample clock generator, digital QAM signals and digital VSB signals based on their respective final IF signal frequencies. A detailed block diagram of a circuit providing ROMs for supplying digital description signals of complex carriers, and address generators for the ROMs,

FIG. 5 is a circuit similar to that of FIG. 4, with base address synchronization and digital VSB signals for ROMs supplying digital description signals of complex carriers used to base digitally synchronize the QAM signals. A detailed block diagram of a circuit in which an address generator for ROMs supplying digital description signals of complex carriers used to make the configuration share an address counter,

6 is a circuit for converting digital samples into a complex form in DTV signal radio receivers embodying the present invention, including a Hilbert transform filter for generating imaginary samples from real samples, which is equivalent to the delay of the filter. Detailed block diagram of a circuit with delay compensation for real samples,

FIG. 7 is a known circuit that can be used to convert digital samples into complex form in a DTV signal radio receiver embodying the present invention, which is designed based on a Jacobian elliptic function and is constant for digitized baseband signals. a detailed block diagram of a pair of infinite-impulse-response (IIR) type prepass digital filters representing a phase response difference of π / 2,

8 and 9 are block diagrams illustrating a modified configuration made for the filter circuit of FIG. 7 to eliminate transient delays;

10 is a circuit that can be used to convert digital samples into a complex form in a DTV signal radio receiver embodying the present invention, a pair of finite impulse responses exhibiting a constant π / 2 phase response difference for digitized baseband signals. detailed block diagram of (finite-impulse-response) (FIR) type prepass digital filters,

FIG. 11 is a graph showing constraints on final intermediate frequencies frequency-converted from carriers of a QAM DTV signal and a VSB DTV signal, in which a carrier of a VSB DTV signal has a frequency lower than that of a QAM DTV signal in a final IF signal. Ie the final sideband of the VSB DTV signal has a higher frequency than its residual sideband in the final IF signal, and when the sample rate in the digitization process is limited to a rate equivalent to 21.52 * 10 ⁶ samples per second. A graph showing constraints on intermediate frequencies,

12 is a graph showing constraints on the final intermediate frequencies frequency-converted from the carriers of the QAM DTV signal and the VSB DTV signal, in which the carrier of the VSB DTV signal has a higher frequency than the carrier of the QAM DTV signal in the final IF signal. Ie the final sideband of the VSB DTV signal is lower in frequency than its residual sideband in the final IF signal, and when the sample rate in the digitization process is limited to a rate of 21.52 * 10 ⁶ samples per second. A graph showing constraints on intermediate frequencies,

FIG. 13 is a block diagram showing a part of another type of DTV receiver that can implement the present invention, in which data synchronization recovery schemes are different from those of FIG.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the block diagram of the accompanying drawings, the connection configuration for the clock signal or the control signal is indicated by a dotted line only when it is necessary to distinguish the connection configuration for the controlled signals. In addition, in order to simplify the illustration, some intermediate delay elements have been omitted so that the designer of the circuit or system may consider it necessary for the digital circuit.

1 shows a multi-conversion tuner 5 consisting of components 11 to 21, which is one of the channels corresponding to different positions in the frequency band for the DTV signal. Is selected to perform a plurality of frequency conversions on the final intermediate frequency signal of the final intermediate frequency band in this selected channel. 1 also shows a broadcast receiving antenna 6 which is arranged to capture DTV signals for the multi-conversion tuner 5. In another embodiment, the multiple conversion tuner 5 may be connected to receive DTV signals from a narrow broadcast reception antenna or a cable broadcasting transmission system.

In particular, in the case of the multi-conversion tuner 5 shown in FIG. 1, the frequency of the first local oscillation signal is determined by the channel selector 10 designed for human operation, and the frequency of the first local oscillation signal is The frequency synthesizer 11, which acts as a first local oscillator, is supplied to the first mixer 12 and is heterodyned with the DTV signals received from the antenna 6 or other DTV signal source. The first mixer 12 upconverts the signals received on the selected channel to a predetermined first intermediate frequency (e.g., has a carrier of 922.69 MHz) and is supplied from the first mixer 12. The LC image removal filter 13 is used to remove unwanted image frequencies occurring as a result of the frequency upconversion. The first intermediate frequency signal generated by the rising frequency conversion and supplied as a response signal of the LC image removing filter 13 is supplied to the first intermediate frequency amplifier 14 (hereinafter referred to as "first IF amplifier 14"). Applied as an input signal, the first IF amplifier 14 thus supplies an amplified first IF signal for driving a filter composed of a first SAW filter 15 or ceramic resonators. The first SAW filter 15 may easily have a plurality of poles and zeros according to the rising conversion of the first intermediate frequencies which are somewhat high frequency. The band of the first SAW filter 15 is determined so as to pass frequencies obtained by converting frequencies in the range from the lower limit frequency of the television channel to about 300 kHz, the upper limit frequency of the television channel. Preferably, the SAW filter 15 is designed to remove frequency-modulated voice carriers of coherent NTSC analog TV signals of the same channel. The second mixer 17 connected to the first SAW filter 15 is supplied with a second local oscillation signal generated from the second local oscillator 16 to be hetero-dined with the response signal of the first SAW filter 15. As a result, a second intermediate frequency (for example, having a carrier of 46.69 MHz) is generated. A second SAW filter 18 is used to reject unwanted video frequencies that occur as a result of the frequency down conversion supplied from the second mixer 17, which is a digital signal from NTSC television transmission. It may contain mainly traps for audio and video carriers of NTSC television signals transmitted on adjacent channels during the transition to television transmission. The second IF signal supplied as a response signal of the second SAW filter 18 is applied to the second IF amplifier 19 as an input signal, and in response to the input signal, the second IF amplifier 19 is amplified. A second IF signal response signal is generated. In the third mixer 21 connected to the second IF amplifier 19, the amplified second IF signal response signal is heterodyne with the oscillation signal from the third local oscillator 20. The multi-conversion multi-tuner tuner 5 described so far is except that the frequency of the oscillation signal generated from the third local oscillator 20 is selected so that the third mixer 21 can supply the third IF signal response signal. Is similar to the existing tuners.

The third IF signal response signal is the final intermediate frequency output signal of the multi-conversion tuner 5, which is then referred to as a subsequent analog-to-digital converter (ADC) 22 (hereinafter referred to as " bandpass ADC 22 ") for digitization. Is referred to). The final intermediate frequency output signal has a 6 MHz wide frequency band where the lowest frequency is higher than the zero frequency. The low band analog filtering of the third mixer 21, which is performed as a preliminary step of the analog / digital conversion in the bandpass ADC 22, removes the image frequencies of the third intermediate frequency, and the second SAW filter 18 has already been removed. The bandwidth of the third intermediate frequency signals to be digitized, applied to the bandpass ADC 22, is in a limited state, and thus the bandpass ADC 22 acts as a band analog / digital converter. Sampling of the low pass analog filter response signal, which is performed in the band pass ADC 22 as a next step of the analog / digital conversion, is made in response to the pulses of the first clock signal supplied from the sample clock generator 23.

The sample clock generator 23 preferably includes a crystal oscillator capable of frequency control in a relatively narrow range so as to generate cissoidal oscillation signals at multiples of the symbol rate. A symmetrical clipper or limiter is used to generate a first clock signal that is used for timing the sampling of the final IF signal after filtering to limit the bandwidth in the bandpass ADC 22 for the seesawed oscillation signal. Generates a square wave response signal. The frequency of the seesaw oscillating signal generated by the crystal oscillator provided in the sample clock generator 23 is generated in response to received DTV signal components which are symbol harmonics or baud rates as described below. Can be determined by automatic frequency and phase control (AFPC) signals. The pulses of the first clock signal are twice the symbol rate for VSB signals corresponding to 10.76 * 10 ⁶ symbols per second and four times the symbol rate for QAM signals corresponding to 5.38 * 10 ⁶ symbols per second. The symbol rate is repeated corresponding to 21.52 * 10 ⁶ symbols per second. At the symbol rate corresponding to 21.52 * 10 ⁶ symbols per second, if the final IF signal has a median frequency of more than 5.38 MHz, the number of samples of the QAM carrier at the symbol rate corresponding to 21.52 * 10 ⁶ symbols per second is 4 Only, and as a result, the uniformity of the synchine response signal supplied for symbol decoding is undesirably reduced.

The bandpass ADC 22 supplies a 10-bit real digital response signal or equivalent resolution signal to samples of the final IF signal with reduced frequency band, which is a circuit 24 (hereinafter " real / complex "). Sample converter 24 ") to convert the complex digital samples. Various methods are known for configuring the real / complex sample converter 24. Imaginary digital samples at the QAM carrier frequency may be generated using a Hilbert transform filter as described, for example, in US Pat. No. 5,479,449. If the frequency band of 6 MHz of the final IF signal has a minimum frequency of at least 1 megahertz or the like, keep the number of taps in the Hilbert transform filter moderately small, thereby keeping the filter's waiting time moderately short. It is possible. Another configuration for the real / complex sample converter 24 is as described in US Pat. No. 5,548,617 between the responses of two IIR (infinite-impulse-response) filters that are approximately equal to a phase difference of 90 ° at all frequencies. The use of the differential delay is mentioned. Another configuration for the real / complex sample converter 24 is to use a differential delay between the responses of two finite-impulse-response (FIR) filters that are approximately equal to a phase difference of 90 ° at all frequencies. .

In the receiver circuit of FIG. 1, the complex digital samples of the final IF signal supplied from the real / complex sample converter 24 are applied to a circuit 25 which synchronizes the QAM signal as the basis. The circuit 25 supplies a stream of real samples and a stream of imaginary samples in parallel to the symbol deinterleaver 26 to provide a baseband description signal of the QAM modulated signal. The QAM synchro-dining circuit 25 read-only memory (ROM) 27 (hereinafter referred to as a "QAM complex carrier") a complex digital representation signal for two phases of a QAM carrier transformed into a final intermediate frequency and orthogonal to each other. ROM 27 ". The QAM complex carrier ROM 27, which includes a sine and cosine look-up table for the QAM carrier frequency, is addressed by the first address generator 28. The first address generator 28 includes an address counter (not clearly shown in FIG. 1) for counting recurrent clock pulses in the first clock signal generated by the sample clock generator 23. . The resulting address coefficient value is increased by a symbol phase correction term generated by the QAM de-rotator to generate an address signal for the QAM complex carrier ROM 27. The configuration and operation of the QAM synchrodining circuit 25 and the first address generator 28 will be described in more detail below.

The complex digital samples of the final IF signal supplied from the real / complex sample converter 24 in the receiver circuit of FIG. 1 are also circuit 30 for synchronizing the VSB signal to the base (hereinafter referred to as " VSB synchronization circuit 30 "). Is called). The VSB synchro-dining circuit 30 supplies streams of samples representing real and imaginary components of the residual sideband (VSB) modulated signal that is base-synchronized. The VSB synchro- dinning circuit 30 receives complex digital representation signals for two phases of the VSB carrier that are converted to the final intermediate frequency and are orthogonal to each other from a read-only memory (ROM) 31. do. The ROM 31 (hereinafter referred to as " VSB complex carrier ROM 31 ") that includes a sine and cosine look-up table for the VSB carrier frequency is addressed by the second address generator 32. The second address generator 32 includes an address counter (not clearly shown in FIG. 1) for counting cyclic clock pulses in the first clock signal generated by the sample clock generator 23. In the alternative embodiment of the present invention, the address counter is the same as the address counter used in the first address generator 28. The resulting address coefficient value is increased by the symbol phase correction term generated by the symbol phase correction circuit, thereby generating an address signal for the VSB complex carrier ROM 31. The configuration and operation of the VSB synchro-dining circuit 30 and the second address generator 32 will be described in more detail below.

A digital signal multiplexer 33 is connected to the symbol deinterleaver 26 and the VSB synchro- dinning circuit 30. The digital signal multiplexer 33 uses one of two complex digital input signals as a response signal. It serves as a synchro-dining result selector (hereinafter referred to as "synchronization result selector 33") to select. The synchronization result selector 33 is controlled by a detector 34 for detecting a zero frequency term of real samples from the VSB synchronization circuit 30 to select a signal. If the zero frequency term has essentially zero energy, indicating that there is no pilot carrier signal accompanying the VSB signal, the synchro- ning result selector 33 is basally synchronized QAM signal supplied from the deinterleaver 26. Selectively respond to a first complex digital input signal representing the de-interleaved result of. However, if the zero frequency term has a substantial energy indicating the presence of a pilot carrier signal accompanying the VSB signal, the synchro- dinating result selector 33 may add the real and imaginary components of the baseband response signal of the VSB synchro- dinning circuit 30. Selectively responds to a second complex digital input signal.

The response signal of the synchro-dining result selector 33 is resampled in response to the second clock signal from the sample clock generator 23 in a 2: 1 decimation circuit 35 to obtain a complex base response signal. The sample rate is reduced to a 10.76 MHz VSB symbol rate that is twice the 5.38 MHz QAM symbol rate. That is, 2: 1 decimation processing is performed on both the streams of real digital samples and the streams of imaginary digital samples. The 2: 1 decimation response signal of the synchro- ning result selector 33 may be applied to the equalizer 36 prior to being applied as an input signal to the amplitude and group delay equalizer 36. Reduce requirements As another example, instead of using the 2: 1 decimator 35 at the rear end of the synchro result selector 33 as described above, 2: 1 decimation can be performed at the front end of the synchro result selector 33. The base response signals of the QAM synchro dining circuit 25 and the VSB synchro dining circuit 30 may be resampled in response to the second clock signal from the sample clock generator 23.

FIG. 2 illustrates the amplitude and group delay equalizer 36 described above, wherein the amplitude and group delay equalizer 36 outputs a base response signal having amplitude and phase versus frequency characteristics that are susceptible to intersymbol error. Convert to a signal with improved amplitude versus frequency characteristics that minimizes the tendency to generate intersymbol errors. Amplitude and group delay equalizers 36 may be any suitable monolithic integrated circuits available off the shelf for use in equalizers. Such integrated circuits are multi-tap digital filters that are programmable for amplitude and group delay equalization, circuits for selectively accumulating training signals, and temporarily storing the accumulated results, and amplitude and group delay equalization. It includes a microcomputer to calculate updated tap weights of the multi-tap digital filter used for.

When the received DTV signal is in the VSB form, a training signal is included in the initial data segment of each data field. The microcomputer is programmed to compare the temporarily stored accumulation results with an ideal training signal known as "priori" and to set a series of weighting factors for the multi-tap digital filter used for amplitude and group delay equalization. Subsequently, the weighting factors are set to "RAPID-UPDATE ADAPTIVE CHANNEL-EQUALIZATION FILTERING FOR DIGITAL RADIO RECEIVERS, SUCH," as of July 15, 1997, to better compensate for changes in multipath conditions caused by the aircraft in flight. AS HDTV RECEIVERS "may be updated at a more frequent frequency using crystallographic equalization techniques as described in US Pat. No. 5,648,987, which is patented by the inventors and Dr. Jian Yang. If the received DTV signal is in the QAM form, the decision direction equalization technique should be used if the equalization should be performed without the provision of the training signal. Setting a satisfactory initial weighting factor requires more time than using a training signal. If the DTV receiver remains in place during the operating and non-operational periods, the time required to set a satisfactory set of initial weighting factors upon return of the DTV channel is determined by the example weighting factors finally determined for the DTV channel. If it is stored in memory, it can be reduced.

Both real and imaginary response signals of amplitude and group delay equalizer 36 are input to a two-dimensional symbol decoding circuit 37 which performs symbol decoding to recover the symbol decoded digital data streams from a QAM origin signal. It is applied as a signal. Assuming that the QAM original signal contains data synchronization information corresponding to the data synchronization information in the VSB original signal, one of the symbol decoded digital data streams is trellis decoded digital data supplied for further data processing. And another one of such symbol decoded digital data streams is generated by data slice processing without subsequent trellis decoding. Data synchronization information is extracted from the latter symbol decoded digital data stream, which is used to control the processing of the QAM original data by the receiver.

The real response signal of the amplitude and group delay equalizer 36 is applied as an input signal to the one-dimensional symbol decoding circuit 38 which performs symbol decoding to recover the symbol decoded digital data streams from the VSB original signal. In the case of the VSB signal according to the ATSC standard, trellis coding is used for data in all data segments except for the initial data segment of each data field including field synchronization code groups without trellis coding processing. As in the prior art, one of the symbol decoded digital data streams supplied by the symbol decoding circuit 38, which should be used for later data processing, trellis decodes the result of the data slice process. Are generated and typically optimal Viterbi decoding techniques are used. As in the prior art, used as another one of the symbol decoded digital data streams supplied by the symbol decoding circuit 38 to control data processing by the receiver in response to the synchronization information contained in the received VSB original signal. The digital data stream to be generated is generated using a data slice process without subsequent trellis decoding. The symbol decoding circuit 38 is preferably a U.S. Pat. It differs from conventional practice in that it uses a data slice technique similar to that described in US 08 / 746,520.

A digital signal multiplexer 39 is connected to the two-dimensional symbol decoding circuit 37 and the one-dimensional symbol decoding circuit 38, and the digital signal multiplexer 39 responds to one of the two digital input signals applied thereto. It functions as a data source selector (hereinafter referred to as "data source selector 39") for selecting as a signal. The data source selector 39 selects a signal by the control of a VSB pilot carrier presence detector 34 for detecting the zero frequency term of real samples from the VSB synchrodining circuit 30. When the zero frequency term has essentially zero energy, indicating that there is no pilot carrier signal accompanying the VSB signal, the data source selector 39 selectively responds to its first digital input signal as its digital data output source. A two-dimensional symbol decoding circuit 37 for decoding the symbols included in the QAM signal is selected. However, if the zero frequency term has substantial energy indicative of the presence of a pilot carrier signal accompanying the VSB signal, the data source selector 39 selectively responds to its second digital input signal in response to its VSB signal as its digital data output source. One-dimensional symbol decoding circuit 38 to decode the symbols included in is selected.

The data selected by the data source selector 39 is applied to the data deinterleaver 40 as an input signal, and the de-interleaved data supplied from the data deinterleaver 40 is applied to the Reed-Solomon decoder 41. Will be. The data deinterleaver 40 is often configured within its dedicated monolithic integrated circuit and pilot carrier presence detector to select a de-interleaving algorithm suitable for the DTV signal depending on whether the currently received DTV signal is in QAM or VSB form. It is possible to respond to the output display signals from 34, but this is merely a design matter. In addition, the Reed-Solomon decoder 41 is also often configured in its dedicated monolithic integrated circuit and pilots to select a Reed-Solomon algorithm suitable for the DTV signal depending on whether the currently received DTV signal is in QAM or VSB form. Although it is possible to respond to the output display signals from the carrier presence detector 34, this is also merely a design matter. The Reed-Solomon decoder 41 supplies error detection data to the data de-randomizer 42. In response to the error detection data, the data de-randomizer 42 transmits the renderer to the DTV receiver. Play the sized signal. The reproduced signal includes data packets for a packet sorter 43. The data de-randomizer 42 outputs signals from the pilot carrier presence detector 34 so that a data de-randomizing algorithm suitable for the DTV signal can be selected depending on whether the currently received DTV signal is in QAM or VSB form. It is configured to respond to, but this is just a simple design.

The data synchronization information included in the data output of the two-dimensional symbol decoding circuit 37 is restored by the first data synchronization recovery circuit 44, and the data synchronization information included in the data output of the one-dimensional symbol decoding circuit 38 is The second data synchronization recovery circuit 45 restores the data. A data synchronization selector 46 is connected to the data synchronization recovery circuits 44 and 45. The data synchronization selector 46 detects a zero frequency term of the real samples from the VSB synchro- dinning circuit 30. According to the control of the VSB pilot carrier presence detector 34, one of the data synchronization information provided by the first and second data synchronization recovery circuits 44 and 45 is selected. If the zero frequency term has essentially zero energy, indicating that there is no pilot carrier signal accompanying the VSB signal, the data synchronization selector 46 is provided by the first data synchronization recovery circuit 44 as its output signal. Select data synchronization information. However, if the zero frequency term has substantial energy indicating the presence of a pilot carrier signal accompanied by a VSB signal, the data synchronization selector 46 is provided by the second data synchronization recovery circuit 45 as its output signal. Select the information.

When the data synchronization selector 46 selects the data synchronization information provided by the second data synchronization recovery circuit 45 as its output signal, the initial data lines of each data field are used as amplitude and group delay equalizers as training signals. 36) to be applied.

The occurrence of the 511-sample PN sequence can be detected to provide data field indexing information to the second data synchronization selector 46 in the second data synchronization recovery circuit 45. In another embodiment, the occurrence of two or three consecutive 63-sample PN sequences in the data synchronization recovery circuit 45 is detected to provide data field indexing information to the data synchronization selector 46.

The specification for the QAM DTV signal is not as well defined as the specification for the current VSB DTV signal. 32-state QAM signals provide sufficient capacity for a single HDTV signal without the need to use compression techniques independent of the MPEG specification, but in general, some of the compression techniques not related to the MPEG specification convert a single HDTV signal into a 16-state QAM signal. It is being used to code as. Typically, the first data synchronization recovery circuit 44 detects the generation of a predetermined 24-bit word to generate data field indexing information for application to the data synchronization selector 46. The multiplexer embedded in the data synchronization selector 46 selects one of the data field indexing information supplied by the first and second data synchronization restoration circuits 44 and 45, respectively. The field indexing information is supplied to the data deinterleaver 40, the Reed-Solomon detector 41, and the data derandomizer 42. In this case, it is recorded that the training signal is not included in the QAM DTV signal. Thus, the amplitude and group delay equalizer 36 is adjusted to use a crystal directional equalization technique that does not depend on the training signal in response to the VSB pilot carrier presence detector 34 indicating the absence of a pilot carrier, and the second data synchronizer. The VSB training signal selected by the reconstruction circuit 45 is transmitted through the data synchronization selector 46 without the need for a multiplexer. In addition, as a data line synchronization signal for QAM DTV transmission, at least a data line synchronization signal other than the data line synchronization signal selected as a reference does not exist. The first data synchronization recovery circuit 44 includes a counting circuit for counting samples in each data field to generate synchronization information in the data field. The synchronization information in the data field (for example, data line coefficient values) generated by the synchronization information in the data field and the second data synchronization restoring circuit 45 may be converted into a data deinterleaver 40 and a Reed-Solomon decoder (if necessary). 41) and by the appropriate multiplexers in the data synchronization selector 46 to be applied to the data de-randomizer 42.

In Fig. 2 of US Pat. No. 5,506,636, a variation of the two-dimensional symbol decoding circuit 37 is shown, in which case the trellis decoding result and the symbol decoded data synchronization signal are the data source selector 39 and the first data synchronization. Time division multiplexing on a single bus is applied to the recovery circuit 44. Also shown in Fig. 2 of U.S. Patent No. 5,506,636 is a variant of the symbol decoding circuit 38, in which case the trellis decoding result and the symbol decoded data synchronization signal are also used for the data source selector 39 and the second data synchronization. Time division multiplexing on a single bus is applied to the recovery circuit 45. As in the embodiment shown in FIG. 2 of the accompanying drawings, the first data synchronization recovery circuit 44 and the second data synchronization recovery circuit 45 perform data synchronization by matching filtering of the result of symbol decoding. do. In the case of simply recording the initial data segment of each data field per VSB broadcast ATSC technology signal using QAM cable broadcasting symbol codes, symbol synchronization of the QAM signal can be performed to find the symbol-decoded PN sequence information and perform data synchronization. . 2 illustrates that data synchronization is performed after symbol decoding the VSB signal. This data synchronization is performed by finding symbol-decoded PN sequence information. In the case of simply recording the initial data segment of each data field per VSB broadcasting ATSC-regulated signal using QAM cable broadcasting symbol codes, it is a modification of the DTV receiver circuit of FIG. 2 after both symbol decoding and VSB signal reception and QAM signal reception. Data synchronization can be performed using the same device.

In another embodiment, a data signal synchronization during the VSB signal reception generates a spike response signal for the PN sequence in the response signal of the 2: 1 decimator 35 or the response signal of the amplitude and group delay equalizer 36. Matching filters may be used prior to symbol decoding. The matched filters for generating a spike response signal for the sync code sequences are preferably a synchro- dinning circuit (digital multiplier 29, VSB synchro- dinning circuit 30) so as to reduce the number of samples in their respective kernels. Rather than receiving the decimated response signals as an input signal, the input signals are supplied at the decimated sample rate instead. The matched filters for generating spike response signals for the sync code sequences are preferably the response signal of the amplitude and group delay equalizer 36 so that multipath reception can reduce the effect of having on data synchronization. The connection is made to receive.

FIG. 13 shows a variation of some components of the DTV receiver shown in FIG. 2, in which the data synchronization recovery circuit 45 for recovering data synchronization from the result of symbol decoding has an amplitude and group delay equalizer 36. As shown in FIG. Is replaced by a second data synchronization recovery circuit 450 employing matching filters for restoring data synchronization from the response signal. The initial data segment in each data field can be detected using one matched filter for each PN sequence of that initial data segment. It is preferable to use a matched filter for a 511-sample PN sequence as the matched filter because the matched filter for the 511-sample PN sequence has an autocorrelation response energy more than that of the matched filter for the 63-sample PN sequence. This is because it can provide higher selectivity. The matched filter for the PN sequence can also be used to identify the locations of ghosts during the calculation of the filter coefficients for the amplitude and group delay equalizers 36 and can have a dual function in this regard. Jay as of January 14, 1997. US Patent No. 5,594,506, entitled J. Yang entitled “LINE SYNC DETECTOR FOR DIGITAL TELEVISION RECEIVER”, is designed to detect a group of four symbol segment sync codes located at the beginning of each data segment. Suitable forms of are described.

The packet sorter 43 sorts data packets for different purposes in response to header codes in the consecutive data packets. Data packets representing the audio portions of the DTV program are applied to the digital sound decoder 47 by the packet sorter 43. The digital sound decoder 47 supplies left and right channel stereo audio signals to a multichannel audio amplifier 48 for driving a plurality of speakers 49 and 50. Data packets representing the video portion of the DTV program are applied to the MPEG-2 type MPEG decoder 51 (hereinafter referred to as "MPEG-2 video decoder 57") by the packet sorter 43, for example. The MPEG-2 video decoder 51 sends signals to the kinescope drive amplifier 54 for applying the red (R), green (G), and blue (B) drive signals amplified to the kinescope (53). Supply. As a variant of the DTV receiver shown in Figs. 1 and 2, other types of display devices may be used instead of or in addition to the kinescope 53, and in the case of a sound restoration system, another type, but a single audio channel. It is possible to use one that is composed of two or more complex ones than a simple stereo playback system.

Returning to FIG. 1 again, the QAM and VSB complex carrier ROMs 27, 31 are digital complex numbers of QAM and VSB signal carriers converted to respective final intermediate frequencies in response to an address signal generated according to the coefficients of the first clock signals. In order to be able to use it to generate representation signals, an apparatus for locking the final intermediate frequency, which is the carrier of the currently received DTV signal among the final intermediate frequencies, by a factor of multiple of the frequency of the first clock signal is required. Do. That is, the final intermediate frequencies must each have a predetermined ratio ratio with the first clock signal frequency. An automatic phase and frequency control (AFPC) signal is generated in a digital circuit disposed at the rear end of the bandpass ADC 22, which is the first, second and third local oscillators 11 in the multiple conversion tuner 5. Is used to control the frequency and phase of one of the (16) and (20). Preferably, a third local oscillator 20 of frequency synchronization type is used to easily ensure alignment between the second IF signal and the second SAW filter 18, and the second local oscillator 16 may be used. The frequency and phase of the oscillation signal generated by this are controlled. The second SAW filter 18 always contains traps for adjacent channel signal components, in which case it is important to properly align between the taps to maintain the second IF signal intact. Symbol clocking is done to provide high frequency stability. When the carrier of the final intermediate frequency (IF) is locked to a divisor of the multiple of the symbol clock frequency in frequency and phase, the AFPC which corrects the frequency and phase error in the carrier to be converted to the final intermediate frequency is always dynamic. It operates to correct symbol phase errors, thus eliminating the need for a separate phase tracker to correct dynamic symbol phase errors.

A digital multiplexer (hereinafter referred to as " AFPC selector 55 ") is shown as an AFPC selector 55 in FIG. 1, wherein the AFPC selector 55 includes a pilot carrier in a currently received DTV signal. In response to the pilot carrier presence detector 34, the imaginary output signal of the baseband response of the VSB synchine circuit 30 is selected as an input signal to the digital LPF 56. The response signal of the digital LPF 56 is a digital AFPC signal supplied as an input signal to the DAC 57. The output signal of the DAC 57 is an analog AFPC signal, which is again low-pass filtered in the analog LPF 58. The response signal of the analog LPF 58 is used to control the frequency and phase of the oscillation signal generated by the second local oscillator 16. Analog lowpass filtering is advantageous for realizing long time constant lowpass filtering because the need for active elements can be reduced compared to digital lowpass filtering. The pin-out of the integrated circuit can be provided at the interface between the integrated circuit of the multi-conversion tuner 5 and the integrated circuit including the digital synchro-dining circuit because the shunt capacitor of the resistive low pass filter can be provided. Analog lowpass filtering can be performed without the cost. However, since the response signal of the digital LPF 56 can be subsampled into the DAC 57 and the cost of the DAC 57 can be reduced by decreasing the speed required for digital / analog conversion. It is advantageous to perform digital low pass filtering of. This process is similar to the process used for the AGC circuit to be described later with reference to FIG. 12, and the DAC 57 can use the third clock signal generated for the AGC circuit. The clock signal can also be used to reset the accumulator included in the digital LPF 56 to average the samples of the filter input signal.

The AFPC selector 55 is a VSB paalot carrier presence detector indicating that a pilot carrier is not included in the currently received DTV signal to select an input signal to the digital LPF 56 from a circuit for processing a QAM DTV signal. Answer 34). 1 shows the product output signal of the digital multiplier 29 provided for the selection. The digital multiplier 29 multiplies the real and imaginary output signals of the QAM synchrodinning circuit 25 with each other to generate a digital AFPC signal in an unfiltered state. The generation of this unfiltered digital AFPC signal is very similar to that in the known Costas loop. In the Costas loop, the AFPC signal is used to control the frequency and phase of the digital local oscillation signal used to synchronize the received signals to the base. The configuration of FIG. 1 differs from the above process in that the AFPC signal is used to control the frequency and phase of the analog oscillation signal generated by the second local oscillator 16. In this configuration, the frequency and phase of the final IF signal supplied to the bandpass ADC 22 are adjusted for digitalization and for subsequent synchro- ning to the base station in the digital system. As in the case of the Costas loop case, the digital multiplier 29 preferably has a special configuration for converting a real signal into a ternary signal so that the imaginary signal can be multiplied, and thus the digital multiplier ( 29) can simplify the configuration and improve the pull-in characteristics of the AFPC loop.

The second IF amplifier 19, the third local oscillator 20 (except for its outboard crystal and other frequency selectors), and the third mixers 21 are advantageously incorporated into the monolithic integrated circuit. In this case, since the output signal of the third mixer 21 has a different frequency than the input signal to the second IF amplifier 19, the second IF amplifier 19 carries a high risk of undesired reproduction. High gains can be achieved without the problem. The first IF amplifier 14, the second local oscillator 16 (except its external board crystals and other frequency selection elements), and the second mixers 17 are also configured inside the same integrated circuit as described above or For example, it may be configured in another integrated circuit. Typically, the analog-to-digital converter (ADC) will be in the form of a flash with a resolution of at least 10 bits, and preferably can be configured inside a monolithic integrated circuit other than IF amplifiers. The analog lowpass filter connected to the input of the analog-to-digital converter (ADC) has a high gain second IF amplifier 19 positioned (and, in some cases, according to the associated switching transients) the sampling circuit. Is isolated from the integrated circuit (where the first IF amplifier 14 is located). This reduces the tendency for unwanted reproduction in the multi-conversion tuner 5. The large number of analog comparators included in the resistive ladder and flash-type ADCs used to set the quantization level requires significant die area, which often leads to monolithic integrated circuits and devices. Do not share

The elements 23 to 35 and the elements 55 and 56 are advantageously constructed inside a single monolithic integrated circuit so as to reduce the number of interconnections formed outside the monolithic integrated circuit. . The QAM and VSB synchro- dinning circuits 25 and 30 both receive input signals from the real / complex sample converter 24 and each address generator (i.e. first address) of the synchro- dinning circuits 25 and 30 is received. The generator 28 and the second address generator 32 may always be provided in the form of a shared circuit. It is advantageous that both the single monolithic integrated circuit and the circuits accompanying the integrated circuit include circuitry for automatically selecting an appropriate reception mode for the currently received DTV transmission signal. This configuration eliminates the need to operate the third local oscillator 20 at two significantly different frequencies depending on whether the DTV signal is in QAM or VSB form. Operating the third local oscillator 20 at two significantly different frequencies typically involves using two different crystals to set those frequencies. Regardless of whether the DTV signal is in QAM or VSB form, operating the third local oscillator at the same frequency can reduce the cost of additional crystals and the cost of electronic switching circuits resulting from the use of two crystals. In addition, the reliability of the multi-conversion tuner 5 is improved as the amount of circuitry located outside of the monolithic integrated circuit is reduced.

If the ADC is not configured entirely or almost entirely inside the integrated circuit, it is advantageous to include the ADC in an integrated circuit that includes circuits for separately synchronizing the QAM ADC signals and the VSB ADC signals, respectively, for a reason This is because signals for clocking the sampling of the final IF signal by the ADC must be generated in the integrated circuit. In addition, the analog low pass filter connected to the input of the converter insulates the sampling circuit from the integrated circuit (s) where high gain IF amplification is performed in accordance with an associated switching transient.

3 specifically illustrates a digital circuit for synchronizing QAM DTV signals to a base, that is, a QAM synchrodining circuit 25. The QAM synchro-dinning circuit 25 includes a QAM in-phase synchronous detector 250 for generating a real part of the output signal of the circuit 25 and an output signal of the QAM synchro- dinning circuit 25. It includes a QAM quadrature phase synchronization detector 255 for generating an imaginary part of. The QAM synchronous dining circuit 25 also includes a digital adder 256, a digital subtractor 257, and first to fourth digital multipliers 251 to 254. The QAM in-phase synchronous detector 250 is a product of the multipliers 251 and 252 and the multipliers 251 and 252 to generate a real part of the output signal of the QAM synchro-dining circuit 25. And an adder 256 for adding the output signals. The first digital multiplier 251 reads the QAM carrier read from the cosine QAM complex carrier lookup table 271 in the QAM complex carrier ROM 27 to real digital samples of the final IF signal supplied from the real / complex sample converter 24. Multiplying the digital samples representing the cosine of, and the second digital multiplier 252 complexes the sine QAM complex in the QAM complex carrier ROM 27 to the imaginary digital samples of the final IF signal supplied from the real / complex sample converter 24. Digital samples representing the sine of the QAM carrier read from the carrier lookup table 271 are multiplied. The QAM quadrature phase synchronous detector 255 is a product of the multipliers 253 and 254 and the multipliers 253 and 254 to generate an imaginary part of the output signal of the QAM synchro-dining circuit 25. And a subtractor 257 for subtracting output signals. The third digital multiplier 253 reads the QAM carrier read from the sine QAM complex carrier lookup table 271 in the QAM complex carrier ROM 27 to real digital samples of the final IF signal supplied from the real / complex sample converter 24. Multiplying the digital samples representing the sine of, the fourth digital multiplier 254 complexes the cosine QAM in the QAM complex carrier ROM 27 to the imaginary digital samples of the final IF signal supplied from the real / complex sample converter 24. The digital samples representing the cosine of the QAM carrier read from the carrier lookup table 271 are multiplied.

3 also specifically illustrates a digital circuit for synchronizing VSB DTV signals on a basis, that is, VSB synchro-dining circuit 30. The VSB synchronization circuit 30 includes a VSB in-phase synchronous detector 300 for generating a real part of an output signal of the circuit 30, and a VSB for generating an imaginary part of an output signal of the circuit 30. A quadrature phase synchronization detector 305 is included. The VSB synchronous dining circuit 30 also includes a digital adder 306, a digital subtractor 307, and first through fourth digital multipliers 301 through 304. The VSB in-phase synchronous detector 300 multiplies the multipliers 301 and 302 with their multipliers 301 and 302 to generate a real part of the output signal of the VSB synchro-dining circuit 30. And an adder 306 for adding output signals. The first digital multiplier 301 reads the VSB carrier read from the cosine VSB complex carrier lookup table 311 in the VSB complex carrier ROM 31 to the real digital samples of the final IF signal supplied from the real / complex sample converter 24. Multiplying the digital samples representing the cosine of, and the second digital multiplier 302 complexes the sine VSB in the VSB complex carrier ROM 31 to the imaginary digital samples of the final IF signal supplied from the real / complex sample converter 24. The digital samples representing the sine of the VSB carrier read from the carrier lookup table 312 are multiplied. The VSB quadrature phase synchronous detector 305 is a product of the multipliers 303 and 304 and the multipliers 303 and 304 to generate an imaginary part of an output signal of the VSB synchrodin circuit 30. And a subtractor 307 for subtracting the output signals. The third digital multiplier 303 reads the VSB carrier read from the sine VSB complex carrier lookup table 312 in the VSB complex carrier ROM 31 to the real digital samples of the final IF signal supplied from the real / complex sample converter 24. Multiplying the digital samples representing the sine of, and the fourth digital multiplier 304 complexes the cosine VSB in the VSB complex carrier ROM 31 to the imaginary digital samples of the final IF signal supplied from the real / complex sample converter 24. Digital samples representing the cosine of the VSB carrier read from the carrier lookup table 311 are multiplied.

4 illustrates a representative configuration of the sample clock generator 23 in detail. That is, the sample clock generator 23 includes a voltage controlled oscillator 230 (hereinafter referred to as "21.5 MHz VCO 230") that generates a seesaw oscillation signal having a nominal frequency of 21.52 MHz. The 21.5 MHz VCO 230 is a controlled oscillator in which the frequency and phase of the generated oscillation signal are controlled by an automatic frequency and phase control (AFPC) signal voltage. The AFPC signal voltage is an automatic frequency and phase control (AFPC) that compares the divided response signal for the oscillation signal of the 21.5 MHz VCO 230 with a 10.76 MHz reference carrier supplied from a digital / analog converter (DAC) 232. Generated by the detector 231. Preferably, the 21.5 MHz VCO 230 is configured in the form of using a crystal to stabilize the natural frequency and phase of its oscillation signal. A symmetrical clipper (or limiter) 233 generates a response signal that is essentially square in response to the seesawed oscillation signal, which signals the timing of the sampling of the final IF signal within the bandpass ADC 22. It is used as the first clock signal for matching. The divided flip-flop 234 responds to the transition of the first clock signal in a predetermined manner to generate another square wave having a fundamental frequency of 10.76 MHz, which is 1/2 of the frequency of the oscillation signal of the 21.5 MHz VCO 230. Let's go. A frequency response signal for the oscillation signal of the 21.5 MHz VCO 230 is supplied to the AFPC detector 231 for comparison with a 10.76 MHz reference carrier supplied from the DAC 232. The divided flip-flop 234 also supplies a square wave output signal having a fundamental frequency of 10.76 MHz to the AND circuit 235 so that the square wave signal is used by the 2: 1 decimator 35 shown in FIG. AND operation with the first clock signal to generate two clock signals.

A reference carrier of 21.52 MHz supplied from the DAC 232 is a signal component having a frequency corresponding to a low frequency of a symbol frequency (or baud frequency), and then extracts a component of a received DTV signal synchronized with a base. It is generated by multiplying the harmonics of the symbol frequency by a suitable multiplier in the multiplication circuit. As evidenced by Kenneth J. Bures's paper, "Understanding Timing Recovery and Jitter in Digital Transmission Systems-Part 1" published in October 1992 by RF Design, Restoring the symbol timing information from a predetermined form of symbol code without narrowing is performed by narrowband filtering processing which uses the harmonics of the complementary frequency as the center frequency, and then the harmonics from which the complementary frequency can be extracted by frequency selective filtering. There was a perception that this could be done by performing squaring or other nonlinear processes that would generate. Narrowband filters used for lower symbol code rates include LC filters and phase-locked loops (PLLs). SAW filters are suitable for use with higher symbol code rates. What is particular about the symbol recovery process in the sample clock generator 23 shown in Figs. 4 and 5 is that the method for recovering symbol timing information, which is generally known, has a predetermined divisor of the symbol frequency of the digitized symbol code stream. It is transformed for use in a digital system using a finite impulse responsive digital bandpass filter with elements clocked by the sample clock generator itself to select. Conventionally, the modified method described above has been expected to have no guarantee of feasibility because it is difficult to evaluate the effect of the digital sampling process when the sampling rate itself is controlled by the result of the method.

However, the frequencies used to generate the AFPC error signal are within the band of bandpass FIR digital filters centered on the divisor of the oscillation frequency of the 21.5 MHz VCO 230, so that the AFPC loop of the 21.5 MHz VCO 230 If the frequency and phase can be fixed, the above modification method can be implemented. In practice, this variant is advantageous in that the bandpass FIR digital filters act as a tracking filter clocked by the sample clock generator. In the state where the frequency and phase of the 21.5 MHz VCO 230 are fixed, there is no phase difference effect caused by symbol rate harmonics and harmonics that do not exactly match the center frequencies of the bandpass filters. Hereinafter, the modified method will be described in detail with the assumption that the received DTV signal is a VSB signal having a symbol frequency of 10.76 MHz, and after that the reception DTV signal is a QAM signal having a symbol frequency of 5.38 MHz. .

The 5.38 MHz reference signal selector 236 responds to a VSB pilot carrier presence detector 34 that detects a pilot carrier that is included in the received DTV signal and indicates that the received DTV signal is a VSB signal. 236 may select real samples of the DTV signal supplied from VSB in-phase synchronous detector 300 according to the response signal for the detection of the pilot carrier. These selected real samples are bandpass FIR digital filters 237 (hereinafter " 5.38 MHz digital BPFs 237 " that provide a selection response signal having a center frequency of 5.38 MHz for selecting the first harmonic of symbol frequency from the VSB signal. ) "). The response signal of the 5.38 MHz digital BPF 237 is squared by a square circuit 238, and the square circuit 238 is a second harmonic of 5.38 MHz and includes a strong 10.76 MHz component of the response signal of the filter 237. Generate harmonics. A digital signal representing a reference carrier analog output signal of 10.76 MHz by the second harmonic by a band FIR digital filter 239 (hereinafter referred to as 10.76 MHz digital BPF 239) providing a selective response signal having a center frequency of 10.76 MHz. It is selected such that it can be applied to the DAC 232 as an input signal.

The 5.38 MHz reference signal selector 236 also generates a response signal when the VSB pilot carrier presence detector 34 is not included in the received DTV signal to detect a pilot carrier indicating that the received DTV signal is a QAM signal. The output signal of the square circuit 23A to be applied to the 5.38 MHz digital BPF 237 which provides a selection response signal having a center frequency of 5.38 MHz is selected. A filter comprising a strong 5.38 MHz component by a band FIR digital filter 23B providing a selection response signal having a center frequency of 2.69 MHz to select a 2.69 MHz first order harmonic of the symbol frequency of the baseband QAM signal ( The input signal is supplied to a square circuit 23A for generating harmonics of the response signal of 23B) (hereinafter referred to as " 2.69MHz digital BPF 23B "). This baseband QAM signal may be supplied from the QAM in-phase sync detector 250 or from the QAM quadrature sync detector 255 as shown in FIG.

4, a square circuit 238 is shown as a digital multiplier that receives the response signal of a 5.38 MHz digital BPF 237 as both a multiplier and a multiplier, and the square circuit 23A is also 2.69 MHz as both a multiplier and a multiplier. It is shown as a digital multiplier that receives the response signal of the digital BPF 23B. Each of the square circuits 238, 23A can be configured as a digital multiplier using logic gates, but is comprised of a ROM that stores a square lookup table for higher operating speeds. In connection with generating harmonics of the response signal of the preceding filter, it is possible to use an absolute value circuit instead of the square circuit, but in this case it is not preferable because weak second harmonics are generated.

4 also shows a cosine QAM complex carrier lookup table 271 and a sinusoidal QAM of a QAM complex carrier ROM 27 that provide complex digital representation signals for two phases of a QAM carrier that are converted to the final intermediate frequency and have quadrature with each other. A representative configuration of the first address generator 28 for supplying an address signal to the complex carrier lookup table 272 is shown in detail. The transition of the first clock signal is counted by the first address counter 281 provided in the first address generator 28 to generate the second basic address signal. The first basic address signal is applied to the digital adder 282 as a first summand. The digital adder 282 is also supplied with a first address correction signal as a second operand and added to the first basic address signal, thereby signing the cosine QAM complex carrier lookup table 271 and the sign of the QAM complex carrier ROM 27. A corrected first address signal for addressing all of the QAM complex carrier lookup table portion 272 is generated as the sum output signal. Rotate the symbol clock for a sequence of real samples of the QAM signal base synchro- nized by the QAM in-phase sync detector 250 and the imaginary samples of the QAM signal synchro- lated by the QAM quadrature sync detector 255 The detector 283 is adapted to respond, wherein the symbol clock rotation detector 283 is performed at the receiver in accordance with the first clock signal as evidenced by the received QAM signal hetered to the final intermediate frequency which is a divisor of the symbol frequency. Detect phase misphasing between symbol clocking and symbol clocking performed at the transmitter. Various forms of such symbol clock rotation detectors 283 are known, which are incorporated herein by way of example and dated May 19, 1992. D. US Pat. No. 5,115,454 to A. D. Kucar, entitled " METHOD AND APPARATUS FOR CARRIER SYNCHRONIZATION AND DATA DETECTION. &Quot; The phase misalignment of the symbol clocking done at the receiver and detected by the symbol clock rotation detector 283 is averaged by the digital low pass filter 284 using a large number of samples (e.g., millions), thereby providing the first base address. The first address correction signal supplied to the adder 282 is generated to correct the signal. As above, averaging over a large number of samples accumulates a small number of samples, and then dumps the accumulated samples forward at a reduced sample rate for continued sample accumulation, and accumulates and subsamples the sub-sample. sampling) can be performed by a process of repeating a few times while gradually decreasing the sussampling rate.

4 also shows a cosine VSB complex carrier lookup table 311 and a sine VSB of a VSB complex carrier ROM 31 that provide complex digital representation signals for two phases of a VSB carrier that are converted to a final intermediate frequency and have a quadrature relationship with each other. A representative configuration of the second address generator 32 for supplying an address signal to the complex carrier lookup table 312 is shown in detail. The transition of the first clock signal is counted by the second address counter 321 provided in the second address generator 32 to generate the second basic address signal. The second basic address signal is applied to the digital adder 322 as a first singer. The digital adder 322 is also applied with a second address correction signal as a second operand and added to the second basic address signal, thereby signing a cosine VSB complex carrier lookup table 311 and a sign of the VSB complex carrier ROM 31. A corrected second address signal for addressing all of the VSB complex carrier lookup tables 312 is generated as the sum output signal.

4 also shows a clocked digital delay line 323 for delaying a predetermined number of sample periods prior to applying samples from in-phase sync detector 300 as input signals to quantizer 324. . The quantizer 324 supplies as an input signal the quantization level that is closest to the sample he has currently received. Quantization levels can be estimated from the energy of the pilot carrier with the VSB signal or from the envelope detection result of the VSB signal. The nearest quantization level selected by the quantizer 324 as its output signal is subtracted by the digital adder / subtracter 325 to the input signal of the quantizer 324. The adder / subtractor 325 includes a clocked latch at an output terminal to operate as a clocked device. The difference output signal of the adder / subtracter 325 indicates the departure of the symbol levels actually recovered from the symbol levels that must be recovered, but the symbol phase mismatch or delay preceded by the polarity of the depreciation Whether due to a phase mismatch remains to be resolved.

Samples from in-phase synchronous detector 300 applied as an input signal to clocked digital delay line 323 are applied as input signals to mean square error (MSE) gradient detection filter 326 without delay. The MSE gradient detection filter 326 is a finite impulse response (FIR) type digital filter having (-1/2), 1, 0, (-1), and (+1/2) kernels. The operation is configured to be clocked. The number of sample periods provided by the clocked digital delay line 323 is such that the response signal of the MSE gradient detection filter 326 is temporarily aligned with the difference signal from the adder / subtracter 325. To this end, the difference signal from the adder / subtracter 325 is multiplied by the response signal of the MSE gradient detection filter 326 by the digital multiplier 327. Only the sign bit of the response signal of the MSE gradient detection filter 326, which is the two's complement filter, and the most significant bit thereafter, can be multiplied, thereby simplifying the configuration of the digital multiplier 327. Samples of the product signal output from the digital multiplier 327 are samples representing phase misalignment of the symbol clocking performed at the receiver, and the phase misalignment of the symbol clocking is supplied to the adder 322 to correct the second base address. The sample averaging for generating the second address correction signal is averaged using a number of samples (eg, millions) by the digital LPF 328.

The symbol synchronization representations used in the second address generator 32 shown in FIG. U. H. SUH Qureshi is identical to the general description of the use of pulse amplitude modulation (PAM) signals in his article "Timing Recovery for Equalized Partial-Response Systems," published in December 1976, IEEE Transactions on Communications, pages 1326-1330. . These symbol synchronization techniques used in conjunction with symbol synchronization of VSB signals are described in particular in the inventors' prior applications cited herein. In the general form of the second address generator 32 shown in FIGS. 4 and 5, the clocked digital delay line 323 does not exist as a separate element, but instead is temporarily aligned with the MSE gradient detection filter 326. The input signal input to the quantizer 324 is delayed by a predetermined number of sample periods from the difference signal from the adder / subtracter 325 generated from the tap-type digital delay line embedded in the MSE gradient detection filter 326. do. The tap-type digital delay line is executed by the (-1/2), 1, 0, (-1), and (+1/2) kernels described above before being summed to generate a response signal of the MSE gradient detection filter 326. Supply differential delayed samples to be weighted.

The carrier of the QAM DTV signal and the carrier of the VSB DTV signal are converted to the final intermediate frequencies, which differ by 2.69 MHz, respectively, because the carrier of the QAM DTV signal is located in the center of a TV channel with a bandwidth of 6 MHz, while the VSB This is because the carrier of the DTV signal has a frequency that is only 310 kHz higher than the lowest frequency of the TV channel having a bandwidth of 6 MHz. The frequencies of the first, second, and third local oscillators 11, 16, and 20 in the multi-conversion tuner 5 of FIG. 1 represent the residual and full sidebands of the QAM DTV signal. The converted intermediate frequency of the VSB DTV signal carrier may be higher than the converted intermediate frequency of the QAM DTV signal carrier while being higher and lower than the carrier of the QAM DTV signal. In another embodiment, the intermediate frequency of the VSB DTV signal carrier is converted to the intermediate frequency of the QAM DTV signal carrier while the residual side band and the full side band of the QAM DTV signal are respectively lower and higher than the carrier of the QAM DTV signal. The frequencies of the first, second and third local oscillators 11, 16 and 20 may be selected to be lower.

The lowest frequency of the final IF signal is greater than or equal to 1 MHz so as to keep the ratio of the highest frequency to the lowest frequency of the final IF signal less than about 8: 1 to mitigate the filtering requirements for the real / complex sample converter 24. It is preferable. To satisfy this preference for the QAM signal alone, the final carrier frequency for the QAM carrier of the final IF signal is 3.69 MHz. Also, in order to satisfy the above selection for the VSB signal alone, the final carrier frequency for the VSB carrier of the final IF signal is 1.31 when it is assumed that the frequency of the entire sideband of the VSB signal must be higher than the frequency of the residual sideband. MHz, and assuming that the frequency of the front side band of the VSB signal should be lower than that of the residual side band, it is 6.38 MHz. Assuming that the frequency of the front side band of the VSB signal should be higher than the frequency of the remaining side band, the carrier frequency of the QAM carrier is at least 4.00 MHz because the carrier frequency of the VSB signal carrier is at least 1.31 MHz. Assuming that the frequency of the front side band of the VSB signal should be lower than the frequency of the residual side band, the carrier frequency of the QAM carrier is at least 3.69 MHz because the carrier frequency of the VSB signal carrier is at least 6.38 MHz.

If the sample rate at the bandpass ADC 22 is set to a sample rate corresponding to 21.52 * 10 ⁶ samples per second by the first clock signal from the sample clock generator 23, the conversion intermediate for the carrier of the QAM DTV signal is The frequency is preferably not higher than 5.38 MHz, in which case the intermediate frequency can be sampled at least four times per cycle. If it is assumed that the frequency of the front sideband of a VSB signal must be higher than the frequency of its residual sideband, then this choice ensures that the lowest frequency of the final IF signal is not higher than 2.38 MHz and that the carrier of the VSB signal is not higher than 2.69 MHz. There is a restriction. 11 illustrates how the VSB carrier is limited to the frequency of 1.31 to 2.69 MHz and how the QAM carrier is limited to the frequency of 4.00 to 5.38 MHz because of the conditions described above.

Assuming that the frequency of the front side band of the VSB signal should be lower than the frequency of the residual side band, the carrier of the VSB signal is limited to the frequency of 3.69 to 5.38 MHz. Therefore, the carrier of the VSB signal is limited to a frequency of 6.38 to 8.07 MHz so that an offset of 2.69 MHz can be maintained between carriers. 12 illustrates a case where the QAM carrier is limited to the frequency range of 3.69 to 5.38 MHz and the VSB carrier is limited to the frequency range of 6.38 to 8.07 MHz.

In order to be able to describe the QAM carrier continuously based on the sine-cosine QAM complex carrier lookup table (272,271) of the QAM complex carrier ROM 27, the final intermediate frequency converted from the QAM carrier must be a multiple of 21.52 MHz. do. On the other hand, in order to be able to continuously describe the VSB carrier based on the sine-cosine VSB complex carrier lookup tables 312 and 311 of the VSB complex carrier ROM 31, the final intermediate frequency converted from the VSB carrier is 21.52 * 10 per second. ^It must be a divisor of multiples of sample rate corresponding to six samples. The final intermediate frequency converted from the carrier and corresponding to (m / n) times of 21.52 MHz has a small n value so that the number of values in the sine-cosine lookup tables stored in the ROM can be kept moderately small. (The variables "m" and "n" mentioned herein are not related to the variables "M" and "N" mentioned in the [Technical Problems to Invent] section of the present specification.)

Intermediate frequencies which conform to the above concept as intermediate frequencies to be converted from the carrier of the QAM DTV signal and the carrier of the VSB DTV signal, respectively, can be found according to the procedure described in US Pat. No. 5,506,636. For the frequency ranges in question, a harmonic table of consecutive harmonics is constructed at the 10.76 MHz VSB symbol rate, which is related to the sampling clock rate in the harmonic plane. Subsequently, the low harmonic pairs of the same harmonics representing the required 2.69 MHz frequency difference are regarded as carriers in terms of their proper advantages.

The harmonics of 21.52 MHz harmonics, the third and seventh harmonics of 5.38 MHz and 2.39 MHz, show an approximately 2.69 MHz offset, which is why the QAM carrier and VSB cause the frequency of the front side band to be higher than the frequency of the residual side band. It is suitable for use as a carrier wave. The 2.69 MHz offset between these low harmonics is 10,762237.762 per second, unlike the 2,690,122.4 Hz offset between the QAM carrier and the VSB carrier that is required to offset the VSB carrier by 59.75 times the nominal NTSC horizontal scan frequency from the cochannel NTSC video carrier. 1/4 of the symbol rate corresponding to the sample, ie 2,690,559.4 Hz. This small 437 Hz frequency mismatch is easily adjusted by the automatic frequency and phase control of the controlled second local oscillator 16 provided in the multiple conversion tuner 5 of FIG. When QAM and VSB carriers are converted to approximate third and seventh harmonics for the 21.52 MHz harmonics in the final IF signals, the addressing of the QAM and VSB complex carrier ROMs 27 and 31 can be greatly simplified. This is because there is an advantage that repetitive symmetry is performed between the stored sine and cosine functions, which can reduce the number of bits of the address signals applied to the ROMs 27 and 31.

The second harmonic of the 21.52 MHz sampling frequency is 43.05 MHz, from which it can find a pair of harmonics that are offset by approximately 2.69 MHz from each other. The seventh and fifteenth harmonics of 43.05 MHz harmonics are the third and seventh harmonics of the 21.52 MHz harmonics described above. The ninth and 26th harmonics of 4.305 MHz and 1.594 MHz, as the lower harmonics of 43.05 MHz harmonics, show an error of 20 kHz or 0.74% for the required 2.69 MHz offset, and may act as QAM carriers and VSB carriers, respectively. . This error is within 30 kHz, which is within the mistuning range allowed by conventional commercial design schemes involving NTSC TV receivers. However, the VSB complex carrier ROM31, which stores the sine / cosine VSB complex carrier lookup tables 312,311 for the 26th order harmonics of 43.05 MHz harmonics, must store an excessive number of samples, and the ninth order of 43.05 MHz harmonics. The QAM complex carrier ROM 27, which stores the sine / cosine QAM complex carrier lookup tables 272 and 271 for low harmonics, must also store an appropriate number of samples.

The third harmonic of the 21.52 MHz sampling frequency is 64.57 MHz, whose harmonics can be found by looking for harmonics that are offset by approximately 2.69 MHz from the lower harmonics of 43.05 MHz or another of the 64.57 MHz harmonics. The 12th harmonics of 4.967 MHz as the lower harmonics of 64.57 MHz and the 18th harmonics of 2.265 MHz as the lower harmonics of 43.05 MHz, resulting in 12 kHz or 0.45% error for the required 2.69 MHz offset, respectively. It may act as a QAM carrier and a VSB carrier where the frequency of the sidebands is higher than the frequency of the residual sidebands. The error is within 30 kHz, which is within the mistuning range allowed in conventional commercial design schemes involving NTSC TV receivers. However, the QAM complex carrier ROM 27, which stores sine / cosine QAM complex carrier lookup tables (272,271) for the 12th order harmonics of 64.57 MHz harmonics, must store an excessive number of samples, and the 18th order of 43.05 MHz harmonics. The VSB complex carrier ROM 31, which stores the sine / cosine VSB complex carrier lookup tables 312,311 for low harmonics, must also store an appropriate number of samples.

The seventh harmonic of the 64.57 MHz harmonic has a frequency of 8.07 MHz, offset almost exactly as required by 2.69 MHz from the third harmonic of the 21.52 MHz harmonic. The low harmonics of 21.52 MHz and the third harmonics of 5.38 MHz, and the low harmonics of 64.57 MHz and the seventh harmonics of 8.07 MHz, respectively, are QAM carriers and VSBs whose frequencies are lower than the residual sidebands. It is suitable for use as a carrier.

The frequencies of the first, second, and third local oscillators 11, 16, and 20 in the multi-conversion tuner 5 of FIG. 1 are converted from the carrier of the VSB DTV signal to the QAM DTV signal. It is desirable to select 5.38 MHz corresponding to the estimated symbol rate and corresponding to 1/2 of the reference symbol rate for the VSB DTV signal. Therefore, when the frequency conversion is performed such that the frequency of the front side band of the VSB carrier is higher than the frequency of the residual side band in the final IF signal, the frequency of the QAM carrier in the final IF signal is preferably 2.69 MHz. In another embodiment, when the VSB carrier is frequency-converted such that the frequency of its front side band is lower than the residual side band frequency in the final IF signal, the frequency of the QAM carrier in the final IF signal is preferably 8.07 MHz. Do.

In addition, all harmonics of 43.05 MHz harmonics and all harmonics of 64.57 MHz harmonics become harmonics of 129.15 MHz harmonics, the third harmonic of 43.05 MHz harmonics and the second harmonic of 64.57 MHz harmonics. The frequencies 2.69 MHz, 5.68 MHz, and 8.07 MHz are 47th, 23rd, and 15th harmonics of 129.15MHz harmonics, respectively. Also, although the harmonic relationship between carriers is considered in relation to the harmonics of 21.52 MHz sampling rate, which is the second harmonic of 10.76 MHz VSB symbol rate, this consideration is also possible in relation to even harmonics of 10.76 MHz symbol rate. In addition, for a more complete consideration of possible high frequency relationships between carriers, consideration can be given to the odd harmonics of the 10.76 MHz VSB symbol rate, that is, at least the third harmonic. The 2.69 MHz, 5.68 MHz, and 8.07 MHz frequencies are 11th, 5th, and 3rd harmonics of 32.29MHz harmonics, which are three times the 10.76MHz symbol rate of the QAM signal.

Those skilled in the art related to analog-to-digital conversion circuits for digital systems will recognize that sampling of analog signals for digitization can be performed using various sampling window widths. In the above description, it is assumed that the sample rate corresponding to 21.52 * 10 ⁶ samples per second is adopted so that the duration of each sampling window is 1/2 of the 21.52 MHz period. The pulses output from the symmetrical clipper (or limiter) 233 can be extended up to almost twice the period if necessary. Another possible embodiment is that the analog / digital conversion circuitry can use two staggered sets of sampling windows each extended by one half of a 21.52 MHz period and corresponds to 43.05 * 10 ⁶ samples per second. Designing such that the digitization can be performed by staggering phases at a combined sample rate. Automatic phase and frequency control accuracy is improved by digitizing the final IF signal at a sample rate of 43.05 * 10 ⁶ samples per second.

FIG. 5 shows a variant of the circuit of FIG. 4 where the third and seventh harmonics of 21.52 MHz harmonics are used as the final intermediate frequencies converted from QAM and VSBMHz carriers, respectively. In the case of the second address generator 320 of FIG. 5, which is a modification of the second address generator 32 of FIG. 4, when the sampling rate corresponds to 21.52 * 10 ⁶ samples per second, the modulus 8 is counted to determine the QAM complex carrier. A second address counter 321 for generating two addressing cycles for the ROM 27 and one addressing cycle for the VSB complex carrier ROM 310 used in place of the VSB complex carrier ROM 31. . The least significant bits of the count value output from the second address counter 321 are used to replace the first base address output from the first address counter 281.

In the case of the first address generator 280 of FIG. 5, which is a modification of the first address generator 28 of FIG. 4, the first address counter 281 of FIG. 4 is omitted, and the first address counter 281 is omitted. The least significant bits of the second address counter 321 are applied to the adder 282 as the first base address instead of the count value from the " The VSB complex carrier ROM 310, which is substituted for the VSB complex carrier ROM 31, has a cosine VSB complex carrier lookup table 313 that stores only half a cycle of cosine values of the VSB carrier, and only the sine values of the VSB carrier. A sinusoidal VSB complex carrier lookup table 314 that stores only half a cycle is included. The cosine and sine VSB complex carrier lookup tables 313, 314 of VSB complex carrier ROM 310 are addressed by the least significant bits of the sum output signal of adder 322. The most significant bit of the sum output signal of the adder 322 is the bit of the VSB carrier cosine values read from the cosine VSB complex carrier lookup table 313 of the VSB complex carrier ROM 310 by a selection bit complementor 315. An exclusive logic sum is performed with each to generate a first addee for the digital adder 317, the most significant bit of the sum output signal of the adder 322 being of importance so as to generate a second addee input to the adder 317. A zero extension is made in the increasing direction of. The sum output from adder 317 provides eight QAM carrier cosine values for eight first clock periods to determine the complete cycle of the VSB carrier. The most significant bit of the sum output signal of the adder 322 is also the bit of the VSB carrier sine values read from the sine VSB complex carrier lookup table 314 of the VSB complex carrier ROM 310 by the selection bit complementer 316. And an exclusive OR are performed to generate a first addee for the digital adder 318, and the most significant bit of the sum output signal of the adder 322 is of importance to generate a second addee input to the adder 318. The zero addition is made in the increasing direction of. The sum output from adder 318 provides eight QAM carrier sine values for eight first clock periods to determine the full cycle of the VSB carrier.

The circuit of FIG. 5 or the circuit of FIG. 4 can also be used when the fifth and third harmonics of 32.29 MHz harmonics are used as the final intermediate frequencies converted from the QAM, VSBMHz carriers, respectively. In this case, of course, the contents of the cosine and sinusoidal VSB complex carrier lookup tables 313 and 314 of the VSB complex carrier ROM 310 are modified for a higher frequency 8.07 MHz VSB carrier.

The skilled person in the field of digital circuit design simplifies other hardware configurations by using a ROM that takes advantage of the symmetry of the cosine function and the sine function or the 90 ° offset to the phases of the two functions. It will be appreciated that this can be achieved. In addition, those skilled in the field of digital circuit design and who understand the above description, 10.76MHz selected by the digital BPF 237 to output an oscillation signal output from the 21.5MHz VCO 230 and converted into a square wave by the symmetrical clipper 233. It will be appreciated that the circuit of FIGS. 4 and 5 can be modified with an AFPC detector for the 21.5 MHz VCO 230 that compares in frequency with the response signal of the frequency multiplier for the signal.

In addition, if the person skilled in the digital circuit design field, referring to the above description, the bandpass ADC 22 can configure a circuit that samples at a sample rate corresponding to 43.05 * 10 ⁶ samples per second during the digitization process. There will be. The 21.5 MHz VCO 230 is replaced with a VCO that supplies an oscillation signal of 43.05 MHz, and is, for example, output from the VCO 230, converted into a square wave by the symmetric clipper 233, and divided by the flip-flop 234. The oscillation signal is compared in frequency with a response signal of frequency double for the 10.76 MHz signal selected by the digital BPF 237. The 2: 1 decimator 35 can be replaced with a 4: 1 decimator, and the square wave output signal from the flip-flop 234 is the basis for generating a reduced sample clock signal for the 4: 1 decimator. It can be divided by a factor of 2 by another flip-flop to provide.

6 shows a configuration that the real / complex sample converter 24 can adopt, in which case the real / complex sample converter 24 has the following configuration, i.e.

(a) Linear phase, finite impulse response (FIR) type digital filter 60 (hereinafter referred to as "Hilbert transform FIR") that generates imaginary (Im) digital samples as a Hilbert transform response to real (Re) digital samples. Filter 60 ", and

(b) the real digital sample, which may be provided by clocked latch elements 61 to 66 embedded in the Hilbert transform FIR filter 60 to compensate for the delay time of the Hilbert transform FIR filter 60; Compensation, clocked digital delay.

D., "IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS", Vol. AES-18, No. 4 (Nov. 1982), pp. 736-739. W. Rice and K. H. K.H. Wu's article, "Quadrature Sampling with High Dynamic Range," describes the use of the circuitry described above for performing in-phase and quadrature sampling processes. Since the 6 MHz wide band of the final IF signal has a minimum frequency of at least 1 MHz or so, there are only seven non-zero weighted taps used in the FIR filter 60 used for the Hilbert transform. It is possible to use.

As such, the Hilbert transform FIR filter 60 having seven taps is one-sample delay element 61, 62, 63, 64 that weights and sums samples taken to generate a Hilbert transform response signal. , Cascade connection of 65, 66. The Hilbert transform has a linear phase characteristic, so that the tap weights of the Hilbert transform FIR filter 60 exhibit symmetry with respect to the median delay. Therefore, the input signal to the delay element 61 to be commonly weighted and the output signal from the delay element 66 are summed by the digital adder 67, and the output signal from the delay element 61 to be commonly weighted. And the output signal from the delay element 65 are summed by the digital adder 68, and the output signal from the delay element 62 and the output signal from the delay element 64 to be commonly weighted are added to the digital adder 68. Are summed by The output signal from the delay element 64 is applied to the ROM 70 as an input address, and the ROM 70 multiplies the signal by an appropriate weight of W ₀ magnitude. The sum output signal from the digital adder 69 is applied to the ROM 71 as an input address, and the ROM 71 multiplies the signal by an appropriate weight of W ₁ magnitude. The sum output signal from the digital adder 68 is applied to the ROM 72 as an input address, and the ROM 72 multiplies the signal by an appropriate weight of W ₂ magnitude. The sum output signal from the digital adder 67 is applied to the ROM 73 as an input address, and the ROM 73 multiplies the signal by an appropriate weight of W ₃ magnitude. As ROMs 70, 71, 72, and 73 are used as multiplicand fixed multipliers, the delay associated with the multiplication can be made negligibly short. The output signals of the ROMs 70, 71, 72, and 73 are weighted W ₀ , W ₁ , W stored in the ROM 70, 71, 72, 73. _2, are combined by the tree structure of the code-type digital adders 74, 75, 76, operating as an adder or subtractor to appropriately add a code to W _3. Adders 67, 68, 69, 74, 75, and 76 each represent a delay for one sample, resulting in six samples in a FIR filter 60 having seven taps. It is assumed as clocked adders that result in a delay for. The delay of the input signal of the filter 60, which compensates for this delay, is cascaded by six one-sample delay elements 61, 62, 63, 64, 65, and 66. Is provided. The input address for the ROM 70 is taken from the output of the delay element 64, not from the output of the delay element 63, and thus adders 67, 68 by the one-sample delay of the delay element 64. ), The one-sample delays of 69 are compensated for.

See, "IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS", Vol. AES-20, No. 6 (Nov. 1984), pp. 821-824. M. C.M. Rader's paper, "A Simple Method for Sampling In-Phase and Quadrature Components," describes an improvement on complex synchronous detection performed on digitized bandpass signals. Rader is a constant π for bandpass signals designed and digitized on the basis of Jacobian elliptic functions instead of the Hilbert transform FIR filter and the delay compensation FIR filters of Rice and Wu. A pair of all-pass digital filters showing a phase response difference of / 2 is used. A suitable configuration of such full band pass digital filters, which are configured in an infinite impulse response (IIR) type, has the following system function.

H ₁ (z) = z ^-1 (z ^-2 -a ² ) / (1-a ² z ^-2 ) a ² = 0.5846832

H ₂ (z) =-(z ^-2 -b ² ) / (1-b ² z ^-2 ) b ² = 0.1380 250

Rader describes a filter configuration that requires only two multiplications, one "a ² " and the other "b ² ".

Fig. 7 shows another form of real / complex sample converter 24, in which Mr. M. A pair of all-pass digital filters 80, 90 (hereinafter referred to as " H1 filter 80, H2 filter 90 " described by CM Rader and having a form designed based on Jacobian elliptic function. "," Are included. The H1 and H2 filters 80 and 90 exhibit a constant π / 2 phase response difference for the digitized bandpass signals. Because oversampling real samples when synchronizing VSB signals can result in better symbol synchronization, the present inventors use the full bandwidth of the radar to use subsampling to provide further reduction in delay network. Do not use pass filters.

Structure of H1 filter 80 providing system function H ₁ (z) = z ^-1 (z ^-2 -a ² ) / (1-a ² z ^-2 ), where a ² = 0.5846832 in decimal operation 7 is shown in FIG. 7, and the operation is performed as follows. That is, the samples output from the bandpass ADC 22 are applied to the node 89 after being delayed by one ADC sample clock period of the clocked delay element 88. The signal applied to the node 89 is delayed by 2 ADC sample clock periods from the clocked delay elements 81 and 82 cascaded again, and then applied to the digital adder 83 as the first subject signal. The sum output signal of the adder 83 becomes a real response signal output from the H1 filter 80. The sum output signal of the adder 83 is also delayed by 2 ADC sample clock periods in the cascaded clock type delay elements 84 and 85, and then receives the signal of the node 89 as a subtractive input signal. Applied to 86 as a susceptible input signal. The resulting difference output signal of the digital subtractor 86 is supplied as a multiplication input signal to a digital multiplier 87 which multiplies the a ² multiplier signal by using a binary operation. The resulting product output signal is applied to the digital adder 83 as a second singular signal.

The structure of the H2 filter 90 which provides the system function H ₂ (z) =-(z ^-2 -b ² ) / (1-b ² z ^-2 ) (where b ² = 0.1380250 in decimal operation) is shown in FIG. It is shown in Figure 7, the operation is made as follows. That is, the samples output from the bandpass ADC 22 are delayed by 2 ADC sample clock periods from the cascaded clock type delay elements 91 and 22, and then applied to the digital adder 93 as a first addee signal. . The sum output signal of the adder 93 becomes an imaginary response signal output from the H2 filter 90. The sum output signal of the adder 93 is also delayed by 2 ADC sample clock periods in the cascaded clocked delay elements 94 and 95, and then applied to the digital subtractor 96 as a subtracted input signal. The digital subtractor 96 receives samples from the bandpass ADC 22 as a subtractive input signal. The resulting difference output signal of the digital subtractor 96 is supplied as a multiplication input signal to the digital multiplier 97 which multiplies the b ² multiplier signal by using a binary operation. The resulting product output signal is applied to the digital adder 93 as a second singular signal.

FIG. 8 shows a complex signal filter obtained by modifying the real / complex sample converter 24 (also referred to as " complex signal filter " in the description of FIGS. 8, 9 and 10) of FIG. That is, the position of the clock type delay element 88 is shifted so as not to delay the digital output signal of the band pass ADC 22 but instead to delay the sum output signal of the adder 83, and the band pass ADC 22 is delayed. Is applied without delay to the node 89, so that a real response signal is provided to the output port of the position shifted clock-type delay element 88. The real response signal provided to the output port of the position shifted clock type delay element 81 is the same as the response signal provided to the output port of the clock type delay element 84. Thus, the real response signal is provided from the output port of the clocked delay element 84, rather than from the output port of the position shifted clock type delay element 81, and thus the position shifted clocked delay element 81. Is no longer needed.

9 illustrates a complex signal filter obtained by modifying the complex signal filter of FIG. 8 as follows. That is, the first subsumed signal for the adder 83 is taken from the cascaded clocked delay elements 91 and 92 without taking the cascaded clocked delay elements 81 and 82 from each other. Thus, the cascaded clocked delay elements 81 and 82 are no longer needed. The complex signal filter of FIG. 9 is preferable to the complex signal filters of FIGS. 7 and 8 in that redundant clock type delay elements are omitted.

Fig. 10 is a detailed block diagram of a complex signal filter for generating a constant? / 2 phase difference between a real response signal Re and an imaginary response signal Im for digitized band pass signals, which is named "QUADRATURE DEMODULATOR". Tee, announced 27 November 1991. F. s. It is similar to the complex signal filter described in UK Patent Application No. 2 244 410 A of T.F.S.Ng. The filter of the engine Ng is not an radar IIR filter but a FIR filter. The complex signal filter of FIG. 10 differs from that of the engine Ng in that 2: 1 decimation is performed after filtering rather than before filtering.

The filter allows real and imaginary filtering to be supported by the shared tapped delay line. As shown in FIG. 10, the shared tapped delay line is cascaded single-clock delay element 100 such as latches clocked at a rate corresponding to four times the symbol transmission rate, such as the bandpass ADC 22. ) To (114). For certain designs, the single-clock delay element 100 may be omitted or included in the bandpass ADC 22. It is assumed that the digital adders and the digital subtractors included in the complex filter of FIG. 6 are each clocked at a rate corresponding to four times the symbol transmission rate with a delay of a single clock period. Digital multipliers are assumed to be wired place shifts or are provided from ROM for multiplication by an integral power of two, so the delay of each multiplication is as long as clocked operation is involved. It becomes zero. It is assumed that the resolution of the resultant signal in the engine Ng filter is at least 8 bits.

In order to generate a real response signal H ₁ (z), the real response filter has tap weights W ₀ = 4, W ₁ = 0, W ₂ = -12, and W ₃ =-for each example described by the engine Ng. Assume 72, W ₄ = 72, W ₅ = 12, W ₆ = 0, and W ₇ = -4. The real response filter includes a digital subtractor 121 for subtracting the response signal of the delay element 114 from the response signal of the delay element 100, in addition to the single-clock delay elements 100 to 114, and a subtractor thereof. A digital multiplier 122 for weighting the differential response signal of 121 by a factor of 4, a digital subtractor 125 for subtracting the response signal of the delay element 103 from the response signal of the delay element 109, and a subtractor thereof. A digital multiplier 126 for weighting the differential response signal of 125 with a factor of 12, a digital subtractor 127 for subtracting the response signal of the delay element 105 from the response signal of the delay element 107, and A digital multiplier 128 for weighting the differential response signal of the subtractor 127 by a factor of 72, a digital adder 129 for summing product signals of the digital multipliers 126, 128, The product signal of the digital multiplier 122 A digital adder 130 for summing up the sum output signal and a 2: 1 decimator 131 for generating a real filter response signal Re in the decimated response signal for the sum output signal from the adder 130. ).

The subtractor 121 subtracts the response signal of the delay element 113 from the output signal of the bandpass ADC 22 to introduce a single-clock period delay to compensate for the delay of the adder 129 instead of the delay element 100. The response signal of the delay element 114 is subtracted from the response signal of. Since W ₁ = 0 and W ₆ = 0, the digital subtractor 123 or the differential response signal of the digital subtractor 123 for subtracting the response signal of the delay element 111 from the response signal of the delay element 101 is weighted. There is no digital multiplier 124 to be summed. As a result, there is no digital adder for summing the product output value from multiplier 124 and the product output value from multiplier 122. As a result, there is a need to compensate for the delay of the adder 129.

In order to generate an imaginary response signal H ₁ (z), the imaginary response filter has a tap weight corrected from the example described by the engine Ng W ₈ = 8, W ₉ = 14, W ₁₀ = 22, W ₁₁ = Assume that 96, W ₁₂ = 22, W ₁₃ = 14, and W ₁₄ = 8 are applied. The imaginary response filter includes, in addition to the single-clock delay elements 100 to 112, a digital adder 141 for adding the response signal of the delay element 112 to the response signal of the delay element 100, and an adder ( A digital multiplier 142 for weighting the sum response signal of 121 with a factor of 8, a digital adder 143 for adding the response signal of the delay element 110 to the response signal of the delay element 102, and the adder A digital multiplier 144 for weighting the sum response signal of 143 by a factor of 14, a digital adder 145 for adding the response signal of the delay element 108 to the response signal of the delay element 104, and A digital multiplier 146 for weighting the sum response signal of the adder 145 with a factor of 22, a digital multiplier 147 for weighting the response signal of the delay element 107 with a factor of 96, and the digital multiplier 142. A digital adder 148 for summing product signals of 144 A digital adder 149 for summing product signals of the hair multipliers 146, 147, a digital adder 150 for summing sum output signals from the adders 148, 149, and And a 2: 1 decimator 151 for generating an imaginary filter response signal Im in the decimated response signal for the sum output signal from the adder 150.

The digital multiplier 147 delays instead of weighting the response signal of the delay element 106 to introduce a single-clock period delay to compensate for the single-clock period delay of each of the adders 141, 143, and 145. The response signal of the element 107 is weighted by a factor of 96.

In another embodiment of the invention, although slightly less preferred, the trellis decoded output signals from the two-dimensional symbol decoding circuit 37 and the one-dimensional symbol decoding circuit 38 are respectively supplied to the data deinterleaver, It may also delay the selection of the data source until data de-interleaving is complete. Also, although slightly less preferred, as another embodiment of the present invention, the trellised output signal of the two-dimensional symbol decoding circuit 37 is deinterleaved by a data deinterleaver and then by a Reed-Solomon decoder. Decode to generate a first stream of error-corrected data, de-interleave the trellised output signal of the one-dimensional symbol decoding circuit 38 by the data deinterleaver and then decode by the Reed-Solomon decoder And generating a second stream of error-corrected data so as to select a data source between the first and second error correction data streams. As a variant of these embodiments, the first and second error correction data streams may be supplied to separate data de-randomizers before the selection of the data source is made. As another variant, separate Reed-Solomon decoders can be used for the QAM signal and the VSB signal, but in this case one data deinterleaver is used for both the QAM signal and the VSB signal, or for both the first and second error correction data. One data derandomizer can be used for this purpose.

In the embodiments of the present invention, the bandpass ADC 22 is configured to sample at a sample rate of 43.05 * 10 ⁶ samples per second, rather than at a sample rate of 21.52 * 10 ⁶ samples per second during digitization. The: 1 decimator 35 is replaced with a 4: 1 decimator. This change, of course, requires appropriate modifications to the sample clock generator 23. When the synchronization circuit 25 or 30 synchronizes a DTV signal having a carrier frequency higher than 5.38 MHz as a base, a sample rate higher than a sample rate corresponding to 21.52 * 10 ⁶ samples per second is used. The situation occurs when the synchro-dining circuit 30 needs to synchronize the baseband of the QAM signal whose frequency of the remaining side band is greater than that of the front side band. Decimators that decimate the baseband signal with a factor greater than 2 do not pre-filter the baseband signal with a pre-fliter, but rather than simply design samples. It is good practice to design samples to subtract the response from the pre-filter.

In the above-described preferred embodiments of the present invention, a digital QAM synchro-dining circuit and a VSB synchro-dining circuit are used. In preferred embodiments of the present invention, the digital processing performed on the final IF signals rather than on the baseband signals reduces the number of analog / digital conversion processes that must be performed and is used in the QAM synchro- dinning circuit. This completely eliminates the problems associated with tracking the conversion characteristics of two analog / digital converters.

However, in another embodiment of the present invention, the process of synchronizing the QAM signal to the base is performed using in-phase and quadrature analog synchronous detectors. In this case, at the rear end of the in-phase and quadrature analog synchronous detectors, the response signal from the in-phase analog synchronous detector is digitized to generate a real sample stream of the interleaved QAM sample code, and the imaginary samples of the interleaved QAM sample code. An analog / digital conversion circuit is provided for digitizing the response signal from the quadrature analog synchronous detector to generate a stream.

In another embodiment of the present invention, which is adopted from the DTV receiver type used for field testing during the development of the ATSC standard, the process of synchronizing the VSB signal based on the analog signal is performed using an analog synchronous detector. In this case, an analog-to-digital converter (ADC) is provided at the rear end of the analog synchronous detector to digitize the response signal from the analog synchronous detector to generate a sample stream of interleaved VSB symbol code. The tracker is installed. For these embodiments, the decimation filter takes the input signal directly from the response signal of the baseband phase tracker.

In the above-described preferred embodiments of the present invention, a digital synchro-processing process is used to achieve "wrap-around" of symbol phase adjustment. The symbol phase adjustment is performed during baseband conversion, so that when the ROMs storing the digital carriers are properly addressed, the symbol phase adjustment is made in a closed adjustment range cycle rather than in an open linear adjustment range cycle. If there is only an open linear adjustment range for the symbol phase, which is valid only at the baseband, the symbol phase phasing will jump in the form of time displacement upon reaching the limit of the adjustment range. This time jump will cause repetition of symbols in the symbol coding stream or symbol loss in the symbol coding stream depending on whether the time shift jump is in the reverse direction or in the forward direction. This effect undesirably interferes with the symbol counting operation in the data line where time shift jumps occur, resulting in temporary data synchronization loss.

Currently, television technicians are studying the use of digital transmission systems for HDTV to transmit a variety of television signals of different types, for example four television signals having a resolution similar to that of modern NTSC signals and transmitted simultaneously. . The invention is suitable for use in receivers for such alternative transmission methods, and therefore the appended claims should be construed broadly enough to encompass receivers as described above.

In the description of the claims, the word "above" is used to refer to the elements set forth above.

Claims (36)

In a digital television signal receiver, Selecting a receiving channel, converting a digital television (DTV) signal to intermediate frequencies for filtering and amplifying on the selected channel, and synchronizing the final intermediate frequency output signal in analog form generated by the filtering and amplifying as a basis A wireless receiver for generating a baseband signal by An analog-to-digital converter (ADC) embedded in the wireless receiver, for sampling one of the signals to be supplied from the wireless receiver as a first digital sample stream representing the baseband signal; Instruct the ADC to have a sample rate that is substantially equal to a predetermined multiple of MN times the symbol rate of the DTV signal, where MN is a product of a positive integer M greater than 1 and a positive integer N greater than or equal to two. A sample clock generator for supplying a sample clock signal for timing sampling by Receiving the first digital sample stream and responsively regenerating only every Nth digital samples of the first digital sample stream at a sample rate corresponding to 1 / N of the sample rate of the first digital sample stream. An N: 1 decimator that generates 2 digital sample streams, A channel equalizer for performing channel equalization on the second digital sample stream to generate a channel equalization response signal; And a symbol decoding circuit for decoding the symbols in the channel equalization response signal while performing correction for a symbol phase error to recover the bit groups corresponding to the decoded symbols. The method of claim 1, wherein the sample clock generator An oscillator for supplying an oscillation signal at a frequency controlled by an automatic frequency and a phase control signal; Circuitry for generating said sample clock signal at a rate responsive to said oscillation frequency; A finite impulse response (FIR) filter for supplying a band response signal for the first digital sample stream with its center frequency at low harmonics of the symbol rate of the DTV signal; A frequency multiplier for generating harmonics of the symbol rate of the DTV signal by multiplying a frequency of one component of the band response signal from the low harmonics of the symbol rate of the DTV signal; And an automatic frequency and phase control detector for detecting the frequency and phase error between the sampling rate of the ADC and the harmonics of the symbol rate of the DTV signal as the automatic frequency and phase control signal to be applied to the oscillator. TV signal receiver. 3. A digital television signal receiver as claimed in claim 2, wherein N is two. 3. A digital television signal receiver as claimed in claim 2, wherein said M is 1 and said N is 2. A digital television signal receiver as claimed in claim 1, wherein said N is two. The digital television signal receiver as claimed in claim 1, wherein M is 1 and N is 2. The method of claim 1, A data synchronization recovery circuit for detecting data synchronization information extracted from the first digital sample stream; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. 8. The digital television signal according to claim 7, wherein the data synchronization recovery circuit is configured to detect data synchronization in response to the bit groups restored by decoding the symbols of the channel equalizer in the symbol decoding circuit. receiving set. 8. The digital television signal receiver as claimed in claim 7, wherein the data synchronization restoring circuit is configured to use a matching filter for detecting data synchronization in response to the second digital sample stream. 10. The digital television signal receiver as claimed in claim 9, wherein said data synchronization recovery circuit is connected to receive said second digital sample stream subjected to channel equalization by said channel equalizer. The method of claim 1, wherein the ADC is connected to sample the final intermediate frequency output signal in analog form, and the synchronization of the final intermediate frequency output signal in analog form to a baseband is performed by QAM digital television signals. A digital television signal receiver comprising a digital synchro-dining device for use. The method of claim 11, A data synchronization restoring circuit for decoding data symbols in response to the recovered bit groups by decoding the symbols of the channel equalizer in the symbol decoding circuit; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. The method of claim 11, A data synchronization restoring circuit using a matching filter for detecting data synchronization in response to the second digital sample stream; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring a randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. The digital television signal receiver as claimed in claim 13, wherein said data synchronization restoring circuit is connected to receive said second digital sample stream subjected to channel equalization by said channel equalizer. The method of claim 11, wherein the sample clock generator An oscillator for supplying an oscillation signal at a frequency controlled by an automatic frequency and a phase control signal; Circuitry for generating said sample clock signal at a rate responsive to said oscillation frequency; A FIR filter for supplying a band response signal for the first digital sample stream with its center frequency at a low harmonic of the symbol rate of the DTV signal; A frequency multiplier for generating harmonics of the symbol rate of the DTV signal by multiplying a frequency of one component of the band response signal from the low harmonics of the symbol rate of the DTV signal; And an automatic frequency and phase control detector for detecting a frequency and phase error between the sampling rate of the ADC and the harmonics of the symbol rate of the DTV signal as the automatic frequency and phase control signal to be applied to the oscillator. TV signal receiver. The method of claim 15, A data synchronization restoring circuit for decoding data symbols in response to the recovered bit groups by decoding the symbols of the channel equalizer in the symbol decoding circuit; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. The method of claim 15, A data synchronization restoring circuit using a matching filter for detecting data synchronization in response to the second digital sample stream; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. 18. The digital television signal receiver as claimed in claim 17, wherein said data synchronization restoring circuit is connected to receive said second digital sample stream subjected to channel equalization by said channel equalizer. The method of claim 1, wherein the ADC is connected to sample the final intermediate frequency output signal in analog form, and the synchronization of the final intermediate frequency output signal in analog form to a baseband is performed by QAM digital television signals. A digital television signal receiver comprising a digital synchro-dining device for use. The method of claim 19, A data synchronization recovery circuit for decoding data symbols in response to the recovered bit groups by decoding the symbols of the channel equalizer in the symbol decoding circuit; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. The method of claim 19, A data synchronization recovery circuit using a matched filter to detect data synchronization in response to the second digital sample stream; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. 22. The digital television signal receiver as claimed in claim 21, wherein said data synchronization restoring circuit is connected to receive said second digital sample stream subjected to channel equalization by said channel equalizer. The method of claim 19, wherein the sample clock generator An oscillator for supplying an oscillation signal at a frequency controlled by an automatic frequency and a phase control signal; Circuitry for generating said sample clock signal at a rate responsive to said oscillation frequency; A FIR filter for supplying a band response signal for the first digital sample stream with its center frequency at a low harmonic of the symbol rate of the DTV signal; A frequency multiplier for generating harmonics of the symbol rate of the DTV signal by multiplying a frequency of one component of the band response signal from the low harmonics of the symbol rate of the DTV signal; And an automatic frequency and phase control detector for detecting the frequency and phase error between the sampling rate of the ADC and the harmonics of the symbol rate of the DTV signal as the automatic frequency and phase control signal to be applied to the oscillator. TV signal receiver. The method of claim 23, wherein A data synchronization restoring circuit for decoding data symbols in response to the recovered bit groups by decoding the symbols of the channel equalizer in the symbol decoding circuit; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. The method of claim 23, wherein A data synchronization restoring circuit using a matching filter for detecting data synchronization in response to the second digital sample stream; A deinterleaver for the bit groups; A Reed-Solomon decoder for receiving the response signal of the deinterleaver as an input signal; And a derandomizer for restoring the randomized signal prior to being transmitted to the DTV receiver in response to a result signal from the Reed-Solomon decoder. 27. The digital television signal receiver as claimed in claim 25, wherein said data synchronization restoring circuit is connected to receive said second digital sample stream subjected to channel equalization by said channel equalizer. A digital television receiver for recovering baseband digital samples of a symbol code from a digital television (DTV) signal, An analog / digital converter for sampling the DTV signal according to a first sample clock signal; A sample clock generator for generating the first sample clock signal, The sample clock generator A controlled oscillator for supplying an oscillation signal, A circuit for supplying the first sample clock signal in a state in which timing is set by the oscillation signal; A center frequency is set at a frequency corresponding to low harmonics of the symbol rate of the symbol code having substantial intensity, and includes the low harmonics of the symbol rate of the symbol code as a response signal to the symbol code baseband digital samples. A narrow band, finite impulse response (FIR) type first digital filter connected to supply the first digital filter response signal, A frequency multiplier for supplying a frequency multiplier response signal including a multiple of the low harmonics of the symbol rate of the symbol code in response to the first digital filter response signal; An automatic frequency and phase control (AFPC) signal for the controlled oscillator in response to a signal derived from a multiple of the low harmonic of the symbol rate of the symbol code included in the frequency multiplier response signal and an oscillation signal of the controlled oscillator. Digital television signal receiver comprising an automatic frequency and phase control circuit for generating. The oscillator of claim 27, wherein the controlled oscillator is configured to supply a sisoidal oscillation signal at a frequency corresponding to twice the symbol frequency. The circuit for supplying the first sample clock signal in timing with the oscillation signal may generate the essentially square wave of the frequency corresponding to twice the symbol frequency as the first sample clock signal. And a clipper circuit for symmetrically clipping the oscillating oscillation signal. 29. The apparatus of claim 28, wherein the sample clock generator further comprises a flip-flop connected as a divider for generating a square wave of the symbol frequency in response to the essentially square wave of the frequency corresponding to twice the symbol frequency. And the signal derived from the oscillation signal of the controlled oscillator and to which the automatic frequency and phase control circuit responds corresponds to a square wave of the symbol frequency. The method of claim 29, A 2: 1 decimator for supplying an output signal having a number of samples corresponding to one half of the baseband digital samples in response to the baseband digital samples of the symbol code from the DTV signal; A channel equalization filter responsive to the output signal from the 2: 1 decimator, Built in the sample clock generator, for the square wave of the frequency corresponding to twice the symbol frequency from the clipper circuit and for the square wave of the symbol frequency from the flip-flop from the 2: 1 decimator And an AND gate for generating an AND response signal to be supplied as a second sample clock frequency to the 2: 1 decimator to match the timing of the samples in the output signal of the digital television signal receiver. 31. The apparatus of claim 30, wherein the frequency multiplier A first square operation circuit for performing a square operation on the response signal of the first digital filter to generate a squared first digital filter response signal including second harmonics of components of the first digital filter response signal; And a narrowband finite impulse response type second digital filter having a center frequency at a frequency corresponding to a symbol rate of the symbol code, and connected to filter the squared first digital filter response signal. Digital television signal receiver characterized by. 32. The apparatus of claim 31, wherein the second digital filter response signal is applied to the automatic frequency and phase control circuit as the multiple of the low harmonic of the symbol rate of the symbol code in the response signal of the frequency multiplier. Digital television signal receiver. 32. The apparatus of claim 31, wherein the frequency multiplier A second square operation circuit for generating a second-order squared digital filter response signal including quadratic harmonics of components of the second digital filter response signal by performing a square operation on the response signal of the second digital filter; The center frequency is set at a frequency corresponding to twice the symbol rate of the symbol code, and the square-operated second digital filter response signal is filtered to determine the symbol rate of the symbol code in the response signal of the frequency multiplier. And a narrowband infinite impulse response-type third digital filter connected to supply a third digital filter applied to the automatic frequency and phase control circuit as the multiple of the low frequency. Signal receiver. 28. The apparatus of claim 27, wherein the frequency multiplier A first square operation circuit for performing a square operation on the response signal of the first digital filter to generate a squared first digital filter response signal including second harmonics of components of the first digital filter response signal; And a narrowband finite impulse response type second digital filter having a center frequency at a frequency corresponding to a symbol rate of the symbol code, and connected to filter the squared first digital filter response signal. Digital television signal receiver characterized by. 35. The apparatus of claim 34, wherein the second digital filter response signal is applied to the automatic frequency and phase control circuit as the multiple of the low harmonic of the symbol rate of the symbol code in the response signal of the frequency multiplier. Digital television signal receiver. 35. The apparatus of claim 34, wherein the frequency multiplier A second square operation circuit for generating a second-order squared digital filter response signal including quadratic harmonics of components of the second digital filter response signal by performing a square operation on the response signal of the second digital filter; The center frequency is set at a frequency corresponding to twice the symbol rate of the symbol code, and the square-operated second digital filter response signal is filtered to determine the symbol rate of the symbol code in the response signal of the frequency multiplier. And a narrowband infinite impulse response-type third digital filter connected to supply a third digital filter applied to the automatic frequency and phase control circuit as the multiple of the low frequency. Signal receiver.