KR100262413B1 - Automatic mode detection circuit of liquid display element - Google Patents

Abstract

PURPOSE: An automatic mode detection circuit of a liquid crystal display is provided to select one mode out of DE only or DE/SYNC modes automatically by detecting the input of vertical synchronous signal. CONSTITUTION: The device includes a clock signal generator(10), a vertical synchronous signal detector(20), a select signal generator(30) and a mode selector(40). The clock signal generator receives a main clock signal and generates a clock signal used for detecting the vertical synchronous signal. The vertical synchronous signal detector detects whether the vertical synchronous signal is input or not and generates a detect signal at every input of a predetermined number of clock signals from the clock signal generator. The select signal generator receives the detect signal from the vertical synchronous signal detector and generates a mode select signal. The mode selector receives the mode select signal from the select signal generator and selects one mode out of the DE only or DE/SYNC mode.

Description

Automatic Mode Detection Circuit of LCD

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic mode detection circuit of a liquid crystal display device, and more particularly, to an automatic mode detection circuit for detecting the presence of a vertical synchronization signal applied to a liquid crystal module and selecting a mode corresponding thereto.

Currently, only notebook signal manufacturers enable the DE signal, which is the data enable signal, to the liquid crystal module, or the data enable signal DE + SYNC signal including the synchronization signal to the liquid crystal module.

In the related art, there is an inconvenience of manually selecting a mode of a liquid crystal module using a jumper from the outside according to the mode of an input signal applied from a PC. In addition, since the controller does not operate even if the mode is manually changed by using a jumper from the outside, there is a problem that the circuit must be corrected in this case.

Therefore, in order to respond to a PC manufacturer applying different types of signals to the liquid crystal module as a controller, a function for selecting a mode according to an input signal must be added to the controller.

The present invention is to solve the problems of the prior art as described above, the automatic mode detection circuit of the liquid crystal display device which can automatically select one of the DE only mode or DE / SYNC mode by detecting the presence of the vertical synchronization signal input The purpose is to provide.

1 is a block diagram of an automatic mode detection circuit of a liquid crystal display device according to an embodiment of the present invention;

2 is a detailed circuit diagram of an automatic mode detection circuit of a liquid crystal display device according to an embodiment of the present invention;

3A and 3B are views for explaining a DE / SYNC mode and a DE only mode,

(Explanation of symbols for the main parts of the drawing)

10: clock signal generator 20: vertical synchronous signal detector

30: mode selection signal generator 40: mode selection unit

50: internal signal generator 11, 31, 33: D flip-flop

21, 32, 34: Inverter 22: Counter

41, 42: Multiplexer

In order to achieve the above object of the present invention, the present invention is a main clock signal in the automatic mode selection circuit for detecting the presence or absence of the vertical synchronization signal input to the liquid crystal display element to select the DE / SYNC mode or DE only mode A clock signal generator configured to input a clock signal to generate a clock signal for detecting the vertical synchronization signal; A vertical synchronous signal detector for detecting whether a vertical synchronous signal is input and generating a detection signal each time a predetermined number of clock signals are applied from the clock signal generator; A selection signal generator for inputting a detection signal output from the vertical synchronization signal detector to generate a mode selection signal; It is characterized by providing an automatic mode detection circuit of a liquid crystal display device including a mode selection unit for inputting a mode selection signal generated from the selection signal generator to select one of a DE / SYNC mode signal or a DE only mode signal.

According to an exemplary embodiment of the present invention, the clock signal generator is applied with an initial reset signal to a clear terminal, and provides an input signal applied to an input terminal to the vertical synchronous signal detector at a rising edge of the main clock signal applied as a clock signal. It is characterized by consisting of the first flip-flop.

According to an embodiment of the present invention, the vertical synchronous signal detector comprises: a first inverter for inputting and inverting a vertical synchronous signal; The clock signal loaded by the vertical synchronization signal inverted through the first inverter and output from the clock signal generator is counted. When a predetermined clock signal is applied from the clock signal generator, the vertical synchronization signal is present. And a counter for generating a detection signal indicating.

According to an embodiment of the present invention, the mode selection signal generator outputs an output signal of the vertical synchronous signal detector applied to an input terminal at a rising edge of the main clock signal cleared by the initial reset signal and applied as a clock signal. A second flip flop; A second inverter for inverting the output of the second flip-flop; A third flip-flop that is cleared by the initial reset signal, the output signal of the second inverter is applied as a clock signal, and a high power supply voltage is applied to an input terminal; And a third inverter for inverting the output signal of the third flip-flop to generate a mode selection signal.

According to an embodiment of the present invention, the mode selector comprises: a first multiplexer for selecting one of a horizontal synchronization signal and a data enable signal according to a mode select signal generated from the mode select signal generator; And a second multiplexer for selecting one of the vertical synchronization signal and the data enable signal according to the mode selection signal applied from the mode selection signal generator.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an automatic mode detection circuit of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a detailed circuit diagram of FIG. 1.

1 and 2, the automatic mode detection circuit of the present invention inputs a main clock signal MCLK to generate a clock signal for detecting a vertical synchronization signal, and a clock signal generator 10 and a vertical synchronization signal. A vertical synchronous signal detection unit 20 for detecting the presence or absence of a VSYNC and generating a detection signal indicating the detection of a vertical synchronous signal whenever a predetermined number of clock signals are applied from the clock signal generation unit 10; A mode selection signal generator 30 for inputting a pulse signal applied from the vertical synchronization signal detector 20 to generate a mode selection signal DE_S for selecting one of the DE only mode and the DE / SYNC mode, and the mode And a mode selector 40 for selecting one of the DE only mode signal and the DE / SYNC mode signal according to the mode selection signal DE_S generated from the selection signal generator 30 to provide the signal to the internal signal generator 50. do.

The clock signal generator 10 is cleared by the initial reset signal FRST, and outputs the signal RCO2 applied to the input terminal at the rising edge of the main clock signal MCLK, that is, the vertical synchronous signal detector 20) a D flip-flop 11 for generating a clock signal for detecting the presence of the vertical synchronization signal.

The vertical synchronous signal detection unit 20 is an inverter 21 for inverting the vertical synchronous signal VSYNC and a vertical synchronous signal cleared by the initial reset signal FRST and inverted through the inverter 21. It consists of a 4-bit binary counter 22 which is loaded at the positive edge of VSYNC and inputs the output signal of the clock signal generator 10 as a clock signal CLK, thereby providing a predetermined number from the clock signal generator 10. For example, whenever 16 clock signals are applied, a detection signal DCT indicating whether or not a vertical synchronization signal is input is generated.

The selection signal generator 30 outputs a detection signal DCT applied to the input terminal D at the rising edge of the main clock signal MCLK, which is cleared by the initial reset signal FRST and applied as a clock signal. The D flip-flop 31, the inverter 32 for inverting the output of the D flip-flop 31, and the inverter 32 cleared by the initial reset signal FRST and applied as a clock signal. D flip-flop 33 to which a high power supply voltage VCC is applied to the input terminal D, and the output signal of the D flip-flop 33 are inverted, and the mode selection signal DE_S It consists of an inverter 34 for generating a).

The mode selector 40 selects one of the horizontal synchronization signal HSYNC and the data enable signal DTMG according to the mode select signal DE_S generated by the mode select signal generator 30 to generate an internal signal generator. And one of the vertical synchronization signal VSYNC and the data enable signal DTMG in accordance with the multiplexer 41 for providing to 50 and the mode selection signal DE_S applied from the mode selection signal generator 30. And a multiplexer 41 for selecting and providing the signal to the internal signal generator.

The operation of the automatic mode detection circuit of the present invention having the above configuration will be described with reference to the waveform diagram of FIG.

The DE only mode refers to a mode in which the liquid crystal module can be operated using only the data enable signal because a blank section is recognized as a vertical synchronization signal in the data enable signal (DEMG) itself. The DE / SYNC mode is a data enable signal. Since there is no blank section for recognizing the vertical synchronization signal in the DTMG, both the data enable signal and the vertical synchronization signal are required to drive the liquid crystal module.

In the present invention, as described above, when the vertical synchronization signal VSYNC is detected by detecting the input of the vertical synchronization signal, the device recognizes the DE / SYNC mode and the vertical synchronization signal HSYNC and the vertical synchronization signal as shown in FIG. 3A. (VSYNC) is selected and provided to the internal signal generator 50 inside the liquid crystal module.

On the other hand, when the vertical synchronization signal (VSYNC) is not applied to recognize the DE only mode, and selects the DTMG signal as shown in Figure 3b to provide to the internal signal generator 50.

The operation of selecting one of the DE / VSYNC mode signal and the DE only mode signal by detecting the presence of the vertical synchronization signal will be described.

The clock signal generator 10 divides the input signal RCO2 by resetting the D flip-flop 11 by the initial reset signal FRST and then using the main clock signal MCLK as the clock signal. At this time, the input signal RCO2 has a period of 270ns.

The output Q of the D flip-flop 11 of the clock signal generator 10 is applied as the clock signal CLK of the counter 22 of the vertical synchronous signal detector 20. At this time, since the vertical synchronization signal VSYNC inverted through the inverter 21 is applied to the load terminal LOAD of the counter 22, the counter 22 has the vertical synchronization signal VSYNC as shown in FIG. 3A. Will only operate during the 20 μs low period.

Accordingly, when the vertical synchronization signal VSYNC is input, the counter 22 performs a counting operation because a high state signal is applied to the load terminal LOAD through the inverter 21 during the low state period as shown in FIG. 3A. . Accordingly, the counter 22 divides the RCO2 signal applied from the clock signal generator 10 that is loaded and applied to the clock terminal into 16 divisions.

Therefore, the counter 22 outputs, as the detection signal DCT, the output signal RCO in the low state indicating the detection of the vertical synchronization signal every time the RCO2 signal is applied as the clock signal, for example, every 16th period. That is, since the period of the RCO2 signal is 270 ns, and the counter 22 divides the RCO2 signal by 16, the counter 22 uses the output signal RCO in the low state as the detection signal DCC every 270 ns x 16 = 17.7 μs. Will print.

When the vertical synchronizing signal is applied as described above, a signal (DCT) indicating the detection of the vertical synchronizing signal is generated from the vertical synchronizing signal detecting unit 20 at every predetermined time and applied to the mode selection signal generating unit 30.

In the mode selection signal generator 30, an output signal DCT generated from the vertical synchronization signal detector 20 is applied to an input terminal D of the D flip-flop 31. Accordingly, the D flip-flop 31 outputs the output signal of the vertical synchronization signal detector 20 applied to the input terminal D to the inverter 32 at the rising edge of the main clock signal MCLK.

Since the inverter 32 inverts the output of the flip-flop 31 to the high state and applies it to the clock terminal of the flip-flop 33, the flip-flop 33 outputs a signal of the high state to the inverter 34. . Accordingly, the inverter 34 generates the mode selection signal DE_S in the low state.

When the mode select signal DE_S in the low state is generated from the mode select signal generator 30, the mode selector 40 selects the DE / SYNC mode signal. That is, the internal signal generator 50 selects HSYNC and VSYNC as shown in FIG. 3A among the signals applied to the multiplexers 41 and 42 according to the mode selection signal DE_S in the low state generated from the selection signal generator 30. To provide.

The internal signal generator 50 inputs VSYNC and HSYNC selected and applied from the mode selector 40 to generate various signals required to drive the liquid crystal module.

Meanwhile, when the vertical synchronization signal VSYNC is not input, as shown in FIG. 3A, the vertical synchronization signal VSYNC does not have a low state section but only a high state section.

Accordingly, since the output of the inverter 21 becomes low and is applied to the load terminal LOAD of the counter 22, the counter 22 counts the output signal of the clock signal generator 10 applied to the clock terminal. You will not be able to.

Accordingly, the counter 22 outputs the high state output signal RCO to the mode selection signal generation unit 30, and the D flip-flop 31 of the mode selection signal generation unit 30 receives the high state signal ( DCT).

Since the output of the inverter 32, which inputs the output of the flip-flop 31, becomes low and is applied to the clock terminal of the flip-flop 33, the output of the flip-flop 33 goes low. The inverter 34 outputs the mode select signal DE_S in the high state to the mode selector 40.

The mode selector 40 selects the DE only mode signal by the multiplexers 41 and 42, respectively, by the mode select signal DE_S of the high state generated from the select signal generator 30. That is, the multiplexers 41 and 42 select the data enable signal DTMG among the input signals by the mode selection signal DE_S in the high state and provide the data enable signal DTMG to the internal signal generator 50.

The internal signal generator 50 inputs a data enable signal DTMG applied to the mode selector 40 to generate a signal for driving the liquid crystal module.

According to the present invention as described above, the present invention can detect whether the vertical synchronization signal input or not, and automatically selects either the DE only mode or the DE / SYNC mode according to the detection result.

Therefore, it is simple to select a mode simply without having to change the mode by using a jumper manually.

In addition, there is an advantage that it is possible to correspond with one controller for different modes.

In addition, since the vertical synchronization signal detection unit 20 divides the RCO2 signal applied from the D flip-flop 11 to the clock terminal of the counter 22 by 16, and outputs the vertical synchronization signal detection signal in a low state, Since the vertical synchronization signal of 17.7 μs or less is filtered, the operation mode can be selected by detecting the vertical synchronization signal accurately regardless of noise.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (5)

In the automatic mode selection circuit for detecting the presence of the vertical synchronization signal input to the liquid crystal display element to select the DE / SYNC mode or DE only mode, A clock signal generator for inputting a main clock signal to generate a clock signal for detecting a vertical synchronization signal; A vertical synchronous signal detector for detecting whether a vertical synchronous signal is input and generating a detection signal each time a predetermined number of clock signals are applied from the clock signal generator; A selection signal generator for inputting a detection signal output from the vertical synchronization signal detector to generate a mode selection signal; And a mode selection unit for inputting a mode selection signal generated from the selection signal generator to select one of a DE / SYNC mode signal and a DE only mode signal. The method of claim 1, wherein the clock signal generation unit An initial reset signal applied to a clear terminal, and a first flip-flop configured to provide an input signal applied to an input terminal to the vertical synchronous signal detector at a rising edge of the main clock signal applied as a clock signal; Automatic mode detection circuit of the device. The method of claim 1, wherein the vertical synchronization signal detector A first inverter for inputting and inverting the vertical synchronization signal; The clock signal loaded by the vertical synchronization signal inverted through the first inverter and output from the clock signal generator is counted. When a predetermined clock signal is applied from the clock signal generator, the vertical synchronization signal is present. An automatic mode detection circuit for a liquid crystal display device, characterized by comprising a counter for generating a detection signal indicating. The method of claim 1, wherein the mode selection signal generation unit A second flip-flop that outputs an output signal of the vertical synchronous signal detector applied to an input terminal at a rising edge of the main clock signal cleared by the initial reset signal and applied as a clock signal; A second inverter for inverting the output of the second flip-flop; A third flip-flop that is cleared by the initial reset signal, the output signal of the second inverter is applied as a clock signal, and a high power supply voltage is applied to an input terminal; And a third inverter for inverting the output signal of the third flip-flop to generate a mode selection signal. The method of claim 1, wherein the mode selection unit A first multiplexer for selecting one of a horizontal synchronization signal and a data enable signal according to a mode selection signal generated from the mode selection signal generator; And a second multiplexer for selecting one of the vertical synchronization signal and the data enable signal in accordance with the mode selection signal applied from the mode selection signal generator.

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