KR100253735B1 - Synchronous partial response iv channel data detector in a digital vcr - Google Patents

Abstract

PURPOSE: A synchronous partial response channel data detector in a digital magnetic recording/playing system is provided to simply construct an equalizer, and to correctly detect a source signal from a signal played through a magnetic channel. CONSTITUTION: An adaptive equalizer(200) outputs a converted digital sample signal as an equalized signal having a partial response channel characteristic according to a pre-setup coefficient value. A maximum likelyhood sequence detector(60) generates code data of the first and the second state for the equalized signal. A phase controller(100) uses the equalized signal and an output of the maximum likelyhood sequence detector(60), and synchronizes a sampling speed of digital sample data with the code data. The maximum likelyhood sequence detector(60) comprises as follows. A branch matrix generator generates a branch matrix displaying the difference between a reference equalizing signal level and the equalized signal as the first and the second state. A difference estimating capacity delayer generates the difference between current error matrixes for the first and the second state as a difference estimating capacity. A survival path decider traces the last survival path of the first and the second state code data, and generates binary code data.

Description

SYNCHRONOUS PARTIAL RESPONSE IV CHANNEL DATA DETECTOR IN A DIGITAL VCR}

The present invention relates to a digital magnetic recording / reproducing system (hereinafter referred to as a "digital VCR"), and more particularly to a synchronous data detector for detecting a digital data signal reproduced from a digital VCR using a partial response channel.

In a digital VCR for recording digital signals on a magnetic tape, a recording mode for magnetizing a magnetic medium such as a magnetic tape through a winding magnetic head and a rotary transformer, and amplifying a magnetic flux change of the magnetic tape, and restoring or decoding them into digital data. There is a playback mode.

Digital VCR cannot transmit DC component which is a basic characteristic of magnetic channel by using magnetic media as transmission channel, and it is caused by high frequency attenuation characteristics and inter symbol interference (ISI) of adjacent data by high density recording. Transmission is interrupted and influenced by tape transfer and head rotation control.

Conventional digital VCRs use a partial response channel IV scheme to reduce the error rate in the magnetic recording / reproducing path. Such partial response channel is processed so that the transmission channel has characteristics similar to the medium in consideration of the characteristics of the magnetic medium, so that the magnetic channel response is approximated to the ideal partial response IV channel, thereby reducing the error data when the recording data is restored. In this way, in order to amplify the magnetic flux variation of the magnetic tape to completely recover the digitally recorded signal, the reproduction signal must be made into a signal having partial response channel characteristics.

Digital data detection systems for detecting two values of signals reproduced in a digital VCR using a conventional partial response channel mainly use an adaptive decision feedback equalizer (DFE). The DFE performs a function of finding an optimal weight for the distorted reproduction signal through the channel and using the same to restore the original desired signal.

In a digital data detection system having a decision feedback equalizer, a reproduction signal from a recording medium is passed through an adaptive feedforward equalizer (FFE), and then through an adaptive decision feedback equalizer. The sum of the equalizers creates a record / play channel response that meets the ideal partial response IV channel response characteristics. Therefore, the output signal from the decision feedback equalizer means the data signal generated by the reproduction signal passing through the ideal partial response channel.

When the digital VCR system is modeled as a partial response channel, the reconstruction of the reproduced digital signal is performed by determining the magnitude of the signal amplitude of the analog reproduced data at a certain point against the preset threshold value, thereby determining the tri-value {y _n } Determined as one of (+2, 0, -2), and the processed three-value value is decoded into data {b _n } (0, 1) according to a binary decoding decision rule as shown in Equation 1 below every data bit period. Is handled in a manner.

Recently, the digital data detection apparatus for further improving the above-described digital data detection apparatus uses a maximum likelyhood sequence detector in conjunction with the output of the adaptive decision feedback equalizer to reduce the error rate. The highest order detector is an apparatus for estimating the code sequence closest to an arbitrary received code string, and uses a Viterbi algorithm for efficiently searching the above-described close code string using trellis. The Viterbi detector does not estimate received data for each data in the above-described prior art data detection apparatus, but estimates using some data previously received.

The Viterbi detector maintains an order of data determination, called a survival sequence, and corresponding error metric, for each possible state assumed by the grid at any data time. For example, if there are two states in the grid, we maintain two survival orders and the corresponding two error metrics.

At each data time, the equalized received signal values are evaluated to update the error metric for the state of the grid, resulting in an updated survival order. The updated survival order with the minimum error metric is considered to be the recorded data signal order. The oldest data in the survival order is produced at the output of the Viterbi detector, repeating this method for the next data. Thus, the Viterbi detector can provide a very good decoding efficiency with a lower error rate than the conventional decoding scheme using threshold values.

However, in the conventional data detection apparatus using a Viterbi detector, when the magnetic recording / reproducing system is modeled as a partial response channel system, it is possible to decode the equalized signal passing through the partial response channel directly using the Viterbi algorithm. However, at this time, since the number of states of the grating is four, the calculation included in the algorithm becomes complicated, and accordingly, there is a problem that the circuit configuration of the Viterbi detector is complicated.

Therefore, an object of the present invention is to provide a digital data decoding apparatus of a digital VCR.

Another object of the present invention is to provide a digital data detection apparatus having an improved Viterbi detector in a digital VCR.

It is still another object of the present invention to provide a digital data detection apparatus for performing digital data detection in a digital VCR in a synchronous mode.

A digital data detector according to the present invention for achieving the above object comprises: an analog-digital converter for converting the analog reproduction signal into digital sample data according to a sampling frequency; Adaptive equalization outputting the digital sample signal as an equalized signal (in) having partial response channel characteristics according to a predetermined coefficient value adjusted by an error signal based on previous binary code data and previous digital sample data. Way; The first and second selected levels of the idealized equalization signal in the first and second states (+2, 0, -2) according to the first and second selection signals respectively for the signal in equalized by the equalization means. A highest order detector for determining as code data in two states; A sign of the sampling rate and the sign data by detecting a phase error using the equalized signal from the adaptive equalizing means and the output of the highest order detector and generating a sampling clock of the digital sample data proportional to the phase error. Phase control means for synchronizing time difference; And an error signal generator for generating the difference between the equalized signal of the adaptive equalization means and the output of the highest order detector as the error signal.

Further, the highest order detector further comprises: branch metrics BM1, BM2, BM3, BM4 indicating the difference between each level of the reference equalized signal and the equalized signal indicating possible first and second states for each state. Branch metric generating unit for generating each of the; The first selection signal for judging the magnitude of the difference between the two metrics of the first state with respect to the previous difference evaluation amount DEM and selecting the branch metric having the smaller difference therein as the current error metric EM1; A comparison unit for determining the magnitude of the difference between the two metrics of the second state with respect to the difference evaluation amount, and generating the second selection signal for selecting the branch metric having the smaller difference therein as the current error metric EM2; ; The difference EM2-EM1 between the current error metrics for the first and second states selected by the comparison unit is generated as the difference evaluation amount DEM, and the difference evaluation amount is provided to the comparison unit as the previous difference evaluation amount. Difference evaluation delay unit; The binary code data is generated by tracking a final survival path of the first and second state code data according to the first and second selection signals generated from the comparator. And survival path determiner provided as the adaptive equalization means as binary coded data.

1 is a schematic block diagram of a synchronous partial response channel data detector of a digital magnetic recording / reproducing system according to a preferred embodiment of the present invention;

2 is a detailed configuration diagram of a phase detector and a loop filter;

3 is a detailed block diagram of an adaptive feedback equalizer;

4 is a detailed configuration diagram of the filter coefficient updating unit;

5 is a detailed configuration diagram of the highest order detector;

6 is a detailed configuration diagram of a difference evaluation amount delay unit;

7 is a detailed configuration diagram of a survival order determiner;

8A and 8B show state transition diagrams and trellis of a partial response channel system;

9A and 9B illustrate a process in which survival paths converge;

<Description of the code | symbol about the principal part of drawing>

20: voltage controlled oscillator 30: feedforward equalizer

40: decision feedback equalizer 55: error signal generator

60: highest order detector 70: phase detector

80: loop filter

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1, a block diagram of a synchronous partial response channel digital data detection apparatus of a digital VCR according to the present invention is shown. As shown, the synchronous partial response channel type digital data detection apparatus of the present invention includes a head amplifier 10, an analog / digital ("A / D") converter 16, a phase control circuit 100, adaptive determination. The feedback equalizer 200 includes a maximum likelihood sequence detector (MLSD) 60 and an MCU 90 that provides a control signal and a clock necessary for data detection.

The signal recorded on the magnetic tape in the digital VCR is reproduced by a pair of video heads (not shown) alternately switched on the head drum, and amplified by the head amplifier 10. The A / D converter 16 samples the signal amplified by the head amplifier 10 according to the sampling clock provided from the phase control circuit 100 and provides a sampled reproduction signal to the adaptive decision feedback equalizer 200. .

The phase control circuit 100 performs a function of generating a sampling clock required for the A / D converter 16, and includes a phase detector 70, a loop filter 80, a digital / analog converter 170, and a voltage controlled oscillator ( voltage controlled oscillator (VCO) 180.

The phase detector 70 detects the phase change amount as a phase error using the surviving signal from the highest order determiner 60 and provides it to the loop filter 80. The loop filter 80 maintains the state of the phase control circuit 100 to increase performance by removing high frequency components and noise from the output of the phase detector 70. The output of the loop filter 80 is converted to a voltage level through the D / A converter 170 and transferred to the voltage controlled oscillator 180. The voltage controlled oscillator 180 generates a clock frequency that varies linearly with the input voltage and provides it to the A / D converter 16 as a sampling clock.

The adaptive decision feedback equalizer 200 includes a feed forward equalizer (FFE) 30, an FFE coefficient updater 35, a decision feedback equalizer DFE 40, and a DFE coefficient. The updater 45 is configured.

The FFE 30 and the DFE 40 each perform a function of making the signal reproduced from the recording medium into a signal satisfying the ideal PR4 channel response according to the coefficient values transmitted from the corresponding coefficient update units 35 and 45, respectively. do. Therefore, the signal output from the FFE 30 and the DFE 40 means a data signal equalized by the reproduced signal passing through the ideal partial response channel. The output signals of the FFE 30 and the DFE 40 are added by the adder 50, respectively, and the output of the adder 30 is input to the error signal generator 55 and the highest order detector 60. The output of the highest order detector 60 is again provided to the DFE 40 of the adaptive decision feedback equalizer 200 to form a feedback loop. This feedback loop serves to suppress mutual interference between residual data in the recording / reproducing channel. The error signal generator 55 generates an error signal "e" which is the difference between the equalized signal from the adder 50 and the ideal signal detected by the highest order detector 60. This error signal e is provided to the DFE and DFE coefficient update units 40 and 45 and used to adjust the filter coefficients of the FFE 30 and the DFE 40.

The highest order determiner 60 estimates a code sequence that is closest to an arbitrary received code sequence by using the most likelihood estimation decoding algorithm, and outputs the code sequence to the next stage encoder. The maximum likelihood decoding algorithm includes a Viterbi algorithm that efficiently searches for the above-described close code sequence using trellis. This Viterbi algorithm is effectively used to improve the performance of a data detector with inter-symbol interference.

First, the encoding process using the partial response channel will be described.

The binary data sequence "b _k " is precoded and generated as a precoded data string "a _k " according to the following equation.

는 배타 OR(exclusive-OR) 연산을 나타낸다.In the above equation

Represents an exclusive-OR operation.

The precoded data string a _k is converted into a bipolar pulse string a ' _k according to the following equation. At this time, the data of the two-pole pulse train has an amplitude.

Then, the two-pole pulse string a ' _k is encoded according to the coding rule according to the following formula, recorded on a magnetic tape, and reproduced therefrom.

는 디지탈 필터인 등화기를 이용하여 재생된 채널 데이터를 나타낸다. 상술한 부호화 과정에 있어서, 프리코드된 데이터 열

은 2진수에 대하여 실행되지만,

을 생성하는 디지탈 필터링은 2극 펄스에 대하여 실행된다는 것이다.In Equation 4

Denotes channel data reproduced using an equalizer which is a digital filter. In the above-described encoding process, the precoded data string

Runs on binary numbers,

Digital filtering to generate is performed on the bipolar pulse.

이 "0 1 1 0" 인 경우에 수행되는 부호화 과정을 작성하면 하기 표 1과 같다.For example, input symbol (data)

If the coding process performed when "0 1 1 0" is written, it is as Table 1 below.

:Binary symbol data

: * 0 One One 0 Precoded Data Column

: * One One 0 One Precoded Data Column

: One One 0 One One 2-pole pulse data string

: * +1 +1 -One +1 2-pole pulse data string

: * +1 -One +1 +1 Equalized Channel Data : 0 -2 +2 0

은 2극 펄스 데이터 열

와

사이의 관계로부터 구한것이고, 2진 데이터 열

의 값은

와

사이의 관계로부터 구한 것이며 "*"는 돈 케어 상태(don't care)를 나타낸다.Precoded Data Columns in Table 1

Silver 2-pole pulse data string

Wow

From the relationship between the binary data columns

The value of

Wow

"*" Represents the don't care.

가 ±1 인 경우에,

는 세가지의 가능한 값, 즉, +2, 0, -2 의 세가지 레벨(three-level)중의 어느 한 값을 갖는다.Binary in the decoding process

If is ± 1,

Has any of three possible values, namely, three-levels of +2, 0, and -2.

In the encoding process of the partial response channel IV system, the even (or odd) signal code string is only affected by the even (or odd) code. Thus, the partial response channel system may be regarded as two independent partial response channel systems with their partial response channel characteristics (1-D). By using this, it is possible to simplify the calculation required to perform the algorithm by dividing the reproduction signal code sequence into odd and even sequences and detecting the signal codes separately by bit TV decoding. Therefore, the number of states of the grid included in the encoding process of the partial response channel system can be reduced to only two.

라하고, 출력 심볼을

라 하면 이들의 관계는 도 8a에 도시된 상태 전이도와 도 9b에 도시된 격자(trellis)로 표현될 수 있다.Input symbol

And the output symbol

These relationships can be expressed by the state transition diagram shown in FIG. 8A and the trellis shown in FIG. 9B.

8B is a grid for one de-interleaved symbol stream of the partial response channel with P (D) = 1-D. This grating helps to understand the operation of the likelihood order determiner 60. In FIG. 9B, upper vertices 251 and 252 represent state 1 in the grid, and lower vertices 261 and 262 represent state 2. In FIG. Left vertices 251 and 261 represent past states in the grid, and right vertices 252 and 262 represent new states. Each branch that progresses from the old state 251, 261 to the new state 252, 262 is shown by an arrow. Associated with each state vertex is an error metric (EM). EM1c is associated with state 1 of vertex 251 and EM2c is associated with state 2 of vertex 261. Associated with each new state vertex is the updated error metric. EM1 is associated with new state 1 of vertex 252 and EM2 is associated with new state 2 of vertex 262.

) 을 받았다면, 가지를 따라 격자상의 다른 상태로 움직이고, 등화기가 2 진 심볼 데이터 0(=

) 를 받았다면, 가지를 따라 같은 상태로 진행한다. 상태의 전이를 일으키는 이상적인 수신된 등화 신호의 값은 입력 신호를 수신했을 때 진행하게 될 격자상의 가지에 대괄호로 표시되어있다. 따라서, 상태 1의 정점 (251)에서 시작하여, 등화된 채널 데이터가 0 이면, 다음의 기호 시간에 상태 1에 남게되고, 정점(252)에서 끝나게된다. 이것은 등화기가 2 진 심볼 데이터 (

)로서 이진수 0을 수신하였음을 의미한다. 등화된 채널 데이터가 값 +2를 가지면, 상태 2로 전이되고, 정점(262)에서 끝난다. 이것은 등화기가 2 진 심볼 데이터 (

)로서 이진수 1을 수신하였음을 의미한다. 마찬가지로, 상태 2의 정점(261)에서 시작하여, 등화된 채널 데이터가 0 이면, 다음의 기호 시간에 상태 2에 남게되고, 정점(262)에서 끝나게된다. 이것은 등화기가 2 진 심볼 데이터 (

)로서 이진수 0을 수신하였음을 의미한다. 등화된 채널 데이터가 값 -2를 가지면, 상태 1로 전이되고, 정점(252)에서 끝난다. 이것은 등화기가 2 진 심볼 데이터 (

)로서 1을 수신하였음을 의미한다.From any particular past state, the grid is binary symbol data 1 (=

), Move along the branch to another state on the grid, and the equalizer equals binary symbol data 0 (=

), Proceed in the same state along the branches. The value of the ideal received equalization signal that causes the transition is indicated by square brackets on the branch on the grid that will proceed when the input signal is received. Thus, starting at vertex 251 in state 1, if the equalized channel data is zero, it remains in state 1 at the next symbol time and ends at vertex 252. This means that the equalizer has binary symbol data (

) Means that binary 0 was received. If the equalized channel data has a value of +2, it transitions to state 2 and ends at vertex 262. This means that the equalizer has binary symbol data (

Means that binary 1 has been received. Similarly, starting at vertex 261 in state 2, if equalized channel data is zero, it remains in state 2 at the next symbol time and ends at vertex 262. This means that the equalizer has binary symbol data (

) Means that binary 0 was received. If the equalized channel data has a value of -2, it transitions to state 1 and ends at vertex 252. This means that the equalizer has binary symbol data (

Means 1 has been received.

)를 입력 신호로서 수신하기는 불가능하다. 따라서, 격자상의 각 가지에서, 가지 메트릭(branch metric) BM 이 계산된다. 각 가지에서, 실제의 수신된 등화된 채널 신호와 그 가지에 해당하는 이상적인 입력 신호간의 크기의 차이가 계산된다. 이 크기를 가지 메트릭 (BM) 이라 지칭하고, 과거에서 누적된 오류 메트릭과 같이 축적된다. 여기서 오류 메트릭은, 각각의 갱신될 오류 메트릭을 만들기 위한 각각의 그 가지에서의 원천 정점(source vertex)에 관련된다. 이 갱신된 오류 메트릭들은 가장 유망한 순서(most likely sequence)를 결정하는데 사용된다.However, real detectors are ideal for binary symbol data (

) As an input signal is not possible. Thus, for each branch on the grid, a branch metric BM is calculated. In each branch, the difference in magnitude between the actual received equalized channel signal and the ideal input signal corresponding to that branch is calculated. This magnitude is referred to as a branch metric (BM) and accumulates like error metrics accumulated in the past. The error metric here relates to the source vertex at each branch to create each error metric to be updated. These updated error metrics are used to determine the most likely sequence.

For the new symbol, there are two ways to reach the vertex 321 representing state 1. Receive a 0 signal at vertex 251 or a -2 signal at vertex 261. The branch metric BM1 is calculated for branches going from vertex 251 to vertex 252 and the branch metric BM3 is calculated for branches traveling from vertex 251 to vertex 252. These branch metrics accumulate with each error metric associated with their source vertex. That is, the branch metric BM1 accumulates like the error metric EM1c accumulated in the past, creating an updated first error metric (EM1 '= BM1 + EM1c) for the branch going from vertex 251 to vertex 252. Serve The branch metric BM3 accumulates with the current error metric EM2c, producing an updated second error metric (EM1 '' = BM3 + EM2c) for the branch going from vertex 261 to vertex 252. Where the updated error metric with the lesser of the first and second error metrics, EM1 'and EM1' ', is assumed to be a more promising branch to reach state 1, and the updated error for vertex 252 It is selected as the metric EM1.

Similarly, the branch metric BM2 is calculated for the branch that progresses from vertex 251 to vertex 262 and BM4 is calculated for the branch that progresses from vertex 261 to vertex 262. Branch metric BM2 accumulates with current error metric EM1c to produce an updated error metric (EM2 '= BM4 + EM1c) for the branch that progresses from vertex 251 to vertex 262. Branch metric BM4 accumulates with the current error metric EM2c, producing an updated error metric (EM2 "= BM4 + EM2c) for the branch that progresses from vertex 261 to vertex 262. Update with less value It is assumed that the more probable branch of the error metric reaches state 2, which is the updated error metric EM2 for vertex 262. That is, the vertex with fewer error metrics becomes the most promising state. As the state accumulates, as shown in FIG. 10, only the surviving path is selected while blocking the unconnected survival path.

Referring now to FIG. 2, a detailed circuit diagram of the phase detector 70 and loop filter 80 of the phase control loop is shown.

The phase detector 70 performs a function of detecting a phase error using a signal surviving in the highest order detector 500. The phase detector 70 is provided from the highest order detector 500 through lines 472, 482, and 492. It includes a set of three survival signal storage registers 610, 620, 630, an adder 640, and a multiplier 650 that store the surviving signals X _n-1 , X _n , X _{n + 1} .

The outputs of the first register 610 and the third register 630 are respectively provided as inputs of the subtractor 640, and the outputs of the second register 620 are provided to the error signal generator 55 which outputs an error signal. . The subtractor 640 subtracts the outputs of the first and third registers 610 and 630 to provide the phase difference signal X _{n + 1} -X _n-1 of the subtracted survival signal to one input of the multiplier 650. . The multiplier 650 outputs the phase error signal Z _k by multiplying the phase difference signal by the error signal e received from the subtractor 55 as another input signal. An operation of the phase detector 70 performing the above operation may be expressed as shown in Equation 5 below.

The phase error signal Z _k generated at the phase detector 70 is provided to the loop filter 80.

The loop filter 80 performs a function of removing high frequency components or noise from the output of the phase detector 70, and a first multiplier 670 that multiplies the filter constant α and the phase error signal Z _k , and a filter. A second multiplier 680 that multiplies the constant β and the phase error signal Z _k , a first adder 690 that adds the output of the second multiplier 680 and the output of the delayer 700, and a first And a second adder 710 that adds the output of the adder 690 and the output of the first multiplier 670. The loop filter 80 performing the above operation generates an output τ _k represented by Equation 6 below.

The output τ _k of the loop filter 80 is converted into an analog voltage by the next stage D / A converter 170 and then provided to the voltage controlled oscillator 180.

Referring to Fig. 3, a detailed configuration of the FFE 30 and the DFE 40 is shown.

The FFE 30 is formed in a transversal form, which is a kind of finite impulse response (FIR) structure. That is, a tapped delay line 210 and each of the delays sequentially delay the sampled signal "Xn" (= n-th signal) output from the A / D converter 16 through the line 25. The output of each multiplier in the multiplier block 220 and the multiplier block 220 multiplying the delayed signal at line 210 by the adaptive filter coefficient " Cn " It consists of an adder 225 to add. The output of adder 225 is provided to the first input of adder 50 (see FIG. 1).

Similarly, the DFE 40 has the same finite response filter structure as the FFE 30. Since the DFE 40 constructed in the present invention multiplies only the data values "1", "0", and "-1" which survive the highest order detector 60, it is a simple structure with a smaller number of gates than the full bit multiplier configuration. It can be configured as. The DFE 40 modulates the delayed delay line 230 that sequentially delays the output 482 of the highest order detector 60 and the delayed signal of each delay line 230. From the multiplier block 240 to multiply the adaptive filter coefficient " Bn " (= n &lt; th &gt; filter coefficients) through the line 47 and the output of each multiplier in the multiplier block 240, respectively. It is composed. The output of adder 245 is provided to a second input of adder 50. The output of the adder 50 is provided to the highest order determiner 60 via line 52 as described with reference to FIG. 1.

FIG. 4 shows a detailed configuration of the filter coefficient updating units 35 and 45, which is shown, and only one configuration is shown in the drawing.

)에 감산기(55)로부터의 에러 신호(e)를 곱한다. 곱셈기(202)의 출력은 곱셈기(204)에서 FFE(30)또는 DFE(40)로부터 제공되는 n-1 번째의 입력 신호(X_n-1)와 곱해진다. 곱셈기(204)의 출력은 가산기(206)에서 초기 필터계수 갱신부(214)로부터 제공되는 이전의 필터 계수(C_n-1(또는 B_n-1))와 가산됨으로써 갱신될 필터 계수 C_n(또는 B_n)이 구해진다. 가산기(206)에의해 갱신된 필터 계수 C_n(또는 B_n)는 지연기(212)를 통하여 FFE(30) 또는 DFE(40)로 제공된다.Multiplier 202 is a convergence constant value (

) Is multiplied by the error signal e from the subtractor 55. The output of multiplier 202 is multiplied by the n−1 th input signal X _n−1 provided from FFE 30 or DFE 40 at multiplier 204. The output of the multiplier 204 is the filter coefficient C _n (to be updated by adding with the previous filter coefficient C _n-1 (or B _n-1 ) provided from the initial filter coefficient updater 214 in the adder 206. Or B _n ) is obtained. The filter coefficient C _n (or B _n ) updated by the adder 206 is provided to the FFE 30 or the DFE 40 through the delay 212.

The filter coefficient C _n (or B _n ) generated by the above-described operation of the filter coefficient updating units 35 and 45 may be expressed by Equations 7 and 8 below.

In the initial state, the initial coefficient updater 214 receives initial filter coefficient data according to an initial coefficient load control signal from the MCU 90, and the hold switch 208 receives an initial value from the MCU 90. Initial coefficients fed back from the initial coefficient updating unit 214 according to the coefficient load control signal are selectively provided to the initial coefficient updating unit 214 via the delay unit 212. The initial filter coefficients provided from the initial coefficient updater 214 to the FFE and DFE coefficient updaters 35 and 45 are used to receive the existing converged coefficient values to increase the initial convergence speed of the adaptive equalizer filter. do. That is, by using the existing converged value, it helps to find a stable filter coefficient faster.

Referring now to FIG. 5, a detailed block diagram of the highest order detector 60 in accordance with the present invention is shown. The highest order detector 60 includes a branch metric generator 310 for generating a branch metric, a branch metric comparator 330, a difference evaluation amount delay unit 400, and a survival path determiner 500.

The branch metric generator 310 lines the reference level (+2, 0, -2) of the ideal equalization signal provided from the MCU 90 through the signal inversion unit 320 from the adaptive decision feedback equalizer 200. Branch metrics are calculated by calculating absolute values of the first and second subtractors 312 and 314 and the outputs of the first and second subtractors 312 and 314 subtracted from the equalized output in provided through 52. First to third absolute value circuits 322, 324, and 326 for generating (BM1, BM2, BM3, BM4). The output of the first subtractor 312 is connected to the first absolute value circuit 322, the equalized output in is connected to the second absolute value circuit 324, and the output of the second subtractor 314 is the third absolute value. Is connected to the circuit 326.

The first absolute value circuit 322 generates the absolute value difference (| -2.0-in |) of the equalization channel signal with respect to the reference equalized signal level " -2 " as a metric BM3, and the second absolute value circuit 324 The absolute value difference (| 0.0-in |) of the equalization channel signal with respect to the reference equalization signal level " 0 " The absolute difference (| +2.0-in |) of the equalization channel signal for the signal is generated as the branch metric BM2. The branch metrics generated by each of the first to third absolute value circuits 322, 324, 326 are provided to the comparator 330.

The comparator 330 generates error metrics EM1 and EM2 for each state of the decoding grid using the branch metrics provided from the branch metric generator 310. For example, Equation 9 below is a process of finding an error metric (EM1) having a small error value among (BM1 + EM1c) and (BM3 + EM2c), and Equation 10 is represented by (BM2 + EM1c) and (BM4 + EM2c). Equation expressing a process of finding an error metric (EM2) having a small error value.

Herein, a variable for evaluating the difference EM2 to EM1 between the error metric EM1 and EM2 is defined as a difference evaluation amount (“DEM”).

Rewriting Equation 9 to determine the error metric EM1 is shown in Equation 12 below.

Similarly, if the equation 10 is rewritten to determine the error metric EM2, it is expressed as Equation 13.

In the comparator 330, the first adder 332 is used to calculate Equation 12, and an output from the first adder 332 is provided to the first selector 336 and the first comparator 342. The first comparator 342 compares the output of the first adder 332 with the output of the second absolute value circuit 324 and compares the result with the first selector 336 and the next stage survival path storage / update module 500. Output as a multiplexer control signal SS1.

Meanwhile, the second adder 334 is used to calculate Equation 13, and the output of the second adder 334 is provided to the second selector 338 and the second comparator 344. The output signals of the second comparators 342 and 344 are provided as multiplexer control signals SS2 of the second selector 338 and the survival path storage / update module 500 of the next stage.

In the operation, when the output BM1 of the second absolute value circuit 324 in the first comparator 342 is smaller than the output DEMc + BM3 of the first adder 332, the control signal SS1 is " 0 " Is supplied to the selector 336 to cause (BM1) to be selectively outputted, and (BM1) is greater than (DEMc + BM3), the control signal SS1 is provided to the selector 336 as "1" (DEMc + BM3) is to be selectively output. Similarly, if the output BM2 of the third absolute value circuit 326 in the second comparator 344 is smaller than the output DEMc + BM4 of the second adder 334, the control signal SS2 is set to "0". If (BM2) is selectively outputted and (BM2) is greater than (DEMc + BM4), the control signal SS2 is provided to the selector 338 as "1" to (DEMc + BM4). Causes optional output.

The outputs of the first and second selectors 336 and 338 by the control signals SS1 and SS2 of the first and second comparators 342 and 344 are input to the subtractor 350 so that the difference evaluation amount DEM, i.e. ( EM2-EM1). The output of the subtractor 350 is provided to the difference evaluation amount delay unit 400 and the survival path determiner 500 of FIG. 6.

Referring to FIG. 6, the detailed configuration of the difference evaluation amount delay unit 400 is shown.

In the difference evaluation amount delay unit 400, one input terminal of the multiplexer 420 is connected to the output of the subtractor 350 and the output of the (1-D) delayer 426 provided through the line 356, and the multiplexer ( The type force stage of 430 is connected to the output of the subtractor 350 and the output of the delayer 436. An output of the multiplexer 420 is connected to a first input of an AND gate 422. The second input of the AND gate 422 is connected to the clear signal CLR, and its output is connected to the second input terminal of the multiplexer 424. The output of the multiplexer 424 is connected to the delay 426. The output of the delayer 426 is coupled to the first input of the multiplexers 420 and 424 and the first input of the multiplexer 470.

Similarly, the output of multiplexer 430 is connected to the first input of AND gate 432. The second input of AND gate 432 is connected to the clear signal CLR, and its output is connected to the first input of multiplexer 434. The output of the multiplexer 434 is coupled to the delayer 436. An output of the delayer 436 is connected to a second input terminal of the multiplexers 430 and 434 and a second input terminal of the output multiplexer 470.

Meanwhile, the signal INITIAL LOAD from the MCU 90 is connected to the control signal input terminal of the multiplexer 414 through the inverter 412. The output of the multiplexer 414 is connected to the delay 416, the output of the delay 416 is connected to the second input of the inverter 418 and the multiplexer 414, and the output of the inverter 418 is connected to the multiplexer ( It is connected to the first input of 414, and is used as a control signal of the multiplexers 420, 430, 470.

Referring now to FIG. 7, a detailed schematic diagram of survival path determiner 500 is shown. As shown, the survival path determiner 500 includes a survival path selection module 510 and a determination signal generator 560.

The survival path selection module 510 includes multiple stages of survival path storage / update units 420, 430, and 440 for determining survival paths of the first and second states. Each survival path storage / update unit (420, 430, 440) is a multiplexer (421), (431), (441) and path memory (423), (433), (443) for determining the survival path of the first state. And two-input multiplexers 422, 432, 442 and path memories 425, 434, 444 that determine the survival path of the second state. In addition, the survival path selection module 510 may include path memories 425, 435, 445 and path memories 425, 434, and 444 respectively connected to outputs of the path memories 423, 433, and 443 in the first state. Path memory pairs 426, 436, and 446, respectively, connected to the output of the sub-head.

In the case of partial response IV, even and odd-numbered code strings are affected only by the even- and odd-numbered code strings, respectively, so that they are separately separated and applied to the multiplexer. Thus, path memory pairs 423, 425, 433, 435, 443, 445 in the first state and path memory pairs 424, 426, 434, 436, 444, 446 in the second state. Each path memory in i) can reduce the number of gates by using an even and odd multiplexer. The advantage of the present invention is thus used to alternately store and update the surviving paths of even and odd signals using path memory pairs, which may be configured as one shift register.

The control terminals of the multiplexers 421, 431, and 441 for selecting the survival paths in the first state in the survival path selection module 510 are provided via the selection signal (line) 352 provided from the error metric generator 330. SS1), the input of the two-input multiplexer 421 is connected to a signal source providing signals 0 and -2 in the first state, and the input of the two-input multiplexer 431 is connected to the path memory 425, 426, and the input of the two-input multiplexer 441 is configured in a manner that is connected to the output of the path memories 435, 436. Similarly, the control terminal of each multiplexer 422, 432, 442 for selecting the survival path of the second state in the survival path selection module 510 is provided with a selection signal provided through the line 354 from the comparator 330. SS2), the input of the two-input multiplexer 422 is connected to the signal source providing signals 0 and +2 in the second state, and the input of the two-input multiplexer 432 is connected to the path memory 426, And an input of the two-input multiplexer 442 is connected to an output of the path memories 436 and 435.

The output of the path memories 445 and 446 of the survival path storage / update unit 440 of the last stage is connected to the input of the multiplexer 450, and the control signal input of the multiplexer 450 is connected to the input of the code bit discriminator 360. The output is connected via line 370.

The sign bit discriminator 360 determines the size of the difference evaluation amount DEM provided through the line 358 as a sign. In other words, the data output with the two's complement value is negative if the most significant bit MSB of the data is "1", and is positive if "0". That is, if the difference evaluation amount DEM is greater than zero, the sign bit discriminator 360 outputs 0 as a sign bit, and if the difference evaluation amount DEM is less than zero, the sign bit discriminator 360 is referred to as a sign bit. Outputs 1 The code bit determined by the code bit discriminator 360 is provided as a selection control signal for controlling the multiplexer 450 via the line 370.

The operation of the survival path selection module 500 will be described, for example, with respect to an odd number of signals reproduced from the head drum.

In FIG. 9A, a state diagram generated by the survival path determiner 500 is shown. As can be seen in this figure, the selection signals SS1 and SS2 generated at every symbol time by the survival path determiner 500 are shown in Table 2 below.

t1 t2 t3 ... t4 SS1 One 0 One ... 0 SS2 0 One 0 ... One

Path memory value at symbol time t1 Memory (423/424) Memory (433/434) ... Memory (443/444) State 1 -2 0 ... 0 State 2 0 0 ... 0

Path memory value at symbol time t2 Memory (423/424) Memory (433/434) ... Memory (443/444) State 1 0 -2 ... 0 State 2 +2 -2 ... 0

Path memory value at symbol time t3 Memory (423/424) Memory (433/434) ... Memory (443/444) State 1 -2 +2 ... 0 State 2 0 +2 ... 0

Path memory value at symbol time t4 Memory (423/424) Memory (433/434) ... Memory (443/444) State 1 0 -2 ... +2 State 2 +2 -2 ... +2

As such, the path that does not lead through the path memory converges while being deleted. In FIG. 9B, the path of the dotted line survives and the path of the solid line is deleted. Deleting a survival path means that the two path memories are filled with only surviving values.

As described above, the same operation is performed on the even-numbered signal reproduced from the head drum, and detailed description thereof is omitted.

As a result, the multiplexer 450 selectively replaces the survival code values (± 2, 0) provided from the path memories 445 and 446 in the first and second states according to the control signal from the sign bit discriminator 370. ± 2 "is 1 and" 0 "is output as" 0 ", thereby outputting the detected bit.

On the other hand, in the determination signal generator 560, the output of the multiplexer 462 is connected to the delay unit 464, the output of the delay unit 464 is connected to the multiplexer 466, the output of the multiplexer 466 is Connected to a retarder 467. Multiplexers 462 and 466 are controlled by a control signal (INITIAL LOAD) provided via line 358.

The output of the path memories 423, 424 is connected to the multiplexer 470, the output of the path memories 425, 426 is connected to the multiplexer 480, and the output of the path memories 433, 434 is the multiplexer 490. Is connected to. Multiplexers 470 and 490 are controlled by the output of delayer 464, and multiplexer 480 is configured to be controlled by the output of delayer 467.

The outputs of the multiplexers 470, 480, 490 are provided to the phase detector 70 (see FIG. 2) of the phase control circuit 100 via lines 472, 482, 492, respectively.

As described above, according to the present invention, it is possible to design the equalizer in a simpler configuration rather than in the configuration of the full bit adder, and the advantage that the detection of the source signal from the signal reproduced from the magnetic channel is more accurate is provided.

Claims (8)

A data detector for estimating binary code data recorded on the magnetic recording medium from an analog signal reproduced from a magnetic recording medium by a digital magnetic recording / reproducing system, An analog-to-digital converter (16) for converting the analog reproduction signal into digital sample data according to a sampling frequency; Adaptive equalization outputting the digital sample signal as an equalized signal (in) having partial response channel characteristics according to a predetermined coefficient value adjusted by an error signal based on previous binary code data and previous digital sample data. Means 200; The first and second selected levels of the idealized equalization signal in the first and second states (+2, 0, -2) according to the first and second selection signals respectively for the signal in equalized by the equalization means. Determined as sign data of two states, wherein the selected sign data of the first and second states begins with each state from the previous first and second states, and each state transitions to one of the two states. Highest order detector 60 which is data surviving; The sampling rate by detecting a phase error using the equalized signal from the adaptive equalization means 200 and the output of the highest order detector 60 and generating a sampling clock of the digital sample data proportional to the phase error Phase control means (100) for synchronizing a code time difference between the code data and the code data; An error signal generator 55 for generating a difference between the equalized signal of the adaptive equalization means and the output of the highest order detector 60 as the error signal; The highest order detector 60, A branch metric generation, each generating a difference between each level of the reference equalized signal and the equalized signal as a branch metric BM1, BM2, BM3, BM4 representing possible first and second states for each state. Part 310; The first selection signal for judging the magnitude of the difference between the two metrics of the first state with respect to the previous difference evaluation amount DEM and selecting the branch metric having the smaller difference therein as the current error metric EM1; A comparison unit for determining the magnitude of the difference between the two metrics of the second state with respect to the difference evaluation amount, and generating the second selection signal for selecting the branch metric having the smaller difference therein as the current error metric EM2; 330; The difference EM2-EM1 between the current error metrics for the first and second states selected by the comparison unit 330 is generated as the difference evaluation amount DEM, and the difference evaluation amount is the previous difference evaluation amount. A difference evaluation amount delay unit 350 provided to the comparison unit 330; The binary code data is generated by tracking a final survival path of the first and second state code data according to the first and second selection signals generated from the comparator. And a survival path determiner (500) provided as said binary coded data to said adaptive equalization means. The method of claim 1, wherein the branch metric generator 310, A first absolute value circuit (322) for generating an absolute difference (| -2.0-in |) of the equalized signal (in) with respect to the level -2 of the reference equalized signal as the branch metric (BM3); A second absolute value circuit (324) for generating a difference (| 0.0-in |) of the equalized signal (in) with respect to level 0 of the reference equalized signal as the branch metrics (BM1, BM4); And a third absolute value circuit 326 which generates as a branch metric BM2 the difference (| +2.0-in |) of the equalized signal in with respect to +2 of the reference equalized signal. Partial Response Channel Data Detector. The method of claim 2, wherein the comparison unit 330, A first adder (332) for adding the output of the first absolute value circuit (322) and the difference evaluation amount; A second adder (334) for adding the output of the second absolute value circuit (324) and the difference evaluation amount; A first comparator (342) for generating the first selection signal by comparing the output of the first adder (332) with the output of the second absolute value circuit (324); A second comparator (344) for generating the second select signal by comparing the output of the second adder (334) with the output of the third absolute value circuit (324); A first selector (336) for selectively outputting the output of the first adder (332) and the output of the second absolute value circuit (324) to the difference evaluation amount delay unit (350) according to the first selection signal; And a second selector 336 for selectively outputting the output of the second adder 332 and the output of the third absolute value circuit 324 to the difference evaluation amount delay unit 350 according to the second selection signal. And a partial response channel data detector. The method of claim 2, wherein the survival path determiner 500, A survival path selection module 510 for determining a survival path of the code data of the first and second states; A determination signal generator 560 for generating the previous binary code data by using the survival path determined by the survival path selection module 510; The survival path selection module 510 includes multiple stages of survival path storage / update units 520, 530, and 540 for sequentially storing the code data of the first and second states that survive. Each of the storage / update units 420, 430, 440, A path memory for storing and updating the multiplexers 421, 431, 441 for determining code data surviving in the first state in response to the first selection signal, and the survival code data determined by the respective multiplexers ( 423), 433, 443; A path memory for storing and updating the multiplexers 422, 432, and 442 for determining the code data surviving in the second state in response to the second selection signal and the survival paths determined by the respective multiplexers; 425), (434), (444); Selectively outputting the survival code data provided from the path memories 443 and 443 of the first and second states of the survival path storage / update unit 440 at the last stage as the binary code data according to a code data selection control signal. A multiplexer 450; And a code bit discriminator (360) for judging the magnitude of the difference evaluation amount (DEM) as a code and providing it as the code data selection control signal. The path of the second state according to claim 4, wherein the survival path selection module 410 is connected to outputs of the path memories 423, 433, and 443 of the first state, respectively. Further comprising path memories 426, 436, 446 connected to the outputs of the memories 425, 434, 444, respectively, to form a memory pair, Path memory pairs 423, 425, 433, 435, 443, 445 of the first state and path memory pairs 424, 426, 434, 436, 444, 446 of the second state Wherein each path memory in &lt; RTI ID = 0.0 &gt; is &lt; / RTI &gt; is used to alternately store and update a survival path representing a signal reproduced by the magnetic recording / reproducing system. The method of claim 1, wherein the equalizing means 200, A first filter coefficient updater 35 providing a first filter coefficient; A second filter coefficient updater 45 for providing a second filter coefficient; A feedforward equalizer (30) multiplying the equalized signal by the equalized signal to form a signal having the partial response channel characteristic; A decision feedback equalizer (40) for removing the inter-sign interference of the symbol data by multiplying the output of the highest order detector by the second filter coefficients; And an adder (50) for adding the output of the feedforward equalizer and the output of the decision feedback equalizer to generate the equalized signal. 7. The initial data update of claim 6, wherein the first and second filter coefficient updating units (35, 45) respectively provide initial filter coefficients to the feedforward equalizer (30) and the decision feedback equalizer (40). And a section (214). The method of claim 4, wherein the phase control means 100, A phase detector (70) for generating a phase error signal based on the amount of phase change of the output of the highest order detector (60) using the output of the highest order detector (60) and the error signal; A loop filter (80) for removing high frequency components and noise from the phase error signal of the phase detector (70); A digital-analog converter (170) for converting the output of the loop filter (80) into an analog phase error signal; And a voltage controlled oscillator (180) for generating said sampling frequency proportional to said converted analog phase error signal.

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