KR100253646B1 - Signature circuit of semiconductor memory device - Google Patents

Abstract

PURPOSE: A signature circuit of semiconductor memory device is provided to prevent a leakage current, through the third power source terminal, which causes a DC voltage drop by storing information of power source affecting the operation of a memory device. CONSTITUTION: The circuit includes first and second powers(VIN_VDD,VIN_GND), first and second terminals(20,30), a buffer(100), the third terminal(40), a pad(10), a switch(200) and a resistance circuit. The first and second powers are selectively connected to a corresponding one of the first and second terminals. The buffer outputs as a switch control signal by buffering one of the first and second powers from a selected one of the first and second terminals. The third terminal supplies the third power. An information detecting signal for detecting information is applied to the pad. The switch is connected to the third terminal and turned on/off in response to the switch control signal. The resistance circuit is located between the switch and the pad.

Description

Signature circuit of semicondoctor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a signature circuit of a semiconductor memory device capable of storing predetermined information about a semiconductor memory device and determining the predetermined information in a package state.

Input / output structures such as × 1 / × 4 / × 8 / × 16 of semiconductor memory devices may be implemented by metal or package wire bonding, and defective memory cells may be formed by capacitive redundancy circuits. Can be saved. In general, when the above method is used, information about an input / output structure of a memory chip, a prime die, and a repaired die may be obtained by applying a predetermined signal to a pin from the outside. A semiconductor memory device, such as a ROM, stores specific information in a cell array, but a semiconductor memory device, such as a stack RAM or a dynamic RAM, stores a specific information by using a signature circuit. Such a signature circuit can detect information stored in advance according to the amount of current flowing when a predetermined signal is applied to a pin from the outside. This signature circuit should not affect current characteristics such as pin leackage current in the chip's normal operating mode. In other words, no current should flow into the signature circuit even if a predetermined signal is applied to the pin under normal operation.

Such a signature circuit may detect information stored in advance according to the amount of current flowing when a predetermined signal is applied to a pin from the outside. This signature circuit should not affect current characteristics such as pin leackage current in the chip's normal operating mode. In other words, no current should flow into the signature circuit even if a predetermined signal is applied to the pin in the chip's normal operating state.

1 is a detailed circuit diagram illustrating a signature circuit of a semiconductor memory device according to the prior art.

Referring to FIG. 1, the signature circuit includes a pad 10, a mode selection unit 100, and a current detection control unit 200 connected to a predetermined pin during wire bonding. The mode selection unit 100 serves to turn on / off the flow of current and is connected to a fuse means F1 connected between the power supply terminal 20 to which the power supply voltage VIN_VDD is applied and the current detection control unit 200. Was done. That is, information indicating the input / output structure of the semiconductor memory device, the type of die, and the like is stored depending on whether the fuse means F1 is cut. The current detection control unit 200 controls the flow of current according to the voltage difference between the power supply terminal 20 and the pad 10 to which a predetermined signal is applied from the outside depending on whether the fuse means 100 is cut. . The current detection controller 200 includes a plurality of NMOS transistors M1-M3 having a channel connected in series between the pad 10 and one end of the fuse means F1, and each gate and each drain thereof interconnected. Was done.

In the signature circuit, when the fuse means F1 is not cut, the pad 10 sums the threshold voltages Vth of the NMOS transistors M1 to M3 and the power supply voltage VIN_VDD. When the test voltage (VDD + 3Vth) applied to the pad 10 is higher than the sum of the values), the transistors M1-M3 are activated and a predetermined current flows to the power terminal 1. On the other hand, when the fuse means F1 is cut, the current path to the power terminal 1 is cut off, so that current does not flow to the power terminal 20 even when a test voltage is applied to the pad 10. In the actual test, a voltage of 0 volts is applied to the power supply terminal 20 and a test voltage is applied to the pad 10, and then the stored information is detected according to the amount of current flowing between the power supply terminal 20 and the pad 10. do. Here, the test voltage is applied at a voltage higher than the sum of the threshold voltage Vth of each of the NMOS transistors M1-M3 of the current detection controller 200 and the voltage applied to the power terminal 20 during the test.

However, according to the signature circuit of the conventional semiconductor memory device as described above, 3.3 volts (when a product having an operating voltage of 3.3 volts) is applied to the power supply terminal 20 during normal chip operation, and is applied to the pad 10 from the outside. Only when a test voltage of 6.3 volts or more is applied, the pin leakage current flows through the current detection controller 200. The input / output structure of the semiconductor memory device may be designed such that the input / output structure of the semiconductor memory device is changed by connecting (wire bonding) the power supply voltage terminal to the ground voltage terminal or the ground voltage terminal to the power supply voltage terminal. In this case, the power supply terminal 20 shown in FIG. 1 will be connected to the ground terminal 30 to which the ground voltage VIN_GND is applied. Under these conditions, when the chip operates normally in an operating region with an external voltage of 3 volts or more, the pin leakage current always flows due to the voltage difference between the pin, that is, the pad (10, 3 volts or more) and the power supply terminal 30, 0 volts. do. As a result, there is a problem that the current DC characteristics of the semiconductor memory device are not satisfied.

Accordingly, an object of the present invention is to provide a signature circuit of a semiconductor memory device which is proposed to solve the above-mentioned problems and is controlled by a signal that affects the operation of a product during package wire bonding.

1 is a circuit diagram showing a signature circuit of a semiconductor memory device according to the prior art;

2 is a circuit diagram illustrating a signature circuit of a semiconductor memory device according to an embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

100: buffer 200: switch circuit

300: resistance circuit

According to one aspect of the present invention for achieving the above object, the signature circuit of the semiconductor memory device according to the present invention comprises: first and second power sources; First and second terminals; The first and second power supplies are optionally connected to a corresponding one of the first and second terminals, and any of the first and second power supplies from a selected one of the first and second power terminals. A buffer for buffering one and outputting it as a switch control signal; A third terminal for providing a third power source; A pad to which an information detection output signal for detecting information is applied; The third terminal; A pad to which an information detection signal for detecting information is applied; A switch connected to the third terminal, the switch being turned on / off in response to the switch control signal; A resistor circuit is included between the switch and the pad. Wherein the buffer includes a plurality of inverters connected in series between one of the first and second terminals and the switch, and the switch is a current path and the buffer formed between the third terminal and the resistance circuit. And a MOS transistor having a gate controlled by the switch control signal from the. The resistor circuit further includes a second MOS transistor having a source connected to one end of the switch, a first MOS transistor having a gate and a drain connected in common, and a gate and a drain connected in common to a source connected to the drain of the first MOS transistor. And a third MOS transistor having a MOS transistor, a source connected to the drain of the second MOS transistor, and a gate and a drain connected to the pad.

Such a circuit can satisfy the current DC characteristics of the semiconductor memory device by blocking the pin leakage current flowing through the signature circuit in the normal operation mode.

Hereinafter, the present invention will be described in detail with reference to FIG. 2.

In Fig. 2, the same reference numerals are given to the components having the same functions as the components shown in Fig. 1.

Referring to FIG. 2, in the signature circuit of the novel semiconductor memory device of the present invention, when an input / output structure of the semiconductor memory device has a different input / output structure according to a connection state of a power supply voltage terminal and a ground voltage terminal, information about the input / output structure is stored. In order to control the switch circuit 200 using the selection signal S output from the buffer 100 to which a power supply voltage affecting the operation of the semiconductor memory device is applied. The signature circuit according to the present invention includes a plurality of power supply voltage terminals, that is, first and second power supply voltage terminals to which the power supply voltage VIN_VDD and the ground voltage VIN_GND are respectively applied to the mode selection unit 100. By using the third power supply voltage terminal 40 that is independent of the fields 20 and 30 and to which the external voltage VDDQ, which is separated internally, is applied, specific information (for example, a power supply voltage is applied to the buffer 100). Information about whether the ground voltage is applied or not). As a result, in the package state, the test voltage (external voltage + 3Vth) is applied to the pin connected to the pad 10 and the presence or absence of current flows to the third power supply voltage terminal 40 to which the external voltage VDDQ is applied. Therefore, the semiconductor memory device may know information about whether the first power supply voltage terminal 20 or the second power supply voltage terminal 30 is connected to the buffer 100. Thus, the current DC characteristic can be satisfied by blocking the pin leakage current flowing through the signature circuit according to the present invention in the normal operating region by using the plurality of power supply voltage terminals.

FIG. 2 is a detailed circuit diagram illustrating a signature circuit of a semiconductor memory device according to an exemplary embodiment of the present invention.

When the first power supply voltage terminal 20 is bonded to the buffer 100 and the second power supply voltage terminal 30 is bonded, the input / output structure of the semiconductor memory device is designed to be different from each other. The signature circuit is shown in FIG. The first and second power supply voltage terminals 20 and 30 to which the signals VIN_VDD and VIN_GND affect the operation of the semiconductor memory device are connected to input terminals of the buffer 100. The third power supply voltage terminals 40, which are not connected to the second power supply voltage terminals 20 and 30 and the chip internally, are connected to one end of the current detection switch circuit 200. The pad 10 to which the test voltage VDDQ + 3Vth is applied from the outside is connected to the other terminal of the active resistance circuit 300 having one terminal connected to the switch circuit 200, and the pad 10 is in a package state. Will be connected to the pin.

When detecting the input / output mode of the semiconductor memory device using the signature circuit, that is, to determine whether the first power supply voltage terminal 20 or the second power supply voltage terminal 30 is connected to the buffer 100. 0 volts is applied to the third power supply voltage terminal 40. At this time, when a test voltage (VDDQ + 3Vth, a voltage of 3 volts or more) is applied to the pad 10, when the first power voltage terminal 20 is connected to the buffer 100, a current path of the switch circuit 200 is provided. Is activated so that a predetermined current flows from the pad 10 to the third power supply voltage terminal 40. On the other hand, when the second power supply voltage terminal 30 is connected to the buffer 100, the current path of the switch circuit 200 is inactivated so that no current flows. In this way, the input / output mode can be determined according to the presence or absence of current flow.

In the normal chip operating region, since a voltage of 3.3 volts is applied to the third power voltage terminal 40, the pin leakage current may flow only when the voltage level applied to the pad 10 is 6.3 volts or more. In addition, when a voltage of 3.3 volts is applied to the third power supply voltage terminal 40 and a test voltage (6.3 volts or more) is applied to the pad 10, which terminal is present in the buffer 100 with or without current flowing. The input / output mode of the semiconductor memory device can be determined by detecting whether the connection is made. Therefore, when the semiconductor memory device operates under the normal operating region, the pin leakage current does not flow through the signature circuit according to the present invention, and thus does not affect the current DC characteristics of the semiconductor memory device.

As described above, the pin leakage current from the pin in the normal operation region to the third power supply voltage terminal is stored by storing specific information according to a signal affecting the operation of the semiconductor memory device, that is, the supply power supply (power supply voltage and ground voltage). By preventing the flow, it is possible to prevent the current DC characteristics of the semiconductor memory device from dropping.

Claims (4)

First and second power supplies VIN_VDD and VIN_GND; First and second terminals 20 and 30; The first and second power sources are optionally connected to a corresponding one of the first and second terminals 20, 30 and from a selected one of the first and second power terminals 20, 30. A buffer (100) for buffering any one of said first and second power sources and outputting it as a switch control signal (S); A third terminal 40 for providing a third power source; A pad 10 to which an information detection signal for detecting information is applied; A switch (200) connected to the third terminal and turned on / off in response to the switch control signal; And a resistance circuit (300) between the switch and the pad. The method of claim 1, wherein the buffer 100 includes a plurality of inverters 11 and 12 connected in series between the switch 200 of one of the first and second terminals 20 and 30. Signature circuit of semiconductor memory device. The switch 200 of claim 1, wherein the switch 200 is controlled by a current path formed between the third terminal 40 and the resistance circuit 300 and the switch control signal S from the buffer 100. Signature circuit of a semiconductor memory device including a MOS transistor M4 having a gate to be formed The method of claim 1, wherein the source is connected to one end of the switch 200, the first MOS transistor M3 having a gate and a drain connected in common, and the source connected to the drain of the first MOS transistor M3. A second MOS transistor M2 having a gate and a drain connected to each other, a source connected to the drain of the second MOS transistor M2, and a third MOS transistor M1 having a gate and a drain connected to the pad 10. The signature circuit of the semiconductor memory device comprising a.

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