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KR100253338B1 - Method for forming wire of semiconductor device - Google Patents

Method for forming wire of semiconductor device Download PDF

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Publication number
KR100253338B1
KR100253338B1 KR1019970054375A KR19970054375A KR100253338B1 KR 100253338 B1 KR100253338 B1 KR 100253338B1 KR 1019970054375 A KR1019970054375 A KR 1019970054375A KR 19970054375 A KR19970054375 A KR 19970054375A KR 100253338 B1 KR100253338 B1 KR 100253338B1
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South Korea
Prior art keywords
film
wiring layer
insulating film
forming
wiring
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KR19990033117A (en
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김경준
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming an interconnection line of a semiconductor device is provided to reduce a difference in height of surfaces and further to remove the formation of voids. CONSTITUTION: In the method, after a trench is formed in a semiconductor substrate(1), the first interconnection line(2) is formed in the trench. The first insulating layer(3) and the first planarized layer(4) are then sequentially deposited over the substrate(1), and the planarized layer(4) is etched back. Next, the second insulating layer(5) is wholly deposited, and the second interconnection line(6) is formed thereon. The first oxide sidewall(20) is then formed on a side of the second interconnection line(6). Thereafter, the third insulating layer(7) and the second planarized layer(8) are sequentially deposited over the second insulating layer(5), and the second planarized layer(8) is etched back. After that, the fourth insulating layer is wholly deposited, and the third interconnection line(10) is formed thereon. Next, the second oxide sidewall(30) is formed on a side of the third interconnection line(10).

Description

반도체소자의 배선형성방법Wiring Formation Method of Semiconductor Device

본 발명은 반도체소자의 배선형성방법에 관한 것으로, 특히 다층구조를 갖는 배선의 급격한 단차에 의한 신뢰성 저하를 개선하기에 적당하도록 한 반도체소자의 배선형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a wiring of a semiconductor device, and more particularly, to a method of forming a wiring of a semiconductor device, which is suitable for improving the reliability deterioration caused by a sharp step of a wiring having a multilayer structure.

종래 반도체소자의 배선형성방법을 도면을 참조하여 상세히 설명하면 다음과 같다.A wiring forming method of a conventional semiconductor device will now be described in detail with reference to the accompanying drawings.

도1a 내지 도1e는 종래 반도체소자의 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 소자들이 형성된 반도체기판(1)의 일부를 식각하여 트랜치구조를 형성한 후, 그 트랜치구조의 내부에 제1배선층(2)을 형성하는 단계(도1a)와; 제1배선층(2)이 형성된 반도체기판(1)의 상부전면에 절연막(3)과 평탄화막(4)을 차례로 증착한 후, 그 평탄화막(4)을 에치백(etch back)하여 상부를 평탄화하는 단계(도1b)와; 평탄화막(4) 및 노출된 절연막(3)의 상부에 절연막(5)을 증착한 후, 그 절연막(5)의 상부에 제2배선층(6)을 형성하는 단계(도1c)와; 제2배선층(6)이 형성된 절연막(5)의 상부전면에 절연막(7)과 평탄화막(8)을 차례로 증착한 후, 그 평탄화막(8)을 에치백하여 상부를 평탄화하는 단계(도1d)와; 평탄화막(8) 및 노출된 절연막(7)의 상부에 절연막(9)을 증착하는 단계(도1e)로 이루어진다. 이하, 상기한 바와같은 종래 반도체소자의 배선형성방법을 좀더 상세히 설명한다.1A through 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art. As shown in FIG. 1A through FIG. 1E, a trench structure is formed by etching a portion of the semiconductor substrate 1 on which the devices are formed, Forming one wiring layer 2 (FIG. 1A); After depositing the insulating film 3 and the planarization film 4 on the upper surface of the semiconductor substrate 1 on which the first wiring layer 2 is formed, the planarization film 4 is etched back to planarize the top. (Step 1b); Depositing an insulating film 5 on the planarization film 4 and the exposed insulating film 3, and then forming a second wiring layer 6 on the insulating film 5 (FIG. 1C); After depositing the insulating film 7 and the planarization film 8 on the upper surface of the insulating film 5 on which the second wiring layer 6 is formed, the flattening film 8 is etched back to planarize the top (FIG. 1D). )Wow; And depositing an insulating film 9 on the planarization film 8 and the exposed insulating film 7 (FIG. 1E). Hereinafter, the wiring forming method of the conventional semiconductor device as described above will be described in more detail.

먼저, 도1a에 도시한 바와같이 소자들이 형성된 반도체기판(1)의 일부를 식각하여 트랜치구조를 형성한 후, 그 트랜치구조의 내부에 제1배선층(2)을 형성한다. 이때, 제1배선층(2)은 트랜치구조가 형성된 반도체기판(1)의 상부전면에 증착한 후, 사진식각공정을 통해 식각하여 트랜치구조의 내부에 매립하여 형성한다.First, as shown in FIG. 1A, a portion of the semiconductor substrate 1 on which the elements are formed is etched to form a trench structure, and then a first wiring layer 2 is formed inside the trench structure. In this case, the first wiring layer 2 is deposited on the upper surface of the semiconductor substrate 1 in which the trench structure is formed, and then etched through a photolithography process to be embedded in the trench structure.

그리고, 도1b에 도시한 바와같이 제1배선층(2)이 형성된 반도체기판(1)의 상부전면에 절연막(3)과 평탄화막(4)을 차례로 증착한 후, 그 평탄화막(4)을 에치백하여 상부를 평탄화한다. 이때, 절연막(3)은 산화막(SiO2)을 플라즈마화학기상증착법(PECVD)으로 증착하며, 평탄화막(4)은 에스오지(SOG : spin on glass)코팅을 통해 형성하고, 그 평탄화막(4)은 절연막(3)의 상부가 평탄화 될때까지 에치백한다.Then, as shown in FIG. 1B, an insulating film 3 and a planarization film 4 are sequentially deposited on the upper surface of the semiconductor substrate 1 on which the first wiring layer 2 is formed, and then the planarization film 4 is deposited. To make it back, flatten the top. At this time, the insulating film 3 is deposited by the plasma chemical vapor deposition (PECVD), the oxide film (SiO 2 ), the planarization film 4 is formed through spin on glass (SOG) coating, the planarization film 4 ) Is etched back until the top of the insulating film 3 is planarized.

그리고, 도1c에 도시한 바와같이 평탄화막(4) 및 노출된 절연막(3)의 상부에 절연막(5)을 증착한 후, 그 절연막(5)의 상부에 제2배선층(6)을 형성한다. 이때, 절연막(5)은 제1배선층(2)과 제2배선층(6)의 층간절연막(interlayer metal dielectric : IMD)으로 절연막(3)과 동일하게 산화막을 플라즈마화학기상증착법으로 증착한다.Then, as shown in FIG. 1C, an insulating film 5 is deposited on the planarization film 4 and the exposed insulating film 3, and then a second wiring layer 6 is formed on the insulating film 5. . In this case, the insulating film 5 is an interlayer metal dielectric (IMD) of the first wiring layer 2 and the second wiring layer 6, and the oxide film is deposited by the plasma chemical vapor deposition method in the same manner as the insulating film 3.

그리고, 도1d에 도시한 바와같이 제2배선층(6)이 형성된 절연막(5)의 상부전면에 절연막(7)과 평탄화막(8)을 차례로 증착한 후, 그 평탄화막(8)을 에치백하여 상부를 평탄화한다. 이때, 평탄화막(8)은 평탄화막(4)과 동일하게 에스오지코팅을 통해 형성함과 아울러 절연막(7)의 상부가 평탄화 될때까지 에치백한다.Then, as shown in FIG. 1D, the insulating film 7 and the planarization film 8 are sequentially deposited on the upper surface of the insulating film 5 on which the second wiring layer 6 is formed, and then the planarization film 8 is etched back. To flatten the top. At this time, the planarization film 8 is formed through the SG coating similarly to the planarization film 4 and etched back until the upper portion of the insulating film 7 is planarized.

그리고, 도1e에 도시한 바와같이 평탄화막(8) 및 노출된 절연막(7)의 상부에 절연막(9)을 증착한다. 이때, 절연막(9)은 제2배선층(6)과 이후에 형성되는 제3배선층의 층간절연막이다.1E, an insulating film 9 is deposited on the planarization film 8 and the exposed insulating film 7. At this time, the insulating film 9 is an interlayer insulating film of the second wiring layer 6 and the third wiring layer formed thereafter.

이후, 상기와 동일하게 배선층의 상부에 층간절연막 및 평탄화막을 형성한 후, 배선층을 형성하여 다층의 배선구조를 형성한다.Thereafter, an interlayer insulating film and a planarization film are formed on the wiring layer in the same manner as above, and then a wiring layer is formed to form a multilayer wiring structure.

그러나, 상기한 바와같이 제조되는 종래 반도체소자의 배선형성방법은 배선층의 급격한 단차로 인해 이후의 사진식각공정에서 부분적인 노광부족으로 배선층간의 접촉이 발생하여 배선의 신뢰성이 저하되는 문제점과; 평탄화막을 에치백할 때 배선사이의 이격거리가 협소한 곳에서 보이드(void)가 발생하는 문제점이 있었다.However, the wiring forming method of the conventional semiconductor device manufactured as described above has a problem that the reliability of the wiring is deteriorated because contact between the wiring layers occurs due to partial exposure in the subsequent etching process due to the rapid step of the wiring layer; When etching back the planarization film, there is a problem in that voids are generated at a narrow distance between wirings.

본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 배선층의 단차를 완만하게 하고, 배선사이의 이격거리가 협소한 곳에서 발생하는 보이드를 제거할 수 있는 반도체소자의 배선형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of smoothing a step of a wiring layer and removing voids generated at a narrow distance between wirings. It is to provide a wiring forming method.

도1은 종래 반도체소자의 배선형성방법을 보인 수순단면도.1 is a cross-sectional view showing a method for forming a wiring of a conventional semiconductor device.

도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

1:반도체기판 2,6,10:제1,제2,제3배선층1: semiconductor substrate 2, 6, 10: first, second, third wiring layer

3,5,7,9:절연막 4,8:평탄화막3,5,7,9 Insulation film 4,8 Flattening film

20,30:산화막측벽20,30: oxide film side wall

상기한 바와같은 본 발명의 목적은 소정거리 이격되어 제1배선층이 형성된 반도체기판의 상부전면에 제1절연막과 제1평탄화막을 차례로 증착하고, 그 제1평탄화막을 에치백하여 평탄화한 후, 상부전면에 제2절연막을 증착하는 단계와; 상기 제2절연막의 상부에 사진식각공정을 통해 소정거리 이격되도록 제2배선층을 형성한 후, 그 제2배선층의 측면에 각각 제1산화막측벽을 형성하는 단계와; 상기 제1산화막측벽이 형성된 제2배선층 및 제2절연막의 상부전면에 제3절연막과 제2평탄화막을 차례로 증착하고, 그 제2평탄화막을 에치백하여 평탄화한 후, 상부전면에 제4절연막을 증착하는 단계와; 상기 제4절연막의 상부에 사진식각공정을 통해 소정거리 이격되도록 제3배선층을 형성한 후, 그 제3배선층의 측면에 각각 제2산화막측벽을 형성하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 배선형성방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.As described above, an object of the present invention is to deposit a first insulating film and a first planarization film on the upper surface of a semiconductor substrate on which a first wiring layer is formed at a predetermined distance, and then etch back the planarization film to planarize the upper surface. Depositing a second insulating film on the substrate; Forming a second wiring layer on the second insulating layer so as to be spaced apart by a predetermined distance through a photolithography process, and then forming first oxide side walls on the side surfaces of the second wiring layer; A third insulating film and a second flattening film are sequentially deposited on the upper surfaces of the second wiring layer and the second insulating film on which the first oxide film side wall is formed, and the second flattening film is etched back to planarize, and then a fourth insulating film is deposited on the upper front surface. Making a step; The third wiring layer is formed on the fourth insulating layer to be spaced apart by a predetermined distance through a photolithography process, and then the second oxide film side walls are formed on the side surfaces of the third wiring layer, respectively. The wiring forming method of the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도2a 내지 도2f는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 소자들이 형성된 반도체기판(1)의 일부를 소정거리 이격되도록 식각하여 트랜치구조를 형성한 후, 그 트랜치구조의 내부에 제1배선층(2)을 형성하는 단계(도2a)와; 제1배선층(2)이 형성된 반도체기판(1)의 상부전면에 절연막(3)과 평탄화막(4)을 차례로 증착한 후, 그 평탄화막(4)을 에치백하여 상부를 평탄화하는 단계(도2b)와; 평탄화막(4) 및 노출된 절연막(3)의 상부에 절연막(5)을 증착한 후, 그 절연막(5)의 상부에 소정거리 이격된 제2배선층(6)을 형성하는 단계(도2c)와; 그 제2배선층(6)이 형성된 절연막(5)의 상부전면에 산화막을 증착한 후, 등방성(isotropic) 식각방식을 통해 식각하여 제2배선층(6)의 측면에 각각 산화막측벽(20)을 형성하는 단계(도2d)와; 그 산화막측벽(20)이 형성된 제2배선층(6) 및 절연막(5)의 상부전면에 절연막(7)과 평탄화막(8)을 차례로 증착하고, 그 평탄화막(8)을 에치백하여 평탄화한 후, 상부전면에 절연막(9)을 증착하는 단계(도2e)와; 상기 절연막(9)의 상부에 사진식각공정을 통해 소정거리 이격되도록 제3배선층(10)을 형성한 후, 상기 도2d의 단계와 동일하게 산화막을 증착하고, 등방성 식각방식을 통해 식각하여 제3배선층(10)의 측면에 각각 산화막측벽(30)을 형성하는 단계(도2f)로 이루어진다. 이하, 상기한 바와같은 본 발명의 일 실시예를 좀더 상세히 설명한다.2A to 2F are cross-sectional views showing an embodiment of the present invention. As shown in FIG. 2A to 2F, a trench structure is formed by etching a portion of the semiconductor substrate 1 on which elements are formed to be spaced a predetermined distance, and then forming a trench structure. Forming a first wiring layer 2 in the interior thereof (FIG. 2A); After depositing the insulating film 3 and the planarization film 4 on the upper surface of the semiconductor substrate 1 on which the first wiring layer 2 is formed, the planarization film 4 is etched back to planarize the top (Fig. 2b); Depositing an insulating film 5 on the planarization film 4 and the exposed insulating film 3, and then forming a second wiring layer 6 spaced a predetermined distance on the insulating film 5 (FIG. 2C) Wow; After the oxide film is deposited on the upper surface of the insulating film 5 on which the second wiring layer 6 is formed, the oxide film side walls 20 are formed on the side surfaces of the second wiring layer 6 by etching through an isotropic etching method. (FIG. 2D); The insulating film 7 and the planarization film 8 are sequentially deposited on the upper surface of the second wiring layer 6 and the insulating film 5 on which the oxide film side wall 20 is formed, and the planarization film 8 is etched back to planarize. Thereafter, depositing an insulating film 9 on the upper front surface (FIG. 2E); After the third wiring layer 10 is formed on the insulating layer 9 so as to be spaced apart by a predetermined distance through a photolithography process, an oxide film is deposited in the same manner as in FIG. 2D and etched through an isotropic etching method to form a third The step of forming an oxide film side wall 30 on each side of the wiring layer 10 (FIG. 2F). Hereinafter, an embodiment of the present invention as described above will be described in more detail.

먼저, 도2a에 도시한 바와같이 소자들이 형성된 반도체기판(1)의 일부를 소정거리 이격되도록 식각하여 트랜치구조를 형성한 후, 그 트랜치구조의 내부에 제1배선층(2)을 형성한다. 이때, 제1배선층(2)은 트랜치구조가 형성된 반도체기판(1)의 상부전면에 증착한 후, 사진식각공정을 통해 식각하여 트랜치구조의 내부에 매립한다.First, as shown in FIG. 2A, a portion of the semiconductor substrate 1 on which the elements are formed is etched to be spaced a predetermined distance to form a trench structure, and then a first wiring layer 2 is formed in the trench structure. In this case, the first wiring layer 2 is deposited on the upper surface of the semiconductor substrate 1 in which the trench structure is formed, and then etched through a photolithography process to be embedded in the trench structure.

그리고, 도2b에 도시한 바와같이 제1배선층(2)이 형성된 반도체기판(1)의 상부전면에 절연막(3)과 평탄화막(4)을 차례로 증착한 후, 그 평탄화막(4)을 에치백하여 상부를 평탄화한다. 이때, 절연막(3)은 종래와 동일하게 산화막을 플라즈마화학기상증착법을 통해 증착하고, 평탄화막(4)은 에스오지코팅을 통해 형성한 후, 절연막(3)의 일부가 노출될때까지 에치백한다.Then, as shown in FIG. 2B, the insulating film 3 and the planarization film 4 are sequentially deposited on the upper surface of the semiconductor substrate 1 on which the first wiring layer 2 is formed, and then the planarization film 4 is deposited on the substrate. To make it back, flatten the top. At this time, the insulating film 3 is deposited by a plasma chemical vapor deposition method in the same manner as before, and the planarization film 4 is formed through the sedge coating, and then etched back until a part of the insulating film 3 is exposed. .

그리고, 도2c에 도시한 바와같이 평탄화막(4) 및 노출된 절연막(3)의 상부에 절연막(5)을 증착한 후, 그 절연막(5)의 상부에 소정거리 이격된 제2배선층(6)을 형성한다. 이때, 절연막(5)은 층간절연막으로 종래와 동일하게 산화막을 플라즈마화학기상증착법으로 증착한다.As shown in FIG. 2C, after the insulating film 5 is deposited on the planarization film 4 and the exposed insulating film 3, the second wiring layer 6 spaced a predetermined distance apart from the insulating film 5. ). At this time, the insulating film 5 is an interlayer insulating film, and the oxide film is deposited by plasma chemical vapor deposition as in the prior art.

그리고, 도2d에 도시한 바와같이 제2배선층(6)이 형성된 절연막(5)의 상부전면에 산화막을 증착한 후, 등방성 식각방식을 통해 식각하여 제2배선층(6)의 측면에 각각 산화막측벽(20)을 형성한다. 이때, 산화막측벽(20)은 산화막을 400℃의 온도에서 플라즈마화학기상증착법으로 300Å∼500Å의 두께만큼 증착시킨후, 등방성 식각방식으로 식각하여 형성한다.As shown in FIG. 2D, an oxide film is deposited on the upper surface of the insulating film 5 on which the second wiring layer 6 is formed, and then etched by an isotropic etching method to the sidewalls of the oxide film on the side surfaces of the second wiring layer 6, respectively. 20 is formed. At this time, the oxide film side wall 20 is formed by depositing the oxide film by a thickness of 300 kPa to 500 kPa by a plasma chemical vapor deposition method at a temperature of 400 ° C, and then etching by an isotropic etching method.

그리고, 도2e에 도시한 바와같이 산화막측벽(20)이 형성된 제2배선층(6) 및 절연막(5)의 상부전면에 절연막(7)과 평탄화막(8)을 차례로 증착하고, 그 평탄화막(8)을 에치백하여 평탄화한 후, 상부전면에 절연막(9)을 증착한다. 이때, 절연막(7) 및 평탄화막(8)은 상기 절연막(3) 및 평탄화막(4)과 동일하게 형성한다.As shown in FIG. 2E, the insulating film 7 and the planarization film 8 are sequentially deposited on the upper surface of the second wiring layer 6 and the insulating film 5 on which the oxide film side wall 20 is formed, and the planarization film ( 8) is etched back to planarization, and an insulating film 9 is deposited on the upper surface. At this time, the insulating film 7 and the flattening film 8 are formed in the same manner as the insulating film 3 and the flattening film 4.

그리고, 도2f에 도시한 바와같이 절연막(9)의 상부에 사진식각공정을 통해 소정거리 이격되도록 제3배선층(10)을 형성한 후, 상기 도2d의 단계와 동일하게 산화막을 증착하고, 등방성 식각방식을 통해 식각하여 제3배선층(10)의 측면에 각각 산화막측벽(30)을 형성한다. 이때, 산화막측벽(30)은 산화막을 400℃의 온도에서 플라즈마화학기상증착법으로 500Å∼1000Å의 두께만큼 증착시킨후, 등방성 식각방식으로 식각하여 형성한다.As shown in FIG. 2F, after forming the third wiring layer 10 on the insulating layer 9 to be spaced apart by a predetermined distance through a photolithography process, an oxide film is deposited and isotropic in the same manner as in FIG. 2D. By etching through the etching method, the oxide film side walls 30 are formed on the side surfaces of the third wiring layer 10, respectively. At this time, the oxide film side wall 30 is formed by depositing the oxide film by a thickness of 500 kPa to 1000 kPa by plasma chemical vapor deposition at a temperature of 400 ° C., and then etching the oxide film by isotropic etching.

이후, 상기와 동일하게 측면에 산화막측벽이 형성된 배선층의 상부에 층간절연막 및 평탄화막을 형성한 후, 측면에 산화막측벽이 형성된 배선층을 형성하여 다층의 배선구조를 형성한다.Subsequently, an interlayer insulating film and a planarization film are formed on the upper side of the wiring layer on which the oxide film side wall is formed, and then a wiring layer having the oxide film side wall is formed on the side to form a multilayer wiring structure.

상기한 바와같이 제조되는 본 발명에 의한 반도체소자의 배선형성방법은 배선층의 측면에 산화막측벽을 형성하여 배선층의 급격한 단차를 완화하고, 배선사이의 이격거리가 협소한 곳의 플로잉(flowing)특성을 향상시켜 다층배선의 절연신뢰성을 향상시킬 수 있는 효과가 있다.The wiring forming method of the semiconductor device according to the present invention manufactured as described above forms an oxide film side wall on the side of the wiring layer to mitigate abrupt steps of the wiring layer, and the flow characteristic of the place where the separation distance between the wirings is narrow. This improves the insulation reliability of the multilayer wiring.

Claims (3)

소정거리 이격되어 제1배선층이 형성된 반도체기판의 상부전면에 제1절연막과 제1평탄화막을 차례로 증착하고, 그 제1평탄화막을 에치백하여 평탄화한 후, 상부전면에 제2절연막을 증착하는 단계와; 상기 제2절연막의 상부에 사진식각공정을 통해 소정거리 이격되도록 제2배선층을 형성한 후, 그 제2배선층의 측면에 각각 제1산화막측벽을 형성하는 단계와; 상기 제1산화막측벽이 형성된 제2배선층 및 제2절연막의 상부전면에 제3절연막과 제2평탄화막을 차례로 증착하고, 그 제2평탄화막을 에치백하여 평탄화한 후, 상부전면에 제4절연막을 증착하는 단계와; 상기 제4절연막의 상부에 사진식각공정을 통해 소정거리 이격되도록 제3배선층을 형성한 후, 그 제3배선층의 측면에 각각 제2산화막측벽을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체소자의 배선형성방법.Depositing a first insulating film and a first flattening film in order on the upper surface of the semiconductor substrate on which the first wiring layer is formed at a predetermined distance, and etching the planarized first flattening film, and then depositing a second insulating film on the upper surface; ; Forming a second wiring layer on the second insulating layer so as to be spaced apart by a predetermined distance through a photolithography process, and then forming first oxide side walls on the side surfaces of the second wiring layer; A third insulating film and a second flattening film are sequentially deposited on the upper surfaces of the second wiring layer and the second insulating film on which the first oxide film side wall is formed, and the second flattening film is etched back to planarize, and then a fourth insulating film is deposited on the upper front surface. Making a step; Forming a third wiring layer on the fourth insulating layer so as to be spaced apart by a predetermined distance through a photolithography process, and then forming second oxide sidewalls on the side surfaces of the third wiring layer, respectively. Formation method. 제 1항에 있어서, 상기 제1산화막측벽은 산화막을 400℃의 온도에서 플라즈마화학기상증착법으로 300Å∼500Å의 두께만큼 증착시킨후, 등방성 식각방식으로 식각하여 형성되는 것을 특징으로 하는 반도체소자의 배선형성방법.The semiconductor device wiring according to claim 1, wherein the first oxide film side wall is formed by depositing an oxide film at a temperature of 400 ° C. by a plasma chemical vapor deposition method and then etching it by an isotropic etching method. Formation method. 제 1항에 있어서, 상기 제2산화막측벽은 산화막을 400℃의 온도에서 플라즈마화학기상증착법으로 500Å∼1000Å의 두께만큼 증착시킨후, 등방성 식각방식으로 식각하여 형성되는 것을 특징으로 하는 반도체소자의 배선형성방법.2. The semiconductor device wiring according to claim 1, wherein the second oxide film side wall is formed by depositing an oxide film at a temperature of 400 ° C. by a plasma chemical vapor deposition method, and then etching it by an isotropic etching method. Formation method.
KR1019970054375A 1997-10-23 1997-10-23 Method for forming wire of semiconductor device Expired - Fee Related KR100253338B1 (en)

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