KR100252926B1 - Polysilicon thin-film transistor using silicide and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A polysilicon thin film transistor using a silicide and a fabrication method thereof are provided to simplify the fabrication process and to improve the process yield. CONSTITUTION: The transistor includes a polysilicon layer(11) formed on an insulating substrate(10), and a gate insulating layer(13) formed on a channel region of the polysilicon layer(11). In addition, a heavily doped semiconductor layer(16) is formed on the gate insulating layer(13) and an exposed portion of the polysilicon layer(11). Next, a nickel silicide layer(12) is formed on the heavily doped semiconductor layer(16) by sputtering. The heavily doped semiconductor layer(16) and the nickel silicide layer(12) constitute not only a gate electrode(14) on the gate insulating layer(13) but also a source/drain region(15) on the exposed portion of the polysilicon layer(11) in a self-aligned manner. The gate insulating layer(13) and the overlying semiconductor layer(16) prevent ion impurities from being implanted into the channel region in the polysilicon layer(11) without the formation of a typical ion stopper.

Description

Polysilicon Thin Film Transistor Using Silicide and Manufacturing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) and a method for manufacturing the same, and more particularly, to a polysilicon thin film transistor using a silicide and a method for manufacturing the same.

Among various kinds of metals capable of forming silicides, high melting point metals such as Mn, Ta, Ti, W, Cr, and quasi-noble metals such as Co, Ni, and Pd have been widely used. High quality silicides are simple to etch and form and have strong chemical bonds.

Hereinafter, a thin film transistor of the related art will be described with reference to the accompanying drawings.

In general, TFTs have been widely used as pixel elements in liquid crystal displays (LCDs) as driving elements or as switching elements in SRAMs. The structure of such a TFT is classified according to the arrangement of the active layer which is a semiconductor layer pattern.

Among them, a staggered type TFT has a structure in which a gate electrode and a source / drain electrode are positioned between semiconductor layers, and a coplanar type TFT has a gate electrode and a source / drain electrode located at one side of the semiconductor layer. It is formed into a structure.

3 is a cross-sectional view of a conventional staggered TFT.

The conventional staggered TFT has a source / drain electrode 15 formed at regular intervals on an insulating substrate, a highly doped semiconductor layer 16 formed on the source / drain electrode 15, and the high concentration. And a semiconductor layer 11 formed on the insulating substrate between the semiconductor layer 16 doped with the semiconductor layer and the heavily doped semiconductor layer and used as the channel region. The gate insulating layer 13 is formed on the semiconductor layer 11, and the gate electrode 14 is formed of a conductive material on a portion of the gate insulating layer 13 corresponding to the channel portion of the semiconductor layer 11. However, in the staggered TFT, since the highly doped semiconductor layer 15 is exposed to air, the conventional staggered TFT has a low yield.

4 is a cross-sectional view of an inverted staggered TFT proposed to solve the above problem.

The reverse staggered TFT includes a gate electrode 14 formed on the insulating substrate 10, a gate insulating film 13 formed on the entire surface of the structure, and a semiconductor layer formed on the gate insulating film 13 on the gate electrode 14. (11). The source / drain electrodes 14 are formed in contact with both sides of the semiconductor layer 11. The heavily doped semiconductor layer 16 is formed at the interface between the semiconductor layer 11 and the source / drain electrodes 15. This TFT structure is applicable to amorphous silicon TFTs.

5 is a cross-sectional view of a conventional coplanar TFT.

The conventional coplanar TFT is formed of a polysilicon on an insulating substrate 10 and an ion stopper formed of a silicon nitride film or an oxide film on a central portion of the semiconductor layer 11 and used as a channel. and a heavily doped semiconductor layer 16 formed on the semiconductor layer 11 on both sides of the ion stopper 17. The gate insulating film 13 of silicon oxide or nitride is formed on the entire surface and is removed so that a portion of the heavily doped semiconductor layer 16 is exposed. The gate electrode 14 is formed on the gate insulating film 13 on the ion stopper 17, and the source / drain electrodes 15 are exposed on both sides of the gate electrode 14, and the semiconductor layer 16 doped with high concentration is exposed. It is formed to contact with.

However, since the ion stopper 17 (nitride or oxide) is used as a mask in an individual ion implantation process, the conventional coplanar TFT has a low yield.

Such a thin film transistor of the prior art has the following problems.

Conventional staggered TFTs and ion stoppers, in which highly doped semiconductor layers are exposed to air, form coplanar TFTs used as masks in individual ion implantation processes and have low yields.

Thus, the process is complicated when the ion stopper is formed.

In addition, there is a limitation in solving the leakage current problem due to structural problems.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art thin film transistor, and to provide a polysilicon TFT having almost no additional capacitance and a method of manufacturing a TFT having a simple manufacturing process to improve the process yield.

1 is a scanning electron micrograph of the surface of nickel silicide according to a preferred embodiment of the present invention.

2 is a graph showing sheet resistance versus annealing temperature of a nickel silicide layer made of nickel deposited on ion-doped amorphous silicon in accordance with a preferred embodiment of the present invention.

3 is a cross-sectional view of a conventional staggered TFT.

4 is a cross-sectional view of an inverted staggered TFT.

5 is a cross-sectional view of a conventional coplanar TFT.

6 is a cross-sectional view of a polysilicon TFT using silicide according to a preferred embodiment of the present invention.

7a to 7b is a manufacturing process diagram of a polysilicon TFT using a silicide according to a preferred embodiment of the present invention.

8A to 8B show the transition and output characteristics of a laser annealed polysilicon TFT using silicide according to a preferred embodiment of the present invention, respectively.

9A to 9B show the transition and output characteristics of a laser-annealed polysilicon TFT using silicide according to a preferred embodiment of the present invention, respectively.

The polysilicon TFT using the silicide according to the present invention for achieving the above object is ion on the semiconductor layer on the gate insulating film and the semiconductor layer on both sides of the gate insulating film formed on a portion of the semiconductor used as a channel formed on the insulating substrate A silicide layer with low added capacitance and sheet resistance provided in place of an impurity semiconductor layer used as a contact layer formed by doping n-type ions (eg p ions) using a doping method, a gate electrode, And source / drain electrodes.

Another polysilicon TFT according to the present invention is a substrate; A polysilicon layer on the substrate; A gate insulating film on the semiconductor layer; A first silicide layer formed on the gate electrode and used as the gate electrode; And second and third silicide layers formed on semiconductor layers on both sides of the first silicide layer and used as source and drain electrodes.

A feature of the method for manufacturing a fully self-aligned planar polysilicon TFT according to the present invention includes forming a gate insulating film on a polysilicon layer on an insulating substrate; Forming an amorphous silicon layer on the gate insulating film; Selectively removing the amorphous silicon layer and the gate insulating film so that only one portion of each of the amorphous silicon layer and the gate insulating film is left in the channel region; Converting the amorphous silicon layer into a silicide layer; Converting a polysilicon layer used as a source and a drain on both sides of the gate insulating film into a silicide layer; And forming a gate electrode and a source / drain electrode of silicide.

A feature of the method for manufacturing a self-aligned planar polysilicon TFT according to the present invention includes forming a polysilicon layer on an insulating substrate; Forming a gate insulating film on the polysilicon layer; Forming an amorphous silicon layer on the gate insulating film; Selectively removing the amorphous silicon layer and the gate insulating film so as to remain only on the channel region; Converting the amorphous silicon layer into a silicide layer after ion showering to form a gate electrode; And converting the polysilicon layer on the side of the gate insulating film into a silicide layer to form source and drain electrodes.

Another aspect of the method for manufacturing a self-aligned planar polysilicon TFT according to the present invention includes the steps of: forming a first semiconductor layer on an insulating substrate; Forming a gate insulating film on the first semiconductor layer; Forming a second semiconductor layer on the gate insulating film; Patterning the gate insulating film and the second semiconductor layer to expose first and second side portions of the first semiconductor layer; Ion showering the first and second side portions of the first semiconductor layer and the second semiconductor layer; And forming a silicide layer on the first and second side surfaces of the first semiconductor layer and the gate insulating layer.

Hereinafter, a thin film transistor and a manufacturing process thereof according to the present invention will be described with reference to the accompanying drawings.

Among the metals forming the silicide, the quasi-noble metal forms silicide with M ₂ Si (where M represents a metal) at a lower temperature (˜200 ° C.) with more metal than silicon.

Nickel is particularly suitable as a material for forming a TFT electrode because nickel silicide forms a thin silicide layer that is thin and elongated with a small change in thickness throughout the surface, and provides a constant resistance value at any point. In particular, nickel forms low resistance silicides upon reaction with polysilicon.

Figure 1 shows a scanning electron micrograph of the surface of the nickel silicide prepared according to a preferred embodiment of the present invention.

The nickel silicide was ion showered with a P ion in the amount of 10 ¹⁷ -10 ¹⁸ on the substrate at a temperature of RF power of 15 W and 250 ° C., and a thickness of 100 μs for 15 seconds at a temperature of 200 ° C. Nickel is formed by RF sputtering and heat treatment at a temperature of 260 ° C. for 1 hour to deposit amorphous silicon up to a thickness of about 300 μs by plasma chemicla vapor (PCV) method.

As shown in the photograph, uniform silicide crystals are grown.

2 is a graph showing sheet resistance versus annealing temperature of a nickel silicide layer made of nickel deposited on ion-doped amorphous silicon in accordance with a preferred embodiment of the present invention. The annealing time is 1 hour in each case. The graph shows that even when the annealing temperature is about 200 ° C., even if the sheet resistance is about 50 mA / cm 2, the annealing temperature is about 230 ° C., but the sheet resistance rapidly drops below 5 kV / cm 2.

When the annealing temperature is 260 ° C., the sheet resistance is in the range of about 1 mA / cm 2. Extrapolation of this curve indicates that the sheet resistance is substantially constant even with higher annealing temperatures.

Therefore, nickel silicide can be applied to self-aligned polysilicon TFTs because nickel silicide has a low resistance electrode required for polysilicon TFTs.

6 is a cross-sectional view of a polysilicon TFT using silicide according to a preferred embodiment of the present invention.

As shown in Fig. 6, the polysilicon TFT is made of an insulating substrate 10 made of quartz or glass or a semiconductor layer 11 formed on an oxide film deposited on an insulating substrate, and a gate insulating film 13 made of an oxide film or a nitride film on the entire surface thereof. It includes. Here, the gate insulating layer 12 is partially removed to expose the silicon layer 11. The heavily doped semiconductor layer 16 is formed on the gate insulating film 13 and the exposed semiconductor layer 11.

The heavily doped semiconductor layer 16 and doped nickel silicide layer 12 constitute a gate electrode 14 on the source / drain electrode 15 and the gate insulating film 13 on the semiconductor layer 11, respectively.

In this embodiment, the gate insulating film 13 and the overlying semiconductor layer 16 prevent or prevent ion implantation into the channel region of the semiconductor layer 11. Therefore, it is possible to form a highly doped semiconductor layer 16 by implanting ions into the gate insulating film 13 and the semiconductor layer 11 on both sides of the gate insulating film 13 (this process is performed by the nickel silicide layer ( 12) before forming. This process eliminates the need for ion stoppers. Therefore, the polysilicon TFT according to the present invention does not require the step of forming an ion stopper since the additional semiconductor layer is formed on the gate insulating film and converted into the silicide layer.

In addition, the heavily doped semiconductor layer 16 and the doped nickel silicide layer 12 constituting the source / drain electrodes 15 are not formed over the entire thickness of the semiconductor layer 11 and are formed only at a partial depth of the upper portion to punch. Prevents device degradation due to troughs.

Further, since the gate electrode of the nickel silicide layer on the gate insulating film forms a self-aligned structure having a source / drain region, the manufacturing process of the TFT is simplified, and the production yield is increased.

7A to 7B illustrate a manufacturing process of a polysilicon TFT using silicide according to a preferred embodiment of the present invention.

As shown in FIG. 7A, the semiconductor layer 11 and the gate insulating film 13 are successively formed on the insulating substrate 10. Another semiconductor layer is formed on the gate insulating film 13. The gate insulating film 13 and the semiconductor layer on the gate insulating film are patterned together, and ion showering is performed so that the semiconductor is heavily doped on the semiconductor layer on the gate insulating film and the exposed semiconductor layer 16 on both sides of the gate insulating film 13. Form layer 16.

As shown in FIG. 7B, the nickel silicide layer 12 is RF-sputtered on the semiconductor layer 16 heavily doped with 30 ns of nickel, and the nickel silicide layer 12 is formed over the gate insulating layer 13 and the semiconductor layers on both sides of the gate insulating layer 13. It forms on (11).

In the sputtering, a 6N purity nickel target is heated for 20 minutes at a temperature of 200 ° C. under an initial vacuum of 3 × 10 ⁻⁶ Torr. The sputtering is performed for 5 seconds with 75W of RF power.

Subsequently, the material is heat-treated in an argon environment at a substrate temperature of 260 ° C. for 1 hour to form a nickel silicide layer 12. Residual nickel not reacted with silicon is removed with a mixture of HNO ₃ and HCL (1: 5 ratio).

FIG. 8 shows transition characteristics of a polysilicon TFT subjected to laser heat treatment using impurity nickel silicide according to a preferred embodiment of the present invention.

Polysilicon TFTs have a channel width / length of, for example, (39-79) μm / (13-33) μm. The threshold voltage and field effect mobility obtained at a drain voltage of 1V are 0.5V and 30.6cm 2 / Vs, respectively. The figure shows that the leakage current is about 10 ^-10 A and the on / off current ratio is 10 ⁶ or more.

8B is a graph showing output characteristics of a polysilicon TFT subjected to laser heat treatment using doped nickel silicide according to a preferred embodiment of the present invention. 8B shows no current crowding effect and kink effect when the drain voltage is low.

9A shows the transition characteristics of a solid crystallized polysilicon TFT using impurity nickel silicide according to a preferred embodiment of the present invention.

Polysilicon TFTs have a channel width / length of, for example, (39-79) μm / (13-33) μm. The figure shows that the leakage current is about 10 ⁻¹⁰ or less and the on / off current ratio is 10 ⁶ or more.

9B shows the output characteristics of the solid crystallized polysilicon TFT using impurity nickel silicide according to a preferred embodiment of the present invention. 9b indicates that there is no current crowding effect and kink effect even when the drain voltage is low.

The crystallized polysilicon TFT of the present invention has a field effect mobility of 9.6 cm 2 / Vs and a threshold voltage of 5.9 V. This value is calculated from the channel transconductance g _d according to the gate voltage obtained in the linear region of the output characteristic curve.

Such a polysilicon thin film transistor and a manufacturing method using the silicide according to the present invention has the following effects.

Since the gate electrode of the nickel silicide layer on the gate insulating film forms a self-aligned structure having a source / drain region, the TFT manufacturing process can be simplified, and the production yield can be increased.

In addition, the heavily doped semiconductor layers and the doped nickel silicide layers constituting the source / drain electrodes are not formed over the entire thickness of the semiconductor layer but are formed only at a partial depth of the upper portion to prevent device characteristics from being degraded by punch-through.

Another effect is to form a source / drain electrode with nickel silicide with a shallow junction structure to suppress the current crowding effect and the kink effect that occur when the drain voltage is low.

Claims (23)

Board; A polysilicon layer on the substrate; An insulating film on polysilicon; A gate electrode including a silicide layer on the insulating film; And a source and drain electrode comprising a highly doped semiconductor layer formed on a surface of the polysilicon layer on both sides of the gate electrode and spaced apart from the substrate, and a silicide layer formed on the semiconductor layer. . The polysilicon thin film transistor of claim 1, wherein the gate electrode is formed of silicide on amorphous silicon formed on the gate insulating film. The polysilicon thin film transistor according to claim 1, wherein the gate electrode is formed of silicide on doped amorphous silicon formed on the gate insulating film. Board; A polysilicon layer formed on the substrate; A gate insulating film formed on the polysilicon layer; A first silicide formed on the gate insulating film and used as a gate electrode; And second and third silicides respectively used as source and drain electrodes on the polysilicon layers on both sides of the first silicide. The polysilicon thin film transistor according to claim 4, wherein the silicide comprises Mn, Ti, W, Cr, Co, Pd or nickel silicide. 5. The polysilicon thin film transistor according to claim 4, wherein the channel between the source and drain electrodes has a width of 39-79 µm and a length of 13-33 µm. 5. The polysilicon thin film transistor according to claim 4, wherein the polysilicon thin film transistor has a leakage current of about 10 ^-10 A and an on / off current ratio of 10 ⁶ or more. Forming a polysilicon layer on the insulating substrate; Forming a gate insulating film on the polysilicon layer; Forming an amorphous silicon layer on the gate insulating film; Selectively removing the amorphous silicon layer and the gate insulating film so as to remain only in the channel region; Converting the amorphous silicon layer into silicide after ion showering to form a gate electrode; And forming a source and a drain electrode by changing the polysilicon layers on both sides of the gate insulating film to silicide. 10. The method of claim 8, wherein the polysilicon layer is annealed with a laser. The method of claim 8, wherein the polysilicon layer is a solid phase crystallization method of manufacturing self-aligned coplanar polysilicon thin film transistor. The method of claim 8, wherein the silicide comprises Mn, Ta, Ti, W, Cr, Co, Pd, or nickel silicide. 10. The method of claim 8, wherein the amorphous silicon layer is ion showered before the silicide is formed. 10. The method of claim 8, wherein an amorphous silicon layer on both sides of the gate insulating layer is doped before forming the silicide. The method of claim 8, wherein the gate insulating film is formed of a nitride film. The method of claim 8, wherein the channel is formed to have a width of about 59 μm and a length of about 23 μm. 10. The method of claim 8, wherein the polysilicon thin film transistor is formed to have a leakage current of 10 ^-10 or less and an on / off current ratio of 10 ⁶ or more. Forming a first semiconductor layer on an insulating substrate; Forming a gate insulating film on the first semiconductor layer; Forming a second semiconductor layer on the gate insulating film; Patterning the gate insulating film and the second semiconductor layer to expose first and second side portions of the first semiconductor substrate; Ion showering the first and second side portions and the second semiconductor layer of the first semiconductor layer; And forming a silicide layer on the first and second side surfaces of the gate insulating film and the first semiconductor layer. 18. The method of claim 17, wherein the polysilicon layer is heat treated with a laser. 18. The method of claim 17, wherein the polysilicon layer is solid crystallized. 18. The method of claim 17, wherein the silicide layer comprises Mn, Ta, Ti, W, Cr, Co, Pd, or nickel silicide. 18. The method of claim 17, wherein the gate insulating film is formed of a nitride film. 18. The method of claim 17, wherein the channel has a width of 39-79 μm and a length of 13-33 μm. 18. The method of claim 17, wherein the polysilicon thin film transistor is formed to have a leakage current of about 10 ^-10 and a current ratio of 10 ⁶ or more on / off. .