KR100257521B1 - Signal delay circuit of a semiconductor memory device - Google Patents

Abstract

PURPOSE: A signal delaying circuit of a semiconductor memory device is provided to control the internal signal delay even when the device is packaged. CONSTITUTION: The device includes plurality of signal delay(22), plurality of pull up devices(20), plurality of pull down devices, plurality of fuses, a fuse control signal generator and an enabling device(26). The signal delays are implemented between signal paths of the semiconductor memory device. The pull up devices are coupled with each input node of the signal delays and a source voltage and are operated with response to each of inverted fuse control signal. The pull down devices are coupled with each output node of the signal delays and a ground voltage and are operated with response to each of fuse control signal. The fuses are coupled between the input and output nodes of each of signal delay. The fuse control signal generator generates the plurality of fuse control signals and the inverted fuse control signals and generates a fuse cutting mode set up signal for setting up the fuse cutting mode. The enabler(26) enables the fuse cutting operation of signal paths with response to the fuse cutting mode set up signal.

Description

Signal delay circuit of semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a signal delay circuit of a semiconductor memory device capable of adjusting signal delay.

In recent years, semiconductor memory devices have become highly integrated and faster. Ultra-fast memory devices will now run at speeds of hundreds of MHz, and in the future, operating at speeds of gigabytes per second.

As the semiconductor memory device becomes faster, the operation cycle inside the chip is also faster, which makes it very difficult to control skew of the internal signals, and thus, the desired device can be obtained after several trials and errors. And cost increases. In addition, the test of the conventional semiconductor memory device was able to test even in the wafer state and did not make a big difference with the package state.

However, recent semiconductor memory devices add new interface logic that operates at high speed in addition to memory in the chip to realize ultra-high speed, and delayed lock (DLL) which is a clock skew compensation circuit to eliminate clock skew. loops or phase lock loops (PLLs) are built into the chip.

On the other hand, the operating speed of the memory test circuit is about 100MHz-250MHz, and is useful for testing only the memory device. The interface logic and the operation characteristics of the DLL or PLL cannot be verified in the wafer state.

In addition, memory devices operating at speeds of hundreds of megabytes per second have very small specification values, which require even more sophisticated control of the signals in the chip and can only be checked in the finished state of the package.

And, it is very difficult to control the signal in the chip for the same reason as above. Therefore, in order to obtain a good sample of the high speed memory device according to the conventional method, wafer-> package assembly-> primary characteristic verification-> correction-> package assembly-> secondary characteristic verification-> correction-> package assembly-> 3 As the method of verifying the difference characteristics has to be repeated several times, the cause of cost increase and development period is increased.

1 is a diagram illustrating an example of a signal delay circuit of a conventional semiconductor memory device, and includes PMOS transistors P1 and P2, NMOS transistors N1 and N2, a delay circuit 10, and a fuse f. . Delay circuit 10 generally consists of a resistor or capacitance.

The conventional signal delay circuit has a disadvantage in that package characteristics cannot be guaranteed regardless of the package state characteristics of the memory device by selecting a method of cutting the fuse f with a laser cutter in a wafer state before package assembly. That is, if a signal delay is required, the fuse f may be cut by a laser cutting machine to be a signal delay by the delay circuit 10, and when the signal delay is not necessary, the fuse f may be left uncut.

Since the signal delay circuit of the conventional semiconductor memory device is a signal delay adjustment method in a wafer state, when the characteristic is changed after assembling the package, the semiconductor memory device having the desired characteristic can be obtained by repeating several trials and errors. There was a problem of increasing the cost and increasing the development period.

An object of the present invention is to provide a signal delay circuit of a semiconductor memory device capable of controlling a signal delay in a chip in a package state.

The signal delay circuit of the semiconductor memory device of the present invention for achieving the above object is connected between a plurality of signal delay means between the signal lines of the semiconductor memory device, each input terminal of the plurality of signal delay means and the power supply voltage A plurality of pull-up means which are turned on in response to each inverted fuse control signal, a plurality of pull-down means which are connected between an output terminal of each of the plurality of delay means and a ground voltage and turned on in response to each fuse control signal, A fuse for generating a plurality of fuses connected between respective input / output terminals of the plurality of signal delay means, the plurality of fuse control signals and an inverted fuse control signal, and a fuse cutting mode setting signal for setting a fuse cutting mode; A control signal generating means, and the semiconductor in response to the fuse cutting mode setting signal; It characterized in that it includes the enabling means for enabling the fuse cutting operation of the signal line of the memory device.

1 is an embodiment of a signal delay circuit of a conventional semiconductor memory device.

2 is an embodiment of a signal delay control circuit of the semiconductor memory device of the present invention.

3 is an embodiment of a signal delay circuit of the semiconductor memory device of the present invention.

Hereinafter, a signal delay circuit of a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

2 is an embodiment of a signal delay control circuit of the semiconductor memory device of the present invention, in which an inverter 22 for inverting the reference voltage Vref and n bus data are enabled in response to an output signal of the inverter 22. N parallel-connected flip-flops 20 for storing and outputting (D1 -Dn) in parallel, and inverted fuse control by inverting fuse control signals f1 -fn that are output signals of the flip-flops 20 Inverting circuit 24 composed of n parallel-connected inverters for outputting signals fb1-fbn and fuse control mode f1-fn, fb1-fbn by inputting and ORing the fuse cutting mode signal FM Is composed of a logical sum circuit 26 for outputting

2 is a circuit for controlling the cutting of the n fuses in the memory chip and distinguishing the normal mode from the fuse cutting mode. The reference voltage Vref is a voltage that is necessarily used in interface logic for implementing a high speed interface and always has a random voltage greater than 0V. Since the flip-flop 20 of the control circuit shown in FIG. 2 operates only when the reference voltage Vref is 0 V, the control circuit does not operate when the semiconductor memory device operates in the normal mode.

In addition, any n pins among the package pins can be selected to select n fuses in the chip, and these signals can be used to selectively cut the desired fuses. That is, n data input to the flip-flop 20 is data input from any n pins. The data input to these arbitrary pins are set to the "low" level in the fuse cutting mode, so that the normal mode and the fuse cutting mode can be distinguished. When the reference voltage Vref is 0V, the flip-flop 20 is enabled, and at this time, the data D1 -Dn are stored and output. The output signal of the flip-flop 20 becomes the fuse control signal f1 -fn and the inversion circuit 24 inverts these fuse control signals f1 -fn to output the inverted fuse control signals fb1 -fbn. . That is, the control circuit shown in FIG. 2 can easily distinguish between the normal mode and the fuse cutting mode through the reference voltage Vref and an arbitrary pin, thereby preventing malfunction in the normal mode.

3 is a diagram illustrating a signal delay circuit of a semiconductor memory device according to an embodiment of the present invention, wherein a PMOS transistor P3 having a gate electrode to which a fuse cutting mode signal FM is applied and a source electrode to which a power supply voltage is applied, and a fuse cutting mode signal are illustrated in FIG. An inverter 30 for inverting the FM, a PMOS transistor P4 having a gate electrode to which the input signal IN is applied, a source electrode connected to the drain electrode of the PMOS transistor P3, and an input signal IN are applied. NMOS transistor N3 having a gate electrode and a drain electrode connected to the drain electrode of the PMOS transistor P4, a drain electrode connected to the source electrode of the NMOS transistor N3, a gate electrode to which an output signal of the inverter 30 is applied, and ground N series transistors N4 having a source electrode to which voltage is applied, n series connected delay circuits 40-n, 40- (n-1) for delaying a signal from the drain electrode of the PMOS transistor P4, . ... 40-1, fuses 50-n, 50- (n-1), ..., 50-1 connected between respective input / output terminals of delay circuits, each of supply voltage and delay circuits PMOS transistors P5-n, P5- (n-1) connected between the input terminals and turned on in response to respective inverted fuse control signals fbn, fb (n-1), ..., fb1, ..., P5-1), which is connected between the respective output terminal of the delay circuits and the ground voltage and is turned on in response to the respective fuse control signals fn, f (n-1), ..., f1. PMOS transistors P6 for inputting and inverting the final output signals of the NMOS transistors N5-n, N5- (n-1), ..., N5-1, and delay circuits to generate an output signal OUT. ) And an NMOS transistor (N6).

In the fuse cutting mode, the fuse cutting mode signal FM is at the "high" level, and in the normal mode, the fuse cutting mode signal FM is maintained at the "low" level. Therefore, when the fuse cutting mode signal FM is at the "high" level, the PMOS transistor P3 and the NMOS transistor N4 are turned off, respectively, and thus the input of the input signal IN is disabled. Then, the fuse control signals fn, f (n-1), ..., f1 generated by the combination of the data signals shown in FIG. 2 are all "high" level and the inverted fuse control signals fbn, fb If (n-1), ..., f1) are all at "low" levels, the PMOS transistors P5-n, P5- (n-1), ..., P5-1 and NMOS transistors N5- n, N5- (n-1), ..., N5-1) are all turned on. At this time, the current flowing through the PMOS transistor P5-n flows into the delay circuit 40-n and the fuse 50-n, and the current is summed through the NMOS transistor N5-n. At this time, since the resistance value of the fuse 50-n is small, all current flowing through the PMOS transistor P5-n flows through the fuse f1. That is, the fuse 50-n is cut off by the current flowing through the fuse 50-n.

Here, the manufacturing method of the fuse, the capacity of the fuse, the cutting voltage and the cutting current may be referred to the contents disclosed in US Pat. No. 5,420,456 or US Pat. No. 4,089,734 as prior art, in the case of the present embodiment The fuse is made of polysilicon material having a width of 0.4 mu m and a length of 8 mu m or less, the kitting voltage is applied as 5 volts, and the current is 10 mA milliamps. In addition, since the cutting voltage and current depend on the thickness and thermal resistance of the semiconductor substrate, the thickness of the oxide film, and the melting point of the fuse material, the cutting voltage and the current should be set in consideration of the change of the case.

In this manner, in the normal mode operation, the input signal is delayed through the delay circuit 40-n. In this way, if all the fuses 50- (n-1), ..., 50-1 are blown, the input signal may be delayed by the delay circuits 40-n and 40- (n-1) in the normal mode operation. ), ..., 40-1) will be delayed as much as possible. The adjustment of the signal delay time may be adjusted according to the number of fuses blown out of the n fuses 50-n, 50-(n-1), ..., 50-1. That is, the signal delay time is adjusted depending on how many of the data signals in Fig. 2 are set to the "high" level.

Accordingly, the present invention can secure a good sample without correcting the setup / hold time in not only a normal memory device but also a high-speed memory device by selectively cutting a desired fuse with a combination of external pins in a package state. It can reduce the time and cost.

Therefore, the signal delay circuit of the semiconductor memory device of the present invention can adjust the signal delay time in the chip in the package state, thereby reducing the development period and reducing the cost.

Claims (4)

A plurality of signal delay means between signal lines of the semiconductor memory device; A plurality of pull-up means connected between each input terminal of the plurality of signal delay means and a power supply voltage and driven in response to each inverted fuse control signal; A plurality of pull-down means connected between each output terminal of the plurality of delay means and a ground voltage and driven in response to respective fuse control signals; A plurality of current cuttable fuses connected between input / output terminals of the plurality of signal delay means; A fuse control signal generating means for generating said plurality of fuse control signals and inverted fuse control signals and for generating a fuse cutting mode setting signal for setting a fuse cutting mode; And enable means for enabling a fuse cutting operation of signal lines of the semiconductor memory device in response to the fuse cutting mode setting signal. 2. The apparatus of claim 1, wherein the fuse control signal generating means is enabled in response to a reference voltage signal and connected in parallel to store data input from a plurality of external pins in parallel and output a plurality of fuse control signals. Flip-flops; Inverting means for inverting the plurality of fuse control signals to generate a plurality of inverted fuse control signals; And logic summation means for generating the fuse cutting mode setting signal by ORing the plurality of fuse control signals and the inverted fuse control signals. The signal delay circuit of claim 1, wherein each of the plurality of pull-up means comprises a PMOS transistor. 2. The signal delay circuit of claim 1, wherein each of the plurality of pull-down means consists of an NMOS transistor.

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