KR100247957B1 - Iir filter using serial-parallel multiplier - Google Patents

Abstract

An IIR filter is provided that uses a serial / parallel multiplier that can reduce the size of the entire hardware by using a parallel / multiplier that is faster than a serial multiplier and smaller than a parallel multiplier. The IIR filter using the serial-to-parallel multiplier according to the present invention inputs an input, an intermediate output, and a final output to output current inputs, inputs before a predetermined clock, intermediate outputs, intermediate outputs before a predetermined clock, final outputs, and final outputs before a predetermined clock. A register array for outputting, a first multiplexer for selecting and outputting one of the outputs of the register array, a second multiplexer for selecting and outputting one of a plurality of input filter coefficients, and an output of the first multiplexer; A serial-to-parallel multiplier for outputting an upper bit in parallel and outputting a lower bit in series by multiplying a first shift register to be output in series, an output of the first shift register, and an output of the second multiplexer; Second shift register and phase for outputting in parallel by inputting the lower bit output serially output from There is an advantage in accumulating a lower-bit output that is output in parallel from the serial-parallel multiplier and outputting the upper bits and the second shift register to be output in parallel by comprising an accumulator which outputs the final output and the intermediate output.

Description

IIR Filter Using Serial Parallel Multiplier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital filters, and more particularly, to an IIR filter using a serial / parallel multiplier that can reduce the size of hardware using a serial / multiple multiplier.

FIG. 1 shows a fourth-order infinite impulse response (IRR) filter in which a second-order filter is configured in series. In the fourth-order IIR filter of FIG. 1, the first filter 10 and the second filter 12 are connected in series to operate as a fourth-order IIF filter.

In general, a digital filter is represented by an N-order difference equation as in Equation 1.

As described above, the output y (n) is determined by the linear combination of the present and past inputs with the past outputs, and the coefficients a _k and b _k dominate the characteristics of the digital filter. Therefore, in the case of the second-order digital filter, Equation 1 is equal to Equation 2.

Accordingly, the first filter 10 and the second filter 12 of FIG. 1 may include an adder 20, four delay elements 21, 22, 23, 24, and five coefficient multipliers 25 and 26, as shown in FIG. , 27, 28), and using this, the fourth-order IIR filter of FIG. 1 can be added to the adder 30, 31, delay elements 32, 33, 34, 35, 36, 37, and coefficients as shown in FIG. The multipliers 38, 39, 40, 41, 42, 43, 44, 45, 46, 47 can be configured.

4 shows a fourth-order IIR filter using a conventional parallel multiplier based on the configuration of FIG. 3. The fourth-order IIR filter using the parallel multiplier shown in FIG. 3 inputs the intermediate output y ₁ (n) and the input x (n) and the final output y (n) to the current input (x (n). )), The input of one clock (x ₁ ), the input of two clocks (x ₂ ), the intermediate output (y ₁ (n)), the intermediate output of one clock (y _{1_1} ), the intermediate output of two clocks before (y _{2_1} ) Any one of a register array 50 for outputting a final output y (n), a final output y _{1_1 of} one clock, a final output y _{2_2 of} two clocks, and an output of the register array 50 Selects and outputs the first multiplexer 52 and the filter coefficients (a _{0_1} , a _{1_1} , a _{2_1} , b _{1_1} , b _{2_1} , a _{0_2} , a _{1_2} , a _{2_2} , b _{1_2} , b _{2_2} ) The second multiplexer 54 which selects and outputs one of the outputs, the parallel multiplier 56 for inputting and multiplying the outputs of the first multiplexer 52 and the second multiplexer 54, and the parallel multiplier 56 Input is accumulated by accumulating output and intermediate output (y (n)) The accumulator 58 which outputs the force y ₁ (n) is provided. Here, the final output y (n) and the intermediate output y ₁ (n) output from the accumulator 58 are input to the register array 50 again.

The fourth-order IIR filter using the conventional parallel multiplier configured as described above performs multiplication by dividing time by using the first and second multiplexers 52 and 54 to implement a filter function with one multiplier. N-bit data output from the first and second multiplexers 52 and 54 are respectively multiplied in parallel using the parallel multiplier 56, and then accumulated in the accumulator 58 to output a final output y (n). .

However, since the fourth-order IIR filter using the conventional parallel multiplier as described above uses a parallel multiplier, the operation speed is very fast, but the size of the hardware increases, which is disadvantageous in integration.

An object of the present invention is to provide an IIR filter using a serial / parallel multiplier that can reduce the size of the entire hardware by using a serial / multiplier that is faster than a serial multiplier and smaller in size than a parallel multiplier.

1 is a block diagram illustrating a typical fourth-order IIR filter composed of secondary filters.

2 is a detailed view of a second order IIR filter.

3 is a detailed view of the fourth-order IIR filter shown in FIG. 1.

4 is a block diagram of a fourth-order IIR filter using a conventional parallel multiplier.

5 is a block diagram of a fourth-order IIR filter using a series-parallel multiplier according to an embodiment of the present invention.

6 shows a 4-bit serial-to-parallel multiplier.

<Explanation of symbols for main parts of drawing>

60 ... register array, 62 ... first multiplexer,

64 ... second multiplexer, 66 ... first shift register,

68 ... parallel multiplier, 70 ... second shift register,

72 ... accumulator.

In order to achieve the above object, the IIR filter using a serial-to-parallel multiplier according to the present invention,

A register array configured to input an input, an intermediate output, and a final output to output a current input, inputs before a predetermined clock, intermediate outputs, intermediate outputs before a predetermined clock, final output, and final outputs before a predetermined clock;

A first multiplexer for selecting and outputting one of the outputs of the register array;

A second multiplexer which selects and outputs one of a plurality of input filter coefficients;

A first shift register configured to input an output of the first multiplexer and output in series;

A serial / multiplier for outputting the upper bits in parallel and outputting the lower bits in series by multiplying the output of the first shift register with the output of the second multiplexer;

A second shift register configured to input a lower bit output serially output from the serial / multiplier and output in parallel; And

And an accumulator configured to accumulate an upper bit output output in parallel from the serial / parallel multiplier and a lower bit output output in parallel from the second shift register and output the final output and the intermediate output.

Hereinafter, a preferred embodiment of an IIR filter using a series-parallel multiplier according to the present invention will be described with reference to the accompanying drawings.

5 is a block diagram of a fourth-order IIR filter using a series-parallel multiplier according to an embodiment of the present invention.

The fourth-order IIR filter using the serial-to-parallel multiplier shown in FIG. 5 implements a fourth-order IIR filter in which a second-order IIR filter of FIG. Assume that

In the fourth-order IIR filter using the series-parallel multiplier of FIG. 5, the input (x (n)), the intermediate output (y ₁ (n)), and the final output (y (n)) are inputted to the current input (x (n)). ), Inputs 1 and 2 clocks (x ₁ , x ₂ ), intermediate outputs y ₁ (n), intermediate outputs (y _{1_1} and y _{2_1} ), 1 and 2 clocks, and final output (y ( n)), a register array 60 that outputs the final outputs y _{1_2} and y _{2_2 of} one clock and two clocks, and a first multiplexer 62 that selects and outputs one of the outputs of the register array 60. And a second multiplexer for selecting and outputting one of a plurality of input filter coefficients (a _{0_1} , a _{1_1} , a _{2_1} , b _{1_1} , b _{2_1} , a _{0_2} , a _{1_2} , a _{2_2} , b _{1_2} , b _{2_2} ) 64, the first shift register 66 for inputting and outputting the output of the first multiplexer 62, the output of the first shift register 66, and the output of the second multiplexer 64 to multiply. Output bits in parallel and lower bits in serial Is an upper parallel output from the parallel shift multiplier 68 and the second shift register 70 and the parallel parallel multiplier 68 to input and output the lower bit output serially output from the serial parallel multiplier 68 and in parallel An accumulator for outputting the final output y (n) and the intermediate output y ₁ (n) by inputting and accumulating the bit output and the lower bit output output in parallel from the second shift register 70 is provided. Here, the final output y (n) and the intermediate output y ₁ (n) output from the accumulator 72 are input to the register array 60 again.

The fourth-order IIR filter using the serial-to-parallel multiplier according to the embodiment of the present invention configured as described above uses a first and second multiplexers 62 and 64 to implement a filter function with one serial-to-parallel multiplier. The input / output data and the coefficients are multiplied, and the N-bit data output from the first multiplexer 62 is input to the first shift register 66 and the first shift register 66 is connected to the serial / multiplier 68. Outputs N bit data serially one bit at a time. In addition, the N-bit coefficient data output from the second multiplexer 64 is input to the serial-parallel multiplier 68, and the serial-multiplier 68 multiplies the data input in parallel with the data input in series and multiplies the result. The upper bits of are output to the accumulator 72, and the lower bits of the multiplication result are output to the second shift register 70 by one bit in series. The second shift register 70 outputs the lower bits of the multiplication result input in series in parallel. The accumulator 72 outputs the final output y (n) and the intermediate output y ₁ (n) by continuously accumulating by inputting the upper and lower bits of the multiplication result.

Referring to FIG. 3, when the upper bit output of the serial and multiplier 68 and the lower bit output of the second shift register 70 are added five times in the accumulator 72, the final output y (n) and the intermediate output ( It can be seen that y ₁ (n)) is made.

As shown in Fig. 3, x ₁ and x ₂ are inputs of one and two clocks (x (n)), and y _{1_1} and y _{2_1} are intermediate outputs of one and two clocks (y ₁ (n)). y _{1_2} and y _{2_2} are the final output y (n) of one clock and two clocks. Therefore, it can be seen that the accumulator 72 only needs to make the final output y (n) and the intermediate output y ₁ (n). On the other hand, the final output y (n) and the intermediate output y ₁ (n) which are the outputs of the accumulator 72 are applied to the register array 60. The register array 60 inputs the final output (y (n)) and the intermediate output (y ₁ (n)) and the input (x (n)) so that the final outputs of one clock and two clocks (y _{1_2} , y _{2_2).} ), The middle outputs (y _{1_1} , y _{2_1} ) of one clock and two clocks, and the inputs (x ₁ , x ₂ ) of _one and two clocks.

Meanwhile, FIG. 6 shows a 4-bit serial-to-parallel multiplier. The four-bit serial-and-parallel multiplier of FIG. 6 includes a NAND gate 80, three AND gates 81, 82, 83, NAND gate 80, and four exclusive or gates 84, 85, 86, 87. , Six latches 88, 89, 90, 91, 92, 93, six adders 94, 95, 96, 97, 98, 99, and inverter 100, which are multiplied by adder 96. The lower bits of the result are output in series, and the upper bits of the multiplied result are output in parallel in the inverter 100 and the adders 97, 98, and 99.

The 4-bit serial-to-parallel multiplier of FIG. 6 uses Baugh-Wooley's algorithm, which is equal to Equation 3 when the algorithm is applied to multiplication of 4-bit 2's complement data.

In Equation 3 below, the above three columns may include one NAND gate and three AND gates, and the fourth column may include one AND gate and three NAND gates. Therefore, as shown in FIG. 6, the control signal QS is adjusted to operate as one NAND gate and three AND gates when the control signal QS is 0, and when the control signal QS is 1, the control signal QS is adjusted. It can be operated with an AND gate and three NAND gates.

Upper 4 bits lower 4 bits

In Fig. 6, the latches 91, 92 and 93 are for storing carry of the adders 94, 95 and 96, respectively, and P7 P6 P5 which is the upper 4 bits in the inverter 100 and the adders 97, 98 and 99. P4 is output, and the adder 96 outputs the lower four bits P0 P1 P2 P3 one by one.

As described above, the IIR filter using the serial / parallel multiplier according to the present invention has an advantage of reducing the hardware size of the entire IIR filter by using the parallel / multiplier that is faster than the serial multiplier and smaller than the parallel multiplier.

Claims (1)

A register array configured to input an input, an intermediate output, and a final output to output a current input, inputs before a predetermined clock, intermediate outputs, intermediate outputs before a predetermined clock, final output, and final outputs before a predetermined clock; A first multiplexer for selecting and outputting one of the outputs of the register array; A second multiplexer which selects and outputs one of a plurality of input filter coefficients; A first shift register configured to input an output of the first multiplexer and output in series; A serial / multiplier for outputting the upper bits in parallel and outputting the lower bits in series by multiplying the output of the first shift register with the output of the second multiplexer; A second shift register configured to input a lower bit output serially output from the serial / multiplier and output in parallel; And And an accumulator configured to accumulate an upper bit output that is output in parallel and the lower bit output that is output in parallel in the second shift register and output the final output and the intermediate output. IIR filter using.

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