KR100239845B1 - Semiconductor integrated circuit - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit in which the pitch of the wiring channel grating is improved, the wiring width is set according to the type of wiring to be formed, and the degree of integration is improved without causing unsuitable circuit operation. do. According to the present invention, a plurality of gate basic cells 3a and 3b are arranged on a semiconductor chip, and wiring channel gratings X0 to X11 and Y0 to Y6 are defined on the basic gate cells 3a and 3b to arrange the gate basics. By connecting the cells 3a and 3b along the wiring channel gratings X0 to X11 and Y0 to Y6, in the master slice type semiconductor integrated circuit constituting the logic functional block, the wiring channel gratings X0 to X11 and Y0 to Y6) is defined and composed of non-uniform pitch.

Description

Semiconductor integrated circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit combining a plurality of gate basic cells to form a desired logic circuit, and more particularly, to a semiconductor integrated circuit aimed at improving wiring channel gratings.

In general, an example of a basic cell layout of this kind of semiconductor integrated circuit is shown in FIG.

The layout of the gate base cell shown in Fig. 19 is, for example, a pair of two NMOS transistors 1a and 1b and two PMOS transistors 2a and 2b required to form a two-input NAND gate. Two gate basic cells 3a and 3b and a pair of sub straights 4a and 4b are arranged. In Fig. 19, the wiring channel gratings on which the wirings are formed are defined, for example, 12 of X0 to X11 in the X direction and 7 of Y0 to Y6 in the Y direction.

The layout of the gate base cell in which the wiring channel lattice is defined in this way is, for example, as shown in the functional block layout pattern of FIG. NAND gates Z of four inputs A, B, C, and D are connected by connecting and wiring the respective transistors 1a, lb, 2a, and 2b using the lower power supply wiring 5b and the connection wiring 6. Output) is built.

In the layout of the gate base cell, the pitch of the wiring channel grating was defined uniformly in the value of uniformity or in the X-direction Y direction, with emphasis on consistency with layout CAD. The design value of the pitch of the wiring channel grating was determined by the logical product of the design criteria in the region in which the functional block is formed or the wiring region. As the miniaturization progressed, the pitch of the wiring channel grating was narrowed.

On the other hand, in the technical field of semiconductor integrated circuits, the development of LSI has reached the area called the deep sub-micron generation and the quarter sub-micron generation by the advance of the microfabrication technology. In these generations, the detrimental factors due to miniaturization are remarkable, and in particular, in miniaturization of power supply metal wiring, generation of electromigration and increase in wiring resistance cause a source voltage drop of the transistor inside the chip, which adversely affects device operation. There is concern.

In addition, as the contact diameter becomes smaller, the contact resistance increases, causing a source voltage drop of the transistor as described above, which adversely affects the operation speed of the device. For this reason, miniaturization of power supply metal wiring has reached its limit. The progress of miniaturization excluding the power supply metal wiring, that is, the wiring channel grating of the same uniform pitch as in the prior art has become difficult to improve the degree of integration.

As described above, in the conventional semiconductor integrated circuit in which a desired circuit is constructed by using a gate base cell connected by a wiring formed along the wiring channel grating, the pitch of the wiring channel grating is uniformly set. For this reason, in order to increase the degree of integration, it is necessary to narrow the pitch of the wiring channel grating. However, when the pitch of the wiring channel lattice is uniformly narrowed, the width of the power supply wiring and the wiring through which a large current flows must also be narrowed. In this way, when the width of the wiring is uniformly narrowed, a drop in the source voltage, a wiring defect, or the like occurs, resulting in an inadequate malfunction or a decrease in the operation speed.

The present invention for solving the above problems is to improve the pitch setting of the wiring channel grating, and to set the wiring width according to the type of wiring to be formed, thereby improving the degree of integration without causing unsuitable circuit operation. The present invention provides a semiconductor integrated circuit.

1 is a diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the invention described in claim 1;

FIG. 2 illustrates the functional block layout pattern of FIG. 1; FIG.

3 is a diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the invention as claimed in claim 2 or 3.

4 illustrates the functional block layout pattern of FIG.

Fig. 5 shows the structure of a semiconductor integrated circuit according to an embodiment of the invention as claimed in claim 4;

FIG. 6 illustrates the functional block layout pattern of FIG. 5; FIG.

FIG. 7 illustrates a functional block layout pattern in which FIG. 5 is flipped; FIG.

Fig. 8 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention as claimed in claim 5;

FIG. 9 illustrates the functional block layout pattern of FIG. 8; FIG.

Fig. 10 is a diagram showing a functional block layout pattern in which Fig. 8 is flipped.

Fig. 11 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention as claimed in claim 6;

Fig. 12 is a diagram showing the configuration of a semiconductor integrated circuit according to another embodiment of the invention as set forth in claim 2;

FIG. 13 is a view showing a wiring layout pattern of FIG. 12; FIG.

FIG. 14 shows the functional block layout pattern of FIG. 12; FIG.

FIG. 15 shows the functional block layout and the wiring layout pattern of FIG. 12; FIG.

FIG. 16 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention as claimed in claim 7.

FIG. 17 illustrates the functional block layout pattern of FIG. 16; FIG.

FIG. 18 shows the wiring layout pattern in FIG. 17; FIG.

Fig. 19 shows a layout pattern of a conventional gate basic cell using a wiring channel grating.

FIG. 20 illustrates the functional block layout pattern of FIG. 19; FIG.

* Explanation of symbols for main parts of the drawings

1a, 1b, 2a, 2b: MOS transistors 3a, 3b: gate base cell

4a, 4b: Sub straight 5a, 5b: Power wiring

6 connection wiring 7 contact hole

8: special signal wiring 9: power supply wiring

11: polysilicon 12: source and drain region

13: gate pulley

In order to achieve the above object, the invention described in claim 1 is characterized by arranging a plurality of gate basic cells on a semiconductor chip, and defining a wiring channel grating on the basic gate cells, In a master slice type semiconductor integrated circuit in which desired logic functional blocks are formed only by changing wiring processes by connecting along wiring channel gratings, the wiring channel gratings are defined at non-uniform pitches in accordance with the gate basic cell structure.

In the semiconductor integrated circuit according to claim 1, in the semiconductor integrated circuit according to claim 1, the wiring channel lattice in which the high power wiring or the lower power wiring is provided among the wiring channel lattice is the high power wiring or the low power. The pitch is set to be wider than that of the wiring channel grating where other wirings than the power supply wiring are provided.

In the semiconductor integrated circuit according to claim 3, the invention described in claim 3 is characterized in that, in the semiconductor integrated circuit according to claim 2, the high power supply wiring or the low power supply wiring has a plurality of minimum contact holes or a plurality of contacts having a minimum contact hole. It is characterized by the wiring width which can arrange | position a hole.

The invention as recited in claim 4 is the semiconductor integrated circuit according to claim 1, wherein the wiring channel lattice, which is defined by a nonuniform pitch, is provided with respect to the X direction or the Y direction of the gate basic cell. It is characterized by the object.

In the semiconductor integrated circuit according to claim 5, in the semiconductor integrated circuit according to claim 5, the high power supply wiring or the low power supply wiring is formed so that the center of the wiring width is out of the wiring channel grating.

According to the invention as claimed in claim 6, in the semiconductor integrated circuit according to claim 2, the wiring channel lattice in which the pitch is set wide is a wiring channel other than the high power wiring or the low power wiring. When used as an area, it becomes a wiring channel grating of special signal wiring.

According to the invention as recited in claim 7, the wiring channel grating having a wide pitch in the semiconductor integrated circuit according to claim 2 is a wiring channel other than the high power wiring or the low power wiring. When using as an area | region, it becomes a wiring channel grating of several line wiring.

According to the invention of claim 8, a plurality of gate basic cells are arranged on a semiconductor chip, a plurality of functional blocks are arranged on the gate basic cell, and a wiring channel grating is formed between the functional blocks and on the functional blocks. In a semiconductor slice circuit of a master slice type in which a prescribed wiring area is provided and the arranged functional blocks are connected along the wiring channel lattice to form a desired logic circuit only by changing the wiring process, the wiring channel lattice is nonuniform. It is defined by one pitch.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

1 is a diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the invention as set forth in claim 1 or 8.

FIG. 1 is a view showing a layout of a gate basic cell as shown in FIG. 19. In FIG. 1, the same reference numerals as those in FIG.

When designing the pitch of the wiring channel grating, it can be divided into two cases. That is, in the first case, it is preferable to consider design criteria of the wiring process, for example, wiring width and wiring interval, contact hole diameter and contact hole spacing, via hole contact diameter and via hole contact spacing in the multilayer wiring. . The second case is to consider the design criteria of the diffusion process in addition to the former design criteria.

In the layout of the gate basic cell shown in Fig. 1, in order to define the pitches of the wiring channel lattices Xl to X2 to X3 to X4 and X7 to X8 to X9 to X10, only the design criteria of the wiring process need to be considered. 1 case.

On the other hand, in order to define the pitch of the wiring channel lattice X0 to X1, X4 to X5, X6 to X7, and X10 to X11, the poly 11 and the contact margin, the poly 11 and the source / drain region 12, the spacing and the source Consider the design criteria of the drain area 12 and the contact clearance. In order to define the pitch of the wiring channel gratings X5 to X6 and X11 to X0, the design criteria of the poly 11 and the contact clearance or the spacing of the poly 11 should be considered. In order to define the pitches of the wiring channel gratings Y0 to Y1 to Y2 and Y4 to Y5 to Y6, the design criteria of the gate poly 13 and the contact spacing or the gate poly 13 width should be considered. In order to define the pitch of the wiring channel gratings Y2 to Y3 to Y4, the design criteria of the spacing between the source and drain regions 12 and the sub straights 4a and 4b should be taken into consideration. In order to define the pitch of the wiring channel gratings Y6 to Y0, the design criteria of the source / drain region 12 spacing should be considered. These design rules need to be considered in addition to the design criteria of the wiring process in the first case, which is the second case described above.

In general, since the design criteria of the diffusion process are more accurate than the design criteria of the wiring process, the pitch and wiring of the wiring channel lattice X0 to X1, X4 to X5, X5 to X6, X6 to X7, X10 to X11, and X11 to X0 The pitch in the Y direction of the channel grating should take into account the design criteria of the diffusion process. Therefore, the design criteria of the diffusion process should be set wider than the pitches of the wiring channel gratings X1 to X2 to X3 to X4 and X7 to X8 to X9 to X10. Therefore, when uniformly defining the pitch of the wiring channel grating, the design criteria of the diffusion process are defined where the wiring channel grating pitch is the largest.

In the current semiconductor manufacturing technology, the difference between the design criterion of the wiring process and the design criterion of the diffusion process is remarkable. That is, even if the pitch of the wiring channel gratings is uniform, the pitches of the wiring channel gratings X1 to X2 to X3 to X4 and X7 to X8 to X9 to X10 can be narrowed. Since the pitches of -Y2 and Y4-Y5-Y6 must be increased, the pitches of the wiring channel lattice X1-X2-X3-X4 and X7-X8-X9-X10 also become large, and the degree of integration cannot be improved.

Therefore, in the present invention, the pitch of the wiring channel gratings is not uniform, but the pitch is uniform in one type of the wiring channel gratings so as to be optimized for each area of the circuit. Specific embodiments thereof will be described below with reference to the drawings.

The features of the embodiment shown in Fig. 1 are excluding the pitch between the wiring channel gratings Y0 to Y1 to Y2 and the wiring channel gratings Y4 to Y5 to Y6 in order to satisfy the design criteria between the strict contacts and the gate poly. The pitch of the other wiring channel gratings is narrower than in the prior art. In the pitch setting of the wiring channel grating, a four-input NAND gate is constructed as shown in FIG. 20, as shown in FIG. In Fig. 2, the wiring channel lattice X0 to X11 in the X direction and the wiring channel lattice Y2 to Y4 in the Y direction have a narrower pitch than in the prior art. As a result, compared with the conventional method of uniformly defining the pitch of the wiring channel grating, the formation area of the gate base cell can be reduced in both the X direction and the Y direction, thereby increasing the degree of integration.

3 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention as set forth in claim 2 or 3;

The characteristic of the embodiment shown in FIG. 3 is that the pitch between the wiring channel gratings X1 to X2 to X3 and X8 to X9 to X10 is set broadly with respect to the embodiment shown in FIG. That is, as shown in Fig. 4, the VSS (lower) power supply wiring 5b formed along the wiring channel lattice X2 and the VDD (higher) power supply wiring 5a formed along the wiring channel lattice X9 are arranged in the wiring width direction, for example, two. It is set so thick (or wide) that the contact hole 7 of the minimum size can be taken. The number and size of contact holes can be arbitrarily set as design matters.

Thus, by setting the pitch of the wiring channel grating corresponding to the power wiring wider than other wiring channel gratings, it is possible to increase the wiring width of the power wiring and to reduce the power supply voltage and electromigration due to the increase in the wiring resistance. You can prevent it. In addition, since the source contact resistance becomes small, a decrease in the operation speed can be suppressed.

In addition, in this embodiment, in addition to the above effects, the width of the power supply wiring is widened without widening wiring areas other than the wiring channel gratings Y0 to Y2, Y4 to Y6 and the power supply wiring, so that the pitch of the wiring channel grating is uniformly defined. Compared with the conventional method, the chip area can be reduced and the size can be reduced. As a result, it is possible to solve the inconsistencies caused by the thin wiring, which is a conventional problem, and improve the degree of integration at the same time.

FIG. 5 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention as claimed in claim 4; FIG.

The characteristic of the embodiment shown in FIG. 5 is that the pitch between the wiring channel gratings X3 to X4 and X7 to X8 is set to have the pitch between the wiring channel gratings X1 to X2 to X3 and X7 in order to have the objectability in the X direction with respect to the embodiment shown in FIG. It is in the thing set widely similarly to -X8-X9. In the pitch setting of the wiring channel grating, a four-input NAND gate is formed as shown in FIG.

As described above, when the wiring channel lattice in the X direction is subjected to objectivity, when a plurality of gate base cells are continuously arranged to form a desired logic circuit, the gate shown in FIG. 6 can be easily flipped as shown in FIG. have.

8 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention as claimed in claim 5;

The characteristic of the embodiment shown in FIG. 8 is that the pitch between wiring channel gratings X2 to X3 and X8 to X9 is wider than the embodiment shown in FIG.

In such a wiring channel grating, as shown in Fig. 9, the VDD (high) power supply wiring 5a is formed so as not to overlap the wiring center with respect to the wiring channel grating X9, and the wiring center does not overlap with the wiring channel grating X2. The VSS (lower) power supply wiring 5b is formed so that it may be combed. In this embodiment, compared with the embodiment shown in Figs. 3 and 4, there is an advantage in that the power supply wiring width equivalent to that shown in Fig. 4 can be obtained to reduce the size of the wiring channel grating in the X direction.

In addition, in this embodiment, since the object is in the X direction of the wiring channel grating, flip arrangement can be easily performed as shown in FIG.

FIG. 11 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention as claimed in claim 6.

The characteristic of the embodiment shown in FIG. 11 is that the one-layer wiring along the wiring channel grating X9 and the wiring channel grating Y5 when the area of the gate basic cell shown in FIG. 8 is used as the wiring area with respect to the embodiment shown in FIG. By the two-layer wiring along, the special signal wiring 8 such as the clock signal wiring and the wiring through which a large current flows is made to be thicker than the other wiring.

In such an embodiment, special signal wirings such as clock wirings requiring large wiring widths and wirings through which a large current flows can be easily thickened.

12 is a diagram showing the configuration of a semiconductor integrated circuit according to another embodiment of the invention as set forth in claim 2;

The characteristics of the embodiment shown in FIG. 12 are different from the embodiment shown in FIG. 8 in order to widen the pitch between the wiring channel gratings Y2 to Y3 and the Y3 to Y4 so that the wiring channel gratings Y2 and Y4 are not overlapped so as to be overlapped with Y2 ', Y4 '. In order to provide objectivity in the Y direction, the wiring channel grating Y0 is combed so as not to overlap in the wiring channel grating Y1 (Y1 ') direction, and the wiring channel grating Y6 is deviated so as not to overlap in the wiring channel grating Y5 (Y5') direction. Therefore, as shown in Fig. 13, the thick power supply reinforcement wiring 9 for reinforcing the power supply along the wiring channel lattice Y3 is formed by the two-layer wiring. In Fig. 13, ordinary wirings are formed along the wiring channel lattice Y0 'to Y2' and Y4 'to Y6'.

FIG. 14 shows the wiring channel gratings Y0 to Y6 by wiring using the wiring channel gratings X0 to X11 and the wiring channel gratings Y0 'to Y6' in the wiring channel grating shown in FIG. It is to form a contact hole using.

Fig. 15 superimposes the layout pattern shown in Fig. 14 on the layout pattern shown in Fig. 14, and since layout CAD considers only the wiring channel lattice X0 to X11 and Y0 'to Y6', the via hole contact can be easily connected.

FIG. 16 is a diagram showing the configuration of a semiconductor integrated circuit according to one embodiment of the invention described in claim 7.

The characteristic of the embodiment shown in FIG. 16 is that the pitch between the wiring channel gratings X2 to X3, X8 to X9, Y0 to Y1 to Y2, and Y4 to Y5 to Y6 is made wider than the embodiment shown in FIG.

In this embodiment, as shown in Fig. 17, the power supply wirings 5a and 5b can be wired thicker. In the case of using as a wiring area, as shown in Fig. 18, a wiring along the wiring channel lattice X23 is formed between the wiring channel lattice X2 and X3, and the wiring channel lattice X89 is formed between the wiring channel lattice X8 and X9. The wiring along the wiring channel grating Y0 and Y1 is formed, the wiring along the wiring channel grating Y01 'is formed, the wiring along the wiring channel grating Y1' and Y2 is formed between the wiring channel grating Y1 and Y2, and the wiring is formed. It is possible to form wiring along the wiring channel grating Y45 'between the channel gratings Y4 and Y5, and to form wiring along the wiring channel grating Y56' between the wiring channel gratings Y5 and Y6. In addition, layout efficiency can be improved by increasing the number of wirings. In addition, in such an embodiment, the more the difference between the wiring process and the diffusion process becomes smaller, the more effective.

In this embodiment, the number of wirings was increased by widening the pitch between the wiring channel lattice X2 to X3, X8 to X9, Y0 to Y1 to Y2, and Y4 to Y5 to Y6. However, when the difference in design criteria between the wiring process and the diffusion process becomes more significant, the layout efficiency can be improved by increasing the number of wirings without increasing the pitch of the wiring channel gratings.

As described above, according to the present invention, since the wiring channel lattice is defined to have a nonuniform pitch, the semiconductor suppresses the electromigration, the drop in the power supply voltage, and the decrease in the operation speed of the device while achieving an improvement in the degree of integration due to miniaturization. An integrated circuit can be provided.

Claims (8)

By arranging a plurality of gate basic cells on a semiconductor chip, defining a wiring channel grating on the basic gate cell, and connecting the arranged gate basic cells along the wiring channel grating, a desired logic function block can be obtained by only changing the wiring process. The semiconductor integrated circuit of the master slice system to be configured, wherein the wiring channel grating is defined at an uneven pitch in accordance with the gate basic cell structure. 2. The wiring channel grating according to claim 1, wherein the wiring channel grating provided with the high power wiring or the low power wiring among the wiring channel gratings has a wider pitch than the wiring channel grating provided with the wiring other than the high power wiring or the low power wiring. And a semiconductor integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein the high power supply wiring or the low power supply wiring has a wiring width in which a plurality of minimum contact holes or a plurality of contact holes of the minimum contact hole can be arranged. . The semiconductor integrated circuit according to claim 1, wherein said wiring channel grating defined by non-uniform pitch is an object with respect to the X direction or the Y direction of said gate base cell. 3. The semiconductor integrated circuit according to claim 2, wherein the high power supply wiring or the low power supply wiring has a center of the wiring width away from the wiring channel grating. The wiring channel grating according to claim 2, wherein the wiring channel grating having a wide pitch is used as a wiring channel grating for a special signal wiring when used as a wiring channel region other than the high power wiring or the low power wiring. Semiconductor integrated circuit. The wiring channel grating according to claim 2, wherein the wiring channel grating having a wide pitch is used as a wiring channel grating for a plurality of lines when the wiring channel grating is used as a wiring channel region other than the high power wiring or the low power wiring. A semiconductor integrated circuit characterized by. The plurality of gate basic cells are arranged on the semiconductor chip, and a plurality of functional blocks are arranged on the gate basic cell, and wiring regions defining wiring channel gratings are provided between the functional blocks and on the functional blocks. In a master slice type semiconductor integrated circuit in which a functional block is connected along the wiring channel lattice to form a desired logic circuit only by changing the wiring process, the wiring channel lattice is defined by a nonuniform pitch. integrated circuit.

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