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KR100237797B1 - Manufacturing method of semiconductor device having deep trench - Google Patents

Manufacturing method of semiconductor device having deep trench Download PDF

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Publication number
KR100237797B1
KR100237797B1 KR1019970063311A KR19970063311A KR100237797B1 KR 100237797 B1 KR100237797 B1 KR 100237797B1 KR 1019970063311 A KR1019970063311 A KR 1019970063311A KR 19970063311 A KR19970063311 A KR 19970063311A KR 100237797 B1 KR100237797 B1 KR 100237797B1
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udo
trench
nitride film
silicon nitride
semiconductor device
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KR1019970063311A
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Korean (ko)
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KR19990042476A (en
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김창균
이정환
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김충환
한국전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 깊은 트랜치를 갖는 반도체 장치의 제조방법에 관한 것으로, 이는 반도체 기판 위에 실리콘 질화막과 UDO를 순차적으로 도포하는 공정과, 상기 결과물 위에 사진식각 공정을 이용하여 UDO와 실리콘질화막을 순차적으로 식각하여 패터닝 하는 공정과, 상기 결과물의 패터닝된 UDO를 식각마스크로 사용하여 기판에 트랜치를 형성하는 공정과, 상기 결과물로부터 UDO를 제거하는 공정을 포함하는 데에 그 특징이 있다. 이 방법에 의하면 반도체 기판에 깊은 트랜치를 형성항 때 실리콘질화막과 UDO를 2중 도포한 후 상기 UDO를 식각마스크로 이용하여 트랜치를 형성하게 되므로, 추후 상기 실리콘질화막에 남아 있는 얼라인 키로 사용하여 후속 공정을 진행할 수 있게 되는 것이다.The present invention relates to a method of manufacturing a semiconductor device having a deep trench, which is a step of sequentially applying a silicon nitride film and UDO on the semiconductor substrate, and sequentially etching the UDO and silicon nitride film using a photolithography process on the resultant And a process of patterning, forming a trench in the substrate using the patterned UDO as an etch mask, and removing the UDO from the result. According to this method, when a deep trench is formed in a semiconductor substrate, a trench is formed using a double layer of silicon nitride film and UDO, and then the trench is formed using the UDO as an etching mask, which is subsequently used as an alignment key remaining in the silicon nitride film. You will be able to proceed with the process.

Description

깊은 트랜치를 갖는 반도체 소자의 제조방법Method for manufacturing a semiconductor device having a deep trench

본 발명은 깊은 트랜치를 갖는 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 반도체 소자에 3500Å 이상의 깊이를 갖는 트랜치를 형성함에 있어서 추가 공정의 진행없이 소자의 얼라인 키(align key)를 확보하여 후속 공정이 원할히 진행될 수 있도록 한 반도체 소자의 트랜치 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device having a deep trench, and more particularly, in forming a trench having a depth of 3500 Å or more in a semiconductor device, by securing an alignment key of the device without further processing. It relates to a trench formation method of a semiconductor device so that subsequent processing can proceed smoothly.

실리콘 웨이퍼에 아이솔레이션(Isolation) 등을 목적으로 트랜치를 형성하는 경우 식각마스크가 필요한데, 통상 깊이가 3500Å 이하인 트랜치의 경우에는 실리콘산화막이나 실리콘질화막을 사용하고, 그 이상의 깊이를 필요로 하는 트랜치를 형성하는 데에는 UDO(Undoped Oxide)를 사용한다.An etching mask is required to form a trench for isolation or the like on a silicon wafer. In the case of a trench having a depth of 3500 Å or less, a silicon oxide film or a silicon nitride film is used to form a trench that requires a depth greater than that. UDO (Undoped Oxide) is used for this.

이와 같이 깊은 트랜치를 형성하는 경우 UDO를 식각마스크로 사용하는 이유는, 예를들어 1㎛ 깊이로 트랜치를 형성하는 경우 식각마스크로 실리콘산화막을 사용한다면 실리콘산화막과 실리콘의 식각 선택비가 1 : 10 정도이기 때문에 적어도 0.1㎛ 두께 이상의 실리콘산화막이 필요하나, 이 두께로 산화막을 형성하는 데에는 시간이 많이 걸리기 때문이다.The reason why UDO is used as an etch mask when forming a deep trench is, for example, when using a silicon oxide film as an etch mask when forming a trench with a depth of 1 μm, the etching selectivity between silicon oxide and silicon is about 1: 10. For this reason, a silicon oxide film of at least 0.1 mu m thickness or more is required, but it takes a long time to form the oxide film at this thickness.

따라서 기존에는 통상 3500Å 이하의 깊이로 트랜치를 형성하는 경우에는 도 1에 도시된 바와 같이, 실리콘 기판(10) 위에 실리콘질화막(20)를 도포한 후 사진식각 공정으로 상기 질화막(20)을 패터닝 하고, 패터닝된 질화막(20)을 식각마스크로 사용하여 그 하부의 기판(10)에 트랜치를 형성하였다.Therefore, in the case of forming a trench with a depth of usually 3500 Å or less, as shown in FIG. 1, after the silicon nitride film 20 is coated on the silicon substrate 10, the nitride film 20 is patterned by a photolithography process. Using the patterned nitride film 20 as an etching mask, a trench is formed in the substrate 10 under the patterned nitride film 20.

또한 3500Å 이상의 깊이로 트랜치를 형성하는 경우에는 도 2에 도시된 바와 같이 UDO(30)를 트랜치의 식각마스크로 사용하였다.In addition, when the trench is formed to a depth of 3500 kPa or more, as illustrated in FIG. 2, the UDO 30 is used as an etching mask of the trench.

그러나 UDO를 식각마스크로 사용하는 경우 RIE(Reactive Ion Etching) 식각 후에 기판(10) 위에 UDO가 불균일하게 남게 되며, 이를 식각용액인 BHF로 제거하게 되는데, 이를 제거하고 나면 기판(10)의 표면에 얼라인할 부분이 없어지므로 트랜치를 형성하기 전에 추가 공정을 진행하여 얼라인 키를 만들어야 했다.However, when UDO is used as an etching mask, UDO remains unevenly on the substrate 10 after Reactive Ion Etching (RIE) etching, and it is removed by BHF, which is an etching solution. Since there was no part to align, we had to go through additional steps to create the align key before forming the trench.

본 발명은 이러한 종래 기술의 문제점을 해결하고자 한 것으로, 그 목적은 깊은 트랜치 형성 후에 별도의 얼라인 키 형성 공정의 진행없이 반도체 소자를 제조할 수 있도록 한 깊은 트랜치를 갖는 반도체 소자의 제조방법을 제공하는 데에 있다.The present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method for manufacturing a semiconductor device having a deep trench to enable the manufacture of a semiconductor device without proceeding a separate alignment key formation process after the deep trench formation. It's there.

본 발명의 목적을 달성하기 위한 깊은 트랜치를 갖는 반도체 소자의 제조방법은, 반도체 기판 위에 실리콘 질화막과 UDO를 순차적으로 도포하는 공정과, 상기 결과물 위에 사진식각 공정을 이용하여 UDO와 실리콘질화막을 순차적으로 식각하여 패터닝 하는 공정과, 상기 결과물의 패터닝된 UDO를 식각마스크로 사용하여 기판에 트랜치를 형성하는 공정과, 상기 결과물로부터 UDO를 제거하는 공정을 포함하는 데에 그 특징이 있다.A method of manufacturing a semiconductor device having a deep trench for achieving the object of the present invention, a step of sequentially applying a silicon nitride film and a UDO on a semiconductor substrate, and sequentially using a UDO and a silicon nitride film using a photolithography process on the resultant Etching and patterning, forming a trench in the substrate using the resulting patterned UDO as an etching mask, and removing the UDO from the resulting product.

도 1과 도 2는 종래 기술에 의한 반도체 소자 트랜치 형성 공정을 설명하기 위한 수직 단면도.1 and 2 are vertical cross-sectional views for explaining a semiconductor device trench formation process according to the prior art.

도 3 내지 도 7은 본 발명에 따른 깊은 트랜치를 갖는 반도체 소자의 제조공정순 수직 단면도.3 to 7 are vertical cross-sectional views of a manufacturing process of a semiconductor device having a deep trench according to the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

10 : 실리콘 기판 20,22 : 실리콘질화막10 silicon substrate 20,22 silicon nitride film

30,32 : UDO 40 : 포토레지스트30,32: UDO 40: photoresist

이하, 본 발명에 따른 깊은 트랜치를 갖는 반도체 소자의 제조방법에 대해 첨부한 도 3 내지 도 7을 참조하여 상세하게 설명하고자 한다.Hereinafter, a method of manufacturing a semiconductor device having a deep trench according to the present invention will be described in detail with reference to FIGS. 3 to 7.

먼저 도 3 에 나타낸 바와 같이, 실리콘 기판(10) 위에 실리콘질화막(22)과 UDO(32)를 순차적으로 도포하고, 도 4에서와 같이 상기 UDO(32) 위에 포토레지스트(40)를 도포하고 이를 패터닝한다.First, as shown in FIG. 3, the silicon nitride film 22 and the UDO 32 are sequentially coated on the silicon substrate 10, and the photoresist 40 is coated on the UDO 32 as shown in FIG. 4. Pattern.

다음 도 5에 나타낸 바와 같이, 상기 포토레지스트(40) 패턴을 식각마스크로 사용하여 그 하부에 위치한 UDO(32)를 식각하고, 포토래지스트 패턴이 남아 있는 상태에서 RIE 방식을 이용하여 실리콘질화막(22)을 식각한다.Next, as shown in FIG. 5, the UDO 32 located below the substrate is etched using the photoresist 40 pattern as an etching mask, and the silicon nitride film (RIE) method is used in a state where the photoresist pattern remains. Etch 22).

다음 도 5에 도시된 바와 같이, 포토레지스트(40)를 제거하고 패터닝된 UDO(32)를 식각마스크로 사용하여 하부의 실리콘 기판을 RIE 방식을 이용 식각하여 트랜치를 형성한다.Next, as shown in FIG. 5, the trench is formed by removing the photoresist 40 and etching the lower silicon substrate using an RIE method using the patterned UDO 32 as an etching mask.

그 후 도 7에 나타낸 바와 같이, 트랜치 식각 후 불균일하게 남아 있는 UDO(22)를 BHF 등을 이용 제거하면 실리콘질화막(22)이 남게 된다.After that, as shown in FIG. 7, the silicon nitride film 22 remains when the UDO 22 remaining uneven after the trench etching is removed using BHF or the like.

이후에는 상기 실리콘질화막(22)에 남아 있는 얼라인 키(50)를 이용하여 후속공정을 진행하여 바이폴라 등의 반도체 소자를 제조한다.Thereafter, a subsequent process is performed using the alignment key 50 remaining in the silicon nitride film 22 to manufacture a semiconductor device such as bipolar.

이상에서 상세히 설명한 바와 같이, 본 발명은 반도체 기판에 깊은 트랜치를 형성하는 경우 실리콘질화막과 UDO를 2중 도포한 후 상기 UDO를 식각마스크로 이용하여 트랜치를 형성하게 되므로, 추후 공정을 상기 실리콘질화막에 남아있는 얼라인 키를 이용하여 진행할 수 있는 바, 기존과 같이 별도의 공정에 의해 얼라인 키를 형성할 필요가 없어지게 된다.As described in detail above, in the present invention, when the deep trench is formed on the semiconductor substrate, since the silicon nitride film and the UDO are double coated, the trench is formed by using the UDO as an etching mask. Since it can proceed using the remaining alignment keys, there is no need to form the alignment keys by a separate process as before.

Claims (1)

반도체 기판 위에 실리콘질화막과 UDO를 순차적으로 도포하는 공정과, 상기 결과물 위에 사진식각 공정을 이용하여 UDO와 실리콘질화막을 순차적으로 식각하여 패터닝 하는 공정과, 상기 결과물의 패터닝된 UDO를 식각마스크로 사용하여 기판에 트랜치를 형성하는 공정과, 상기 결과물로부터 UDO를 제거하는 공정을 포함하는 깊은 트랜치를 갖는 반도체 소자의 제조방법.A process of sequentially applying a silicon nitride film and a UDO on a semiconductor substrate, a process of sequentially etching and patterning a UDO and a silicon nitride film using a photolithography process on the resultant, and using the patterned UDO of the resultant as an etching mask A method of manufacturing a semiconductor device having a deep trench comprising a step of forming a trench in the substrate, and a step of removing the UDO from the resultant.
KR1019970063311A 1997-11-27 1997-11-27 Manufacturing method of semiconductor device having deep trench KR100237797B1 (en)

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