KR100235108B1 - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- KR100235108B1 KR100235108B1 KR1019930004245A KR930004245A KR100235108B1 KR 100235108 B1 KR100235108 B1 KR 100235108B1 KR 1019930004245 A KR1019930004245 A KR 1019930004245A KR 930004245 A KR930004245 A KR 930004245A KR 100235108 B1 KR100235108 B1 KR 100235108B1
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor
- leads
- semiconductor chips
- package
- chips
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
이 발명은 반도체 패키지에서, 서로 크기가 다른 두 개의 반도체 칩을 일정 간격으로 형성되어 있는 리들의 일측 상부 및 하부에 실장하거나, 리드들의 일측상부에 두 개의 반도체 칩을 적층 절연실장하여 와이어로 리드들과 연결함으로써, 모듈이나 IC카드등의 면적을 적게 차지하여 메모리 용량 및 실장밀도를 향상시킬 수 있다. 서로 동작이 다른 두 개의 반도체 칩을 리드의 수를 증가시켜 하나의 패키지 몸체에 실장함으로써, 모듈등의 실장밀도를 향상시킬 수 있다.According to the present invention, two semiconductor chips of different sizes are mounted on an upper side and a lower side of a ladle formed at regular intervals, or two semiconductor chips are laminated and mounted on an upper side of the leads to wires. By connecting to the module, the memory capacity and mounting density can be improved by taking up less area of the module or IC card. By mounting two semiconductor chips having different operations to each other and increasing the number of leads in one package body, the mounting density of the module or the like can be improved.
Description
제1도는 종래 기술에 따른 반도체 패키지의 일 실시예의 단면도.1 is a cross-sectional view of one embodiment of a semiconductor package according to the prior art.
제2도는 종래 기술에 따른 반도체 패키지의 다른 실시예의 단면도.2 is a cross-sectional view of another embodiment of a semiconductor package according to the prior art.
제3도는 이 발명에 따른 반도체 패키지의 일실시예의 단면도.3 is a cross-sectional view of one embodiment of a semiconductor package according to the present invention.
제4도는 이 발명에 따른 반도체 패키지의 다른 실시예의 단면도이다.4 is a cross-sectional view of another embodiment of a semiconductor package according to the present invention.
이 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 서로 크기가 다른 두 개의 반도체 칩을 하나의 패키지에 실장하여 실장밀도를 향상시킴으로써 고집적화가 가능하고 실장공정이 간단하여 신뢰성을 향상시킬수 있는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package that can be highly integrated and improves reliability by mounting two semiconductor chips of different sizes in a single package and improving the mounting density. It is about.
최근 반도체 장치의 고집적화, 메모리 용량의 증가, 신호 처리속도 및 소비전력의 증가, 다기능화 및 고밀도 실장의 요구등이 가속화되는 추세에 따라 반도체 패키지의 중요성이 증가되고 있다. 이러한 반도체 장치의 고집적화 및 메모리 용량의 증가로 입출력 단자 수가 증가되어 감에 따라 반도체 장치의 외부와의 접속을 위한 입출력 단자인 리드의 수가 증가되므로 리드가 미세 피치(fine pitch)화 되고 있다. 또한 반도체 장치의 신호 처리 속도 및 소비 전력이 증가되어 감에 따라 반도체 장치에서 다량의 열이 발생되며, 이 열을 발산시키기 위하여 반도체 패키지에 별도의 히트 싱크를 형성하거나, 열전도율이 높은 재료로 패키지 몸체를 형성한다. 또한, 반도체 장치의 다기능화에 따라 여러 가지 기능을 갖는 반도체 패키지가 요구되고 있다. 또한 반도체 장치의 고밀도 실장의 요구에 따라 반도체 패키지를 적층하거나, 반도체 소자를 직접 인쇄회로기판(printed circuit board; 이하 PCB라 칭함)상에 실장하는 칩 온 보드(chip on board; COB)방법등이 연구 실행되고 있다.In recent years, the importance of semiconductor packages is increasing due to the trend of high integration of semiconductor devices, increase in memory capacity, increase in signal processing speed and power consumption, demand for multifunctionalization, and high density mounting. As the number of input / output terminals increases due to the higher integration of the semiconductor device and the increase in memory capacity, the number of leads, which are input / output terminals for connecting to the outside of the semiconductor device, increases, leading to fine pitch. In addition, as the signal processing speed and power consumption of the semiconductor device increase, a large amount of heat is generated in the semiconductor device. In order to dissipate this heat, a separate heat sink is formed in the semiconductor package, or the package body is made of a material having high thermal conductivity. To form. In addition, there is a demand for a semiconductor package having various functions as the semiconductor device becomes more versatile. In addition, a chip on board (COB) method of stacking semiconductor packages or mounting semiconductor devices directly on a printed circuit board (hereinafter referred to as a PCB) according to a demand for high-density mounting of a semiconductor device. Research is being carried out.
일반적으로, IC 또는 LSI등의 반도체 칩은 반도체 패키지에 밀봉되어 PCB에 장착된다. 반도체 패키지의 기본형은 반도체 칩이 방열용 금속판인 다이패드상에 장착되며, 본딩 와이어에 의해 반도체 칩의 전극단자인 본딩패드와 외부회로 접속용의 리드가 접속되고, 에폭시 몰딩 컴파운드(epoxy molding compound; 이하 EMC라 칭함)로 형성된 패키지 몸체가 반도체 칩과 와이어를 감싸 보호하는 구조를 갖는다. 이와 같은 반도체 패키지는 리드가 패키지의 양변으로부터 수직아래방향으로 돌출되어 있는 DIP(dual inline package)방식과, 리드가 패키지의 4변으로 돌출되어 있는 QFP(quad flat package)방식이 주류를 이루고 있다. QFP는 리드의 수를 DIP보다 비교적 많이 형성할 수 있으므로 PCB상의 실장밀도를 약간 더 높일 수 있는 이점이 있다.In general, a semiconductor chip such as an IC or LSI is sealed in a semiconductor package and mounted on a PCB. The basic type of a semiconductor package is a semiconductor chip mounted on a die pad of a heat dissipating metal plate, and a bonding pad, which is an electrode terminal of the semiconductor chip, and a lead for connecting an external circuit are connected by a bonding wire, and an epoxy molding compound; The package body formed of an EMC) is wrapped around and protects a semiconductor chip and a wire. Such semiconductor packages mainly include a dual inline package (DIP) method in which leads protrude downward and downward from both sides of the package, and a quad flat package (QFP) method in which leads protrude to four sides of the package. QFP can form a relatively larger number of leads than DIP, which has the advantage of slightly increasing the mounting density on the PCB.
제1도는 종래 기술에 따른 반도체 패키지(10)의 일 실시예를 나타내는 단면도이다.1 is a cross-sectional view showing an embodiment of a semiconductor package 10 according to the prior art.
한쌍의 메모리용 제1 및 제2반도체 칩(11),(12)의 본딩패드(도시되지 않음)들이 범프(13)를 사이에 두고 각각 입출력단자인 보조 리드(14a),(14b)들과 연결되어 있다. 제1 및 제2반도체 칩(11),(12)은 서로 배면을 마주보고 있으며, 제1반도체 칩(11)은 통상의 포워드 칩(forward chip)이고, 제2반도체 칩(12)은 제1반도체 칩(11)과 회로 및 본딩패드들이 대칭되는 형상으로 형성되어 있는 리버스 칩(reverse chip)이다. 또한 보조 리드(14a),(14b)들은 탭(TAB; tape automated bonding)패키지용의 박막 리드들이며, 보조 리드(14a),(14b) 사이에 외부와 연결되는 리드(15)가 개재되어 있어, 서로 같은 동작을 수행하는 본딩패드와 연결되어 있는 보조리드(14a),(14b)를 연결시킨다. 또한 제1 및 제2반도체 칩(11),(12)과 보조 리드(14a),(14b)들은 EMC로 성형되어 있는 패키지 몸체(19)가 감싸 보호한다.Bonding pads (not shown) of the pair of first and second semiconductor chips 11 and 12 for memory are provided with auxiliary leads 14a and 14b, which are input / output terminals, respectively, with bumps 13 interposed therebetween. It is connected. The first and second semiconductor chips 11 and 12 face back to each other, the first semiconductor chip 11 is a normal forward chip, and the second semiconductor chip 12 is a first chip. The semiconductor chip 11 is a reverse chip in which circuits and bonding pads are formed in a symmetrical shape. In addition, the auxiliary leads 14a and 14b are thin film leads for a tape automated bonding (TAB) package, and the leads 15 connected to the outside are interposed between the auxiliary leads 14a and 14b. The auxiliary leads 14a and 14b connected to the bonding pads performing the same operation are connected to each other. In addition, the first and second semiconductor chips 11 and 12 and the auxiliary leads 14a and 14b are wrapped and protected by an EMC molded package body 19.
제2도는 종래 기술에 따른 반도체 패키지(20)의 다른 실시예를 나타내는 단면도로서, 제1도보다 실장밀도를 더욱 향상시키기 위하여 두쌍의 메모리용 반도체 칩들이 적층되어 있는 반도체 패키지이다.FIG. 2 is a cross-sectional view showing another embodiment of the semiconductor package 20 according to the related art, and is a semiconductor package in which two pairs of memory semiconductor chips are stacked in order to further improve the mounting density of the semiconductor package 20.
포워드 칩인 한쌍의 제1반도체 칩(21)과, 리버스 칩인 한쌍의 제2반도체칩(22)의 본딩패드(도시되지 않음)들이 탭 패키지용의 보조 리드(24a,24b,24c,24d)들과 범프(23)를 사이에 두고 연결되어 있다. 또한 제1반도체 칩(21)과 제2반도체 칩(22)이 하나씩 서로 배면을 마주보고 연결되어 쌍을 이루며, 제1 및 제2반도체 칩(21),(22)의 쌍이 상하로 연결되어 있다. 상측의 제1 및 제2반도체칩(21),(22)과 연결된 동일한 동작을 하는 보조리드(24a),(24b)들은 직접 연결되어 있으며, 하측의 보조 리드(24c),(24d)들도 서로 연결되어 있고, 보조 리드(24a)과 (24b) 및 (24c)와 (24d)의 사이에 외부와 연결되는 리드(25)가 개재된다. 또한 한쌍의 제1 및 제2반도체 칩(21),(22)과 보조 리드(24a,24b,24c,24d)들을 감싸 보호하도록 패키지 몸체(29)가 EMC로 형성되어 있다.The bonding pads (not shown) of the pair of first semiconductor chips 21, which are forward chips, and the pair of second semiconductor chips 22, which are reverse chips, are connected to the auxiliary leads 24a, 24b, 24c, and 24d for the tap package. The bumps 23 are connected to each other. In addition, the first semiconductor chip 21 and the second semiconductor chip 22 are connected to each other and face each other to form a pair, and the pair of the first and second semiconductor chips 21 and 22 are connected vertically. . The auxiliary leads 24a and 24b having the same operation connected to the first and second semiconductor chips 21 and 22 on the upper side are directly connected, and the auxiliary leads 24c and 24d on the lower side are also connected. A lead 25 is connected to each other and connected to the outside between the auxiliary leads 24a and 24b and 24c and 24d. In addition, the package body 29 is formed of EMC to surround and protect the pair of first and second semiconductor chips 21 and 22 and the auxiliary leads 24a, 24b, 24c, and 24d.
상술한 종래의 반도체 패키지들은 포워드 칩과 리버스 칩을 하나의 패키지로 형성하므로 실장 밀도를 향상시킬 수 있으나, 동일한 동작을 수행하는 반도체 칩만을 패키지화 할 수 있으며, 별도의 리버스 칩을 형성하여야 하는 문제점이 있다.Since the above-described conventional semiconductor packages form a forward chip and a reverse chip as one package, the mounting density can be improved, but only a semiconductor chip performing the same operation can be packaged, and a separate reverse chip must be formed. have.
이 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 이 발명의 목적은 서로 기능 및 크기가 다른 두 개의 반도체 칩을 하나의 패키지에 실장하여 실장 밀도를 향상시킬 수 있는 반도체 패키지를 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to provide a semiconductor package that can improve the mounting density by mounting two semiconductor chips of different functions and sizes in one package.
이 발명의 다른 목적은 별도의 리버스 칩을 형성하지 않고 메모리 용량을 증가시킬 수 있는 반도체 패키지를 제공함에 있다.Another object of the present invention is to provide a semiconductor package capable of increasing memory capacity without forming a separate reverse chip.
상기와 같은 목적을 달성하기 위하여, 이 발명은 일정간격으로 형성되어 있는 리드들과; 상기 리드들의 일측 상부에 실장되며, 상기 리드들과 제1와이어로 연결되는 제1반도체 칩과; 상기 제1반도체 칩보다 면적이 크며, 상기 리드들의 일측 하부에 실장되고, 상기 리드들과 중첩되지 않는 부분에 본딩패드들이 형성되어 있으며, 상기 리드들과 제2와이어로 연결되는 제2반도체 칩과; 상기 제1 및 제2반도체 칩과 제1 및 제2와이어를 감싸 보호하는 패키지 몸체를 구비하는 반도체 패키지를 제공한다.In order to achieve the above object, the present invention and the lead is formed at a predetermined interval; A first semiconductor chip mounted on one side of the leads and connected to the leads by a first wire; A second semiconductor chip having an area larger than that of the first semiconductor chip, mounted on one side of the leads and not overlapping the leads, and connected to the leads and a second wire; ; A semiconductor package includes a package body surrounding and protecting the first and second semiconductor chips and the first and second wires.
이하, 이 발명에 따른 반도체 패키지의 바람직한 실시예에 대하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a preferred embodiment of a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.
제3도는 이 발명에 따른 반도체 패키지(30)의 일 실시예를 나타내는 단면도로서, 서로 크기 및 작용이 다른 두 개의 반도체 칩(31),(32)이 하나의 패키지몸체(39)에 몰딩되어 있는 반도체 패키지이다.3 is a cross-sectional view showing an embodiment of the semiconductor package 30 according to the present invention, in which two semiconductor chips 31 and 32 having different sizes and functions from each other are molded in one package body 39. Semiconductor package.
일정간격으로 리드(35)들이 형성되어 있으며, 리드(35)들의 일측 상·하부에 제1 및 제2반도체 칩(31),(32)이 실장되어 있으며, 제1 및 제2반도체 칩(31),(32)의 본딩패드(33),(34)들이 리드(35)들의 일측과 제1 및 제2와이어(37),(38)들로 연결되어 있다. 여기서 리드(35)들의 하부에 실장되는 제2반도체칩(32)은 제1반도체 칩(31)보다 면적이 크고, 본딩패드(34)의 위치가 리드(35)들과 중첩되지 않도록 서로 엇갈리게 형성되어 있는 반도체 칩으로써, 제1반도체 칩(31)과 동일한 동작을 수행하거나, 서로 다른 종류의 칩이다. 제1 및 제2반도체 칩(31),(32)은 접착수단(36), 예를 들면 폴리이미드 테이프 또는 절연 접착제로 접착되어 있으며, 제1 및 제2반도체 칩(31),(32)과 제1 및 제2와이어(37),(38)들을 감싸 보호하는 패키지 몸체(39)가 EMC등의 몰딩 부재로 형성되어 있다.Leads 35 are formed at predetermined intervals, and first and second semiconductor chips 31 and 32 are mounted on upper and lower sides of the leads 35, and the first and second semiconductor chips 31. The bonding pads 33 and 34 of the 32 and 32 are connected to one side of the leads 35 and the first and second wires 37 and 38. Here, the second semiconductor chip 32 mounted below the leads 35 has a larger area than the first semiconductor chip 31, and is formed to cross each other so that the positions of the bonding pads 34 do not overlap with the leads 35. As a semiconductor chip, the same operation as that of the first semiconductor chip 31 is performed, or a different type of chip. The first and second semiconductor chips 31 and 32 are bonded with an adhesive means 36, for example, polyimide tape or an insulating adhesive, and the first and second semiconductor chips 31 and 32 are bonded to each other. The package body 39 surrounding and protecting the first and second wires 37 and 38 is formed of a molding member such as EMC.
제1 및 제2반도체 칩(31),(32)이 서로 크기 및 동작이 다른 칩이면, 제1 및 제2반도체 칩(31),(32)과 연결되는 각각의 리드(35)들을 동일 평면상에 배열되며, 제1 및 제2와이어(37),(38)들은 서로 다른 리드(35)와 연결된다. 또한 제1 및 제2반도체 칩(31),(32)이 크기만 다른 동일한 동작을 수행하는 메모리용 칩이며, 리드(35)들은 제1 및 제2반도체 칩(31),(32)의 동일한 동작을 수행하는 본딩패드(33),(34)들과 연결된다.If the first and second semiconductor chips 31 and 32 are chips of different sizes and operations, the leads 35 connected to the first and second semiconductor chips 31 and 32 are coplanar. The first and second wires 37, 38 are connected to different leads 35. In addition, the first and second semiconductor chips 31 and 32 are memory chips for performing the same operation with different sizes, and the leads 35 are the same as those of the first and second semiconductor chips 31 and 32. It is connected to the bonding pads 33 and 34 that perform the operation.
제4도는 이 발명에 따른 반도체 패키지(40)의 다른 실시예의 단면도로서, 서로 크기는 다르나 동일한 동작을 수행하는 두 개의 메모리용 반도체 칩(41).(42)을 하나의 패키지몸체(49)에 실장한 반도체 패키지이다.4 is a cross-sectional view of another embodiment of a semiconductor package 40 according to the present invention, in which two memory semiconductor chips 41 and 42 having different sizes but performing the same operation are placed in one package body 49. It is a semiconductor package mounted.
일정간격으로 형성되어 있는 리드(45)들과, 리드(45)들의 일측 상부에 실장 되어 있는 제1반도체 칩(42)과, 제1반도체 칩(42)의 상부에 실장되며 면적이 제1반도체 칩(42)보다 작은 제2반도체 칩(41)과, 제1 및 제2반도체 칩(42),(41)의 본딩패드(44),(43)들을 리드(45)들과 연결시키는 제1 및 제2와이어(48),(47)들과, 제1 및 제2반도체 칩(42),(41)과 제1 및 제2와이어(48),(47)들을 감싸 보호하는 패키지 몸체(49)로 구성되어 있다.Leads 45 formed at a predetermined interval, the first semiconductor chip 42 mounted on one side of the lead 45, and the first semiconductor chip 42 is mounted on the upper portion of the first semiconductor chip 42 A second semiconductor chip 41 smaller than the chip 42 and a first pad connecting the bonding pads 44 and 43 of the first and second semiconductor chips 42 and 41 to the leads 45. And a package body 49 which encloses and protects the second wires 48, 47 and the first and second semiconductor chips 42, 41 and the first and second wires 48, 47. It consists of).
이때 제1 및 제2반도체 칩(42),(41)은 제3도의 경우와 마찬가지로 접착수단(46)에 의해 실장되며, 제1 및 제2반도체 칩(42),(41)은 동일한 용량의 메모리용 반도체 칩이면, 동일한 동작을 수행하는 본딩패드(43),(44)들은 동일한 리드(45)들과 연결되며, 서로 다른 칩이면, 각각의 본딩패드(43),(44)들과 연결되는 리드(45)들을 서로 분리시켜 동일 평면에 형성한다.At this time, the first and second semiconductor chips 42 and 41 are mounted by the bonding means 46 as in the case of FIG. 3, and the first and second semiconductor chips 42 and 41 have the same capacitance. In the case of a memory semiconductor chip, the bonding pads 43 and 44 which perform the same operation are connected to the same leads 45. The leads 45 are separated from each other and formed on the same plane.
이상에서 설명한 바와 같이 이 발명에 따른 반도체 패키지에 의하면, 서로 크기가 다른 두 개의 반도체 칩을 일정간격으로 형성되어 있는 리드들의 일측 상부 및 하부에 실장하거나, 리드들의 일측 상부에 두 개의 반도체 칩을 적층 절연실장하여 와이어로 리드들과 연결함으로써, 모듈이나 IC카드등의 면적을 적게 차지하여 메모리 용량 및 실장 밀도를 향상시킬 수 있는 이점이 있다. 그리고, 서로 동작이 다른 두 개의 반도체 칩을 리드의 수를 증가시켜 하나의 패키지 몸체에 실장함으로써, 모듈등의 실장밀도를 향상시킬 수 있는 이점이 있다.As described above, according to the semiconductor package according to the present invention, two semiconductor chips having different sizes are mounted on upper and lower sides of leads formed at predetermined intervals, or two semiconductor chips are stacked on upper sides of the leads. By insulating and connecting the leads with wires, there is an advantage that the memory capacity and the mounting density can be improved by occupying a small area of the module or IC card. In addition, by mounting two semiconductor chips having different operations in one package body by increasing the number of leads, there is an advantage in that mounting density of a module or the like can be improved.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930004245A KR100235108B1 (en) | 1993-03-19 | 1993-03-19 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930004245A KR100235108B1 (en) | 1993-03-19 | 1993-03-19 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940022822A KR940022822A (en) | 1994-10-21 |
| KR100235108B1 true KR100235108B1 (en) | 1999-12-15 |
Family
ID=19352434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930004245A KR100235108B1 (en) | 1993-03-19 | 1993-03-19 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100235108B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100977915B1 (en) | 2005-12-06 | 2010-08-24 | 춘-흐신 호 | Dual integrated circuit card system |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100618541B1 (en) * | 1999-07-06 | 2006-08-31 | 삼성전자주식회사 | Method for fabricating multi-chip semiconductor package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0215660A (en) * | 1988-07-01 | 1990-01-19 | Sharp Corp | Semiconductor device |
| JPH04142073A (en) * | 1990-10-02 | 1992-05-15 | Nec Yamagata Ltd | Semiconductor device |
-
1993
- 1993-03-19 KR KR1019930004245A patent/KR100235108B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0215660A (en) * | 1988-07-01 | 1990-01-19 | Sharp Corp | Semiconductor device |
| JPH04142073A (en) * | 1990-10-02 | 1992-05-15 | Nec Yamagata Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100977915B1 (en) | 2005-12-06 | 2010-08-24 | 춘-흐신 호 | Dual integrated circuit card system |
Also Published As
| Publication number | Publication date |
|---|---|
| KR940022822A (en) | 1994-10-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5444296A (en) | Ball grid array packages for high speed applications | |
| US6204562B1 (en) | Wafer-level chip scale package | |
| US8035204B2 (en) | Large die package structures and fabrication method therefor | |
| US5245215A (en) | Multichip packaged semiconductor device and method for manufacturing the same | |
| JP3762844B2 (en) | Opposite multichip package | |
| US5373188A (en) | Packaged semiconductor device including multiple semiconductor chips and cross-over lead | |
| KR101070913B1 (en) | Stacked die package | |
| US5349235A (en) | High density vertically mounted semiconductor package | |
| US5742477A (en) | Multi-chip module | |
| US5349233A (en) | Lead frame and semiconductor module using the same having first and second islands and three distinct pluralities of leads and semiconductor module using the lead frame | |
| KR100235108B1 (en) | Semiconductor package | |
| KR970005719B1 (en) | Double attached memory package | |
| US20050023659A1 (en) | Semiconductor chip package and stacked module having a functional part and packaging part arranged on a common plane | |
| KR100216061B1 (en) | Semiconductor package | |
| KR200295665Y1 (en) | Stacked Semiconductor Package | |
| KR19980025890A (en) | Multi-chip package with lead frame | |
| KR100235495B1 (en) | Semiconductor apparatus | |
| KR100352118B1 (en) | Semiconductor package structure | |
| US6924557B2 (en) | Semiconductor package | |
| KR950014124B1 (en) | Semiconductor package and manufacture method | |
| KR950006434B1 (en) | Lead frame | |
| US20020053450A1 (en) | Wafer-level package | |
| KR960004090B1 (en) | Semiconductor package | |
| KR20010036630A (en) | Stack chip package | |
| KR100567045B1 (en) | A package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20070903 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |