KR100223333B1 - Method for forming a contact of semiconductor device - Google Patents
Method for forming a contact of semiconductor device Download PDFInfo
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- KR100223333B1 KR100223333B1 KR1019960025716A KR19960025716A KR100223333B1 KR 100223333 B1 KR100223333 B1 KR 100223333B1 KR 1019960025716 A KR1019960025716 A KR 1019960025716A KR 19960025716 A KR19960025716 A KR 19960025716A KR 100223333 B1 KR100223333 B1 KR 100223333B1
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- forming
- silicon nitride
- nitride film
- silicon
- etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 트랜지스터 콘택홀 형성의 마지막 단계에서 건식식각이 아닌 습식식각을 사용함으로써, 소오스/드레인 접합에서 식각에 의한 데미지를 없애 접합 누설전류를 감소시켜 트랜지스터의 특성을 개선시킬 수 있는 소자의 콘택홀 제조방법에 관한 것이다.The present invention relates to a method of forming a contact hole in a semiconductor device, and in particular, by using wet etching instead of dry etching in the last step of forming a transistor contact hole, the damage of the source / drain junction is eliminated by etching to reduce the junction leakage current. The present invention relates to a method for manufacturing a contact hole of a device capable of improving the characteristics of a transistor.
Description
제1도 내지 제6도는 본 발명의 방법에 따른 반도체 소자의 콘택홀 형성 공정단계를 도시한 단면도1 to 6 are cross-sectional views illustrating the process steps for forming a contact hole in a semiconductor device according to the method of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1: N-웰(또는 P-웰) 2 : 실리콘 산화막1: N-well (or P-well) 2: silicon oxide film
3 : 다결정 실리콘 층 4 : 감광막3: polycrystalline silicon layer 4: photosensitive film
5 : 제1 실리콘 질화막 6 : 제2 실리콘 질화막5: first silicon nitride film 6: second silicon nitride film
7 : 제2 실리콘 질화막 스페이 서 8 : 게이트 산화막7 second silicon nitride film spacer 8 gate oxide film
10,30 : 콘택홀10,30: contact hole
[발명의 상세한 설명]Detailed description of the invention
본 발명의 반도체 소자의 콘택홀 형성방법에 관한 것으로, 특히 트랜지스터(TRANSISTOR) 콘택홀 형성의 마지막 단계에서 건식식각이 아닌 습식식각을 사용함으로써, 소오스/드레인 접합에서 식각에 의한 손상(Damage)을 없애 접합 누설전류를 감소시켜 트랜지스터의 특성을 개선시킬 수 있는 반도체 소자의 콘택홀 제조방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, by using wet etching instead of dry etching in the final step of forming a transistor contact hole, etching damage in a source / drain junction is eliminated. The present invention relates to a method for manufacturing a contact hole in a semiconductor device capable of improving the characteristics of a transistor by reducing a junction leakage current.
일반적으로 종래의 기술에 따른 반도체 트랜지스터의 콘택홀 형성방법에 있어서, 콘택홀 형성을 위한 마지막 식각 단계가 건식식각으로 진행되기 때문에 소오스/드레인(Source/Drain) 접합이 건식식각에 의해 손상된다.In general, in the method of forming a contact hole of a semiconductor transistor according to the related art, the source / drain junction is damaged by dry etching because the last etching step for forming the contact hole is performed by dry etching.
또한 상기와 같이 건식식각에 의한 손상은 접합누설전류를 증가시켜 트랜지스터의 특성을 열화시킬 뿐만 아니라, 특히 반도체 디램 소자에서는 리프레쉬 시간(Refresf time)을 감소시키는 원인으로 작용하여 반도체 소자의 신뢰성을 저하시키게 되는 문제점이 있다.In addition, as described above, the damage caused by dry etching not only degrades the characteristics of the transistor by increasing the junction leakage current, but also acts as a cause of reducing the refresh time in the semiconductor DRAM device, thereby lowering the reliability of the semiconductor device. There is a problem.
따라서 본 발명은 상기의 문제점을 해결하기 위하여 트랜지스터 콘택홀 형성의 마지막 단계에서 건식식각이 아닌 습식식각을 사용함으로써, 소오스/드레인 접합에서 식각에 의한 손상을 없애 접합누설전류를 감소시켜 트랜지스터의 특성을 개선 시킬 수 있는 반도체 소자의 콘택홀 형성방법을 제공함에 그 목적이 있다.Therefore, in order to solve the above problem, the present invention uses wet etching instead of dry etching in the last step of forming the transistor contact hole, thereby eliminating the damage caused by etching in the source / drain junction, thereby reducing the junction leakage current to improve the characteristics of the transistor. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device that can be improved.
상기 목적을 달성하기 위한 본 발명의 방법에 의하면,According to the method of the present invention for achieving the above object,
실리콘 기판에 트랜지스터를 형성하는 공정과,Forming a transistor on the silicon substrate;
전체구조 상부에 실리콘 산화막과 제1 실리콘 질화막을 차례로 형성하는 공정과,Sequentially forming a silicon oxide film and a first silicon nitride film on the entire structure;
상기 제1 실리콘 질화막 상부에 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the first silicon nitride film;
상기 감광막 패턴을 식각 마스크로 사용하여 하부의 제1 실리콘 질화막과 실리콘 산화막을 식각하여 콘택홀을 형성하는 공정과,Etching the lower first silicon nitride film and the silicon oxide film using the photoresist pattern as an etching mask to form contact holes;
감광막을 제거하는 공정과,Removing the photoresist film;
전체구조 상부에 제2 실리콘 질화막을 소정두께 형성하는 공정과,Forming a predetermined thickness of the second silicon nitride film on the entire structure;
전면식각으로 상기 콘택홀의 양측벽에 제2 실리콘 질화막 스페이서를 형성하는 공정과,Forming a second silicon nitride film spacer on both sidewalls of the contact hole by front etching;
상기 제2 실리콘 질화막을 식각장벽으로 하여 소오스/드레인의 실리콘이 드러나도록 하부 실리콘 산화막을 습식식각하는 공정과,Wet etching the lower silicon oxide layer using the second silicon nitride layer as an etch barrier so that silicon of the source / drain is exposed;
상기 제2 실리콘 질화막을 습식식각에 의해 제거하는 공정과,Removing the second silicon nitride film by wet etching;
전체구조 상부에 금속층을 형성하여 콘택을 형성하는 공정으로 구성되는 것을 특징으로 한다.Forming a contact layer by forming a metal layer on top of the overall structure.
이하, 첨부된 도면을 참조하여 본 발명의 적합한 실시예에 대한 상세한 설명을 하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제1도 내지 제6도는 본 발명의 방법에 따른 반도체 소자의 콘택홀 형성 공정단계를 도시한 단면도이다.1 to 6 are cross-sectional views illustrating a process of forming a contact hole in a semiconductor device according to the method of the present invention.
제1도를 참조하면. N-웰 또는 P-웰이 만들어진 실리콘 기판(1)상에 게이트 산화막(8)과 다결정실리콘층(3) 패턴으로된 게이트전극 및 소오스/드레인영역(도시되지 않음)등의 모스전계효과 트랜지스터를 형성한 후, 전표면에 실리콘 산화막(2)과 실리콘 질화막(5)을 순차적으로 형성한다.Referring to Figure 1. On the silicon substrate 1 on which the N-well or P-well is made, a MOS field effect transistor such as a gate electrode having a pattern of a gate oxide film 8 and a polysilicon layer 3 and a source / drain region (not shown) After the formation, the silicon oxide film 2 and the silicon nitride film 5 are sequentially formed on the entire surface.
제2도를 참조하면, 상기 실리콘 질화막(5) 상부에 콘택홀 형성용 감광막 패턴(4)을 형성하고, 노출된 실리콘 질화막(5)과 실리콘 산화막(2)의 일부를 건식식각에 의해 연속적으로 1차 식각한다. 이때. 상기 실리콘기판(1)의 소오스/드레인이 드러나지 않도록 한다.Referring to FIG. 2, a contact hole forming photoresist pattern 4 is formed on the silicon nitride film 5, and the exposed silicon nitride film 5 and a part of the silicon oxide film 2 are continuously etched by dry etching. Primary etching. At this time. The source / drain of the silicon substrate 1 is not exposed.
제3도를 참조하면, 상기 감광막(4)을 제거한 후 다시 전체구조 상부에 실리콘 질화막(56)을 소정두께 형성한다.Referring to FIG. 3, after removing the photosensitive film 4, a silicon nitride film 5 6 is formed on the entire structure again.
제4도를 참조하면, 감광막 없이 상기 실리콘 질화막(56)을 전면식각하여 상기 콘택홀(10) 측벽에 실리콘 질화막 스페이서(7)가 형성된다.Referring to FIG. 4, a silicon nitride film spacer 7 is formed on the sidewall of the contact hole 10 by etching the entire surface of the silicon nitride film 5 6 without a photosensitive film.
제5도를 참조하면, 상기 실리콘 질화막 스페이서(7)를 식각장벽으로 하여 노출되어있는 실리콘 산화막(2)의 나머지 두께를 습식식각하여 소오스/드레인의 실리콘이 드러나도록 한다.Referring to FIG. 5, the silicon nitride film spacer 7 is used as an etch barrier to wet-etch the remaining thickness of the exposed silicon oxide film 2 to expose the source / drain silicon.
제6도를 참조하면, 상기 실리콘 질화막 스페이서(7)와 실리콘 질화막(5)을 습식식각에 의해 제거한 후, 폴리실리콘 또는 금속(3)을 증착하여 콘택을 형성된다.Referring to FIG. 6, after the silicon nitride film spacer 7 and the silicon nitride film 5 are removed by wet etching, polysilicon or a metal 3 is deposited to form a contact.
이상 상기한 바와 같이, 트랜지스터의 콘택홀 형성시 마지막 단계에서 습식식각을 사용함으로써 종래의 건식식각에 의해 소오스/드레인 접합이 선상을 입게되는 문제점을 해결하여 트랜지스터의 특성을 향상시킬 수 있고, 특히 반도체 디램소자 제조시 적용될 경우 리프레쉬 특성을 좋게 할 수 있다.As described above, by using wet etching in the last step in forming a contact hole of the transistor, the problem of source / drain junctions being linearly caused by conventional dry etching can be solved, and thus the characteristics of the transistor can be improved. When the DRAM device is manufactured, the refresh characteristics can be improved.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960025716A KR100223333B1 (en) | 1996-06-29 | 1996-06-29 | Method for forming a contact of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960025716A KR100223333B1 (en) | 1996-06-29 | 1996-06-29 | Method for forming a contact of semiconductor device |
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| Publication Number | Publication Date |
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| KR980005606A KR980005606A (en) | 1998-03-30 |
| KR100223333B1 true KR100223333B1 (en) | 1999-10-15 |
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| KR1019960025716A KR100223333B1 (en) | 1996-06-29 | 1996-06-29 | Method for forming a contact of semiconductor device |
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