KR100222575B1 - Dummy cell driving circuit - Google Patents

Abstract

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a dummy cell driving circuit of a nonvolatile semiconductor memory device capable of readjusting a threshold voltage of a dummy cell which is a reference of a memory cell when reading data. The present invention relates to a memory cell in which a predetermined cell current flows or is blocked according to a program or erase state, a dummy cell provided as a nonvolatile cell transistor for flowing a predetermined reference current, a data line electrically connected to the cell array; A dummy cell driving circuit of a nonvolatile semiconductor memory device having a sense amplifier circuit for supplying the cell current and the reference current to a dummy data line electrically connected to a drain terminal of the nonvolatile cell transistor, respectively. In response to a first signal, a nonvolatile cell of the dummy cell A first voltage supply unit supplying a first voltage having a predetermined level to a control gate terminal of the transistor; In response to the second and third signals applied from the outside, a second voltage of a predetermined level is supplied to the dummy data line electrically connected to the drain terminal of the nonvolatile cell transistor in response to the second signal. The second voltage supply unit discharges the dummy data line to the ground voltage in response to three signals.

Description

A circuit of driving dummy cell of non volatile semicondutor memory device

The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a dummy cell driving circuit of a nonvolatile semiconductor memory device capable of readjusting a threshold voltage of a dummy cell which is a reference of a memory cell when reading data.

1 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device having a sense amplifier circuit according to the prior art.

The nonvolatile semiconductor memory device illustrated in FIG. 1 includes a cell array 100, a row decoder 110, a column decoder 120, a column gate part 130, a dummy cell 200, and a sense amplifier 300. Consists of. The cell array 100 is an area for storing data and includes a plurality of word lines W / L0 to W / L2, a plurality of bit lines B / L0 to B / L2, and the respective word lines. A plurality of memory cells MC0 to MC40 respectively formed at intersections of the bit lines are formed. The row decoder 110 is for selecting a predetermined word line of the cell array 100, and the column decoder 120 selects a predetermined bit line of the cell array 100 through the column gate part 130. It is to choose. In addition, the sensing amplifier circuit 300 includes a first reference current generator 310, a second reference current generator 320, and a comparator 330. In order to read the state of the selected memory cell MC20 in the cell array 100, a predetermined data line D / L corresponds to a bit line B / L1 connected to the drain terminal of the memory cell MC20. Flows the cell current (ICELL). In addition, a predetermined reference current (herein, the amount of the reference current is selected from the selected memory cell MC20) through the dummy data line DD / L to the cells 200 and MSC100 (hereinafter, referred to as a dummy cell). When the memory cell MC20 is on cell and off cell, half of the current flowing out through the memory cell MC20 flows. Accordingly, the amount of current flowing out through the dummy cell MSC100 corresponding to the selected memory cell MC20 is sensed to determine whether the selected memory cell MC20 is an on cell or an off cell. Will print.

The first reference current generator 310 is for flowing a constant cell current ICELL to the memory cell MC20, and the second reference current generator 320 is connected to the dummy cell MSC100. This is to give a constant reference current (IREF). The comparator 330 detects the amount of current drawn out through the selected memory cell MC20 and the dummy cell MC100 and outputs cell data corresponding thereto. That is, the first reference current generator 310 is a sense amplifier enable signal applied from the outside The cell current ICELL is supplied in response to the cell current, and is composed of a plurality of NMOS transistors MSN50, MSN55, and MSN60 and a plurality of PMOS transistors MSP50 and MSP55. In addition, the second reference current generator 320 may enable the sense amplifier enable signal. The reference current IREF is supplied in response to the reference current IREF, and is composed of a plurality of NMOS transistors MSN0, MSN5, MSN10 and a plurality of PMOS transistors MSP0, MSP5. The second reference current generating unit 320 has a voltage of about +1-+2 volts supplied from the PMOS transistor MSP5 through the NMOS transistor MSN10 which operates as a transfer transistor. L). The voltage of the dummy data line DD / L may change slightly due to the reference current IREF. The change is amplified by the PMOS transistor MSP0 and the NMOS transistor MSN5 through the dummy bias line DBIAS, and thus a large change is shown in the dummy sensing line DS0. This phenomenon is called negative feedbak.

The sense amplifier enable signal When the transistor transitions to a low level, the transistors MSP0 and MSN5 are enabled to maintain a constant voltage on the dummy bias line DBIAS. In general, the amount of the reference current IREF supplied to the dummy cell MSC100 is set to be half of the current flowing out through the memory cell in the “on” state, thereby being connected to one input terminal of the comparator 330. The voltage of the dummy sensing line DS0 is kept constant at all times. In addition, in order to select an arbitrary memory cell in the cell array 100, a power supply voltage is provided through the row decoder 110 to a selected word line W / L1 among word lines in which control gate electrodes of the memory cells are commonly connected. (For example, 5 volts). The column decoder 120 selects one memory cell MC20 by selecting a bit line B / L1 to which the drain terminal of the selected memory cell MC20 is connected through the column gate unit 130. do. In this state, a voltage of about +1-+2 volts supplied from the PMOS transistor MSP55 through the NMOS transistor MSN60 which is a transfer transistor of the first reference current generator 310 is selected from the selected bit line B /. It is applied to the data line D / L corresponding to L1).

When the selected memory cell MC20 is an "on" cell, the first reference current generator 310 has the cell current ICELL, that is, a current exiting through the selected memory cell MC20 is present. Will be created. Thus, the voltage of the sensing line SO connected to one input terminal of the comparator 330 is charged at a voltage relatively lower than the voltage of the dummy sensing line DS0 connected to the other input terminal. On the other hand, when the selected memory cell MC20 is an "off" cell, the current flowing out through the memory cell MC20, that is, the cell current ICELL is insignificant, so that the voltage of the sensing line SO becomes the dummy sensing line. It is charged with a voltage that is relatively high compared to the voltage of (DSO). Therefore, the comparison unit 330 is the voltage of the sensing line (S0) and the dummy sensing line (DS0) generated by the first reference current generator 310 and the second reference current generator 320. Amplify it by taking the difference as input. Here, it should be noted that the reference current IREF of the second reference current generator 320 is a memory for a change in manufacturing process and temperature in order to enable a normal read operation of the cell array 100. The fact is that the "on" and "off" states of the cell should always be half-shaped.

In the conventional NOR flash memory device, the MOS transistor MSC100 used as a dummy cell (or reference cell), which is a path through which the reference current IREF supplied from the second reference current generator 320 exits, Mainly, the same type as the memory cells in the cell array 100 is used. Because the dummy cell MSC100 has the same structure as the memory cell MC in the cell array 100, the dummy cell MSC100 changes in the same manner with respect to the process change of the memory cell MC in a manufacturing process. It is because it may have the same change as the memory cell even when the temperature changes.

However, according to the above-described conventional nonvolatile semiconductor memory device, a dummy cell through which the reference current IREF, which is supplied from the second reference current generating unit 320, exits is typically used for the semiconductor manufacturing process. It has a threshold voltage determined at Vth. Therefore, when the dummy cell is not set to the desired threshold voltage by the semiconductor manufacturing process, there is a problem that the threshold voltage of the dummy cell cannot be readjusted to the desired voltage level. In addition, this problem also causes a problem that incorrect data is read from the on-cell to the off-cell or off-cell to the on-cell during a data read operation.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a dummy cell driving circuit of a nonvolatile semiconductor memory device capable of readjusting the threshold voltage of a dummy cell, which is a reference of a memory cell, when data is read. have.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to the prior art;

2 is a cross-sectional view showing the structure of a NOR type memory cell;

3 is a diagram showing a voltage applied in each operation mode;

4 is a block diagram showing a configuration of a dummy cell driving circuit of a nonvolatile semiconductor memory device according to a preferred embodiment of the present invention;

5 is an operation timing diagram according to the present invention;

* Explanation of symbols on the main parts of the drawings

100: cell array 110: row decoder

120: column decoder 130: column gate portion

200: dummy cell 300: detection amplifier circuit

410: first voltage supply unit 420: second voltage supply unit

According to one aspect of the present invention for achieving the above object, the memory cell is provided with a non-volatile cell transistor for flowing a predetermined reference current or a memory cell in which a predetermined cell current flows or is blocked according to a program or erase state. And a sense amplifier circuit for supplying the cell current and the reference current to the dummy cell, the data line electrically connected to the cell array, and the dummy data line electrically connected to the drain terminal of the nonvolatile cell transistor. 11. A dummy cell driving circuit of a semiconductor memory device, comprising: a first voltage supply unit for supplying a first voltage having a predetermined level to a control gate terminal of a nonvolatile cell transistor of the dummy cell in response to a first signal applied from the outside; In response to the second and third signals applied from the outside, a second voltage of a predetermined level is supplied to the dummy data line electrically connected to the drain terminal of the nonvolatile cell transistor in response to the second signal. And a second voltage supply unit configured to discharge the dummy data line to the ground voltage in response to three signals.

In this embodiment, the first voltage is applied to a voltage in the range of about 0 volts to 3 volts.

In this embodiment, the second voltage is applied at a voltage in the range of about 6 volts to 7 volts.

In this embodiment, the first voltage supply unit is configured of first and second MOS transistors and third to fourth MOS transistors.

In this embodiment, the first and second MOS transistors are characterized in that each consisting of an n-channel conductive MOS transistor.

In this embodiment, the third to fourth MOS transistors are characterized in that each consisting of a p-channel conductive MOS transistor.

In this embodiment, the second voltage supply is characterized by consisting of fifth to seventh MOS transistors and eighth to tenth MOS transistors.

In this embodiment, the fifth to seventh MOS transistors are each composed of an n-channel conductive MOS transistor.

In this embodiment, the eighth to tenth MOS transistors are configured as p-channel conductive MOS transistors, respectively.

By such a circuit, even when the dummy cell is set to an unwanted threshold voltage due to a semiconductor manufacturing process or other causes, the margin is secured during read operation by readjusting the threshold voltage of the dummy cell to a desired level through the dummy cell driving circuit according to the present invention. And malfunction can be prevented.

Hereinafter, reference will be made in detail with reference to FIGS. 2 to 5 according to an embodiment of the present invention.

2 to 5, the same reference numerals are given to the components having the same functions as the components shown in FIG.

2 is a cross-sectional view illustrating a structure of a nonvolatile memory cell that is generally used.

In the NOR-type flash memory cell shown in FIG. 2, an N-type source region 3 and a drain region 4 are formed on a P-type semiconductor substrate 1 with a channel region 2 interposed therebetween. A gate insulating film 5, a floating gate 6, an ONO film 7, and a control gate 8 are sequentially formed on the channel region 2. Here, the gate insulating film 5 is formed of a thin insulating film (or oxide film) of about 100 GPa or less. According to the operation of a typical NOR type flash memory, the flash memory cell is a hot electron injection method in which electrons are injected into the floating gate 6 in the channel region 2 adjacent to the drain region 4. Is programmed by. In general, the injection method grounds the source region 3 and the P-type semiconductor substrate region 1, applies a high high voltage (eg, +12 volts) to the control gate 8, and the drain region. (4) is achieved by applying an appropriate amount of voltage (e.g., 6-7 volts) to generate hot electron injection. A negative charge is sufficiently accumulated in the floating gate 6 by the programming method, and the negative potential of the floating gate 6 increases the threshold voltage of the memory cell during a series of read operations. Do it.

Mainly, a read operation applies 1-2 volts to the drain region 4 of the memory cell, applies a constant voltage or a power supply voltage VCC to the control gate 8, and zeros to the source region 3. By applying a bolt. When the read operation is performed as described above, the memory cell whose threshold voltage is increased by the program operation prevents current from being injected from the drain region 4 to the source region 3, wherein the memory cell is " off " "It is said. Further, according to the operation of the NOR type flash memory, F-N tunneling (Fowler-Nordheim tunneling) to the control gate 8 occurs in the source region 3, the flash memory cell is erased. The general tunneling method is achieved by applying a high high voltage (eg, +12 volts) to the source region 3 and applying 0 volts to the control gate 8 and the semiconductor substrate 1. At this time, the drain region 4 is in a high impedance state (for example, a floating state) in order to maximize the effect of erasing.

As described above, a strong electric field is formed between the control gate 8 and the source region 3 by the erasing method, which causes the FN tunneling to occur to generate negative sound in the floating gate 6. Charges are released into the source region (3). Typically, the FN tunneling occurs when an electric field of 6-7 MV / cm is applied between the gate insulating film 5, and a thin gate insulating film having a thickness of 100 μm or less between the floating gate 6 and the source region 3. 5) is formed so that the FN tunneling is possible. In the erase method, negative charge is discharged from the floating gate 6 to the source region 3 to lower the threshold voltage of the memory cell during a series of read operations. In a typical flash memory cell array configuration, each source region 3 is commonly connected for high integration of the memory. As a result, a plurality of cells are simultaneously erased by the erase method, and an erase unit is determined according to an area to which each source region 3 is connected.

During a series of read operations, a memory cell whose threshold voltage is lowered by the erase operation is applied to the control gate 8 when a constant voltage or a power supply voltage VCC is applied to the control gate 8. A current path is formed in region 3, where the memory cell is said to be "on". However, in the configuration of the NOR-type flash memory, the plurality of memory cells must all have a positive threshold voltage by the erase operation. If there is a memory cell having a negative threshold voltage, a leakage current occurs even in a non-selected state having a ground potential at the control gate 8 of the memory cell. Malfunctions that are read from the "state" to the "on" state may occur. Therefore, self-convergence, which is well known in the art, is used for the method used to solve the problem.

The self-convergence method generally includes a bias (e.g., 0-3 volts) corresponding to a soft proramming due to a tunneling current after performing an erase operation. To apply. An appropriate amount of voltage (e.g., 6-7 volts) is applied to the drain region 4 of the memory cell to generate hot electron injection. As a result, an unselected memory cell having a negative threshold voltage is changed into a memory cell having a positive threshold voltage. Reasons for self convergence through the above method are as follows. When a program mode voltage is applied to a gate terminal of an over erased memory cell, an electric field is generated in the tunneling film (where the tunneling film means a gate insulating film). This is because, when the program proceeds, the electric field generated in the tunneling film is relaxed by electrons accumulated in the floating gate 6, so that a kind of self-limit function is performed in which no further program is performed. This is because tunneling injection from the semiconductor substrate 1 to the floating gate 6 has less nonuniformity than tunneling from the floating gate 6 to the semiconductor substrate 1. 3 is a diagram showing voltages applied to respective terminals of memory cells in each operation mode.

The dummy cell driving circuit of the nonvolatile semiconductor memory device according to the preferred embodiment of the present invention shown in FIG. 4 is implemented to freely adjust the threshold voltage of the dummy cell to a desired voltage level. That is, since a dummy cell serving as a reference of the memory cell when data is read is composed of cells of the same type as the memory cell in the semiconductor manufacturing process, the threshold voltage thereof is determined in the semiconductor manufacturing process. Therefore, when the threshold voltage of the dummy cell is not set to a desired level, there is a problem in that a malfunction occurs during a read operation because there is no circuit for readjusting the conventionally. However, according to the dummy cell driving circuit according to the present invention, even if the dummy cell is not set to the desired threshold voltage in the semiconductor manufacturing process, it is possible to readjust the threshold voltage of the dummy cell through the dummy cell driving circuit according to the present invention. It became. As a result, not only a malfunction occurring during the read operation can be prevented, but also a margin can be secured during the read operation.

4 is a block diagram illustrating a configuration of a dummy cell driving circuit of a nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the dummy cell driving circuit of the nonvolatile semiconductor memory device according to the present invention is to adjust the threshold voltage of the dummy cell 200 as a reference of the memory cell 100 to a desired level. The dummy cell driving circuit 400 includes a first voltage supply part 410 and a second voltage supply part 420. First, the memory cell 100 flows a predetermined cell current ICELL according to a program or erase state. That is, when the memory cell 100 is in a programmed state (off cell state), the cell current ICELL flowing through the memory cell 100 is insignificant, and when the memory cell 100 is in an erased state (on cell state), The cell current ICELL flowing through 100 is present. In addition, the dummy cell 200 is for flowing a reference current IREF, which is a reference for the cell current ICELL flowing through the memory cell 100, and the dummy cell 200 has a floating gate. It consists of the volatile cell transistor MSC100. Here, the first reference current generator 310 and the second reference current generator 310 to flow a predetermined cell current ICELL and a reference current IREF to the memory cell 100 and the dummy cell MSC100, respectively. The data is supplied from the data line D / L and the dummy data line DD / L from the 320. The first voltage supply unit 410 is a first control signal (applied from the outside) In order to supply the voltage VPP1 having a predetermined level to the control gate terminal of the nonvolatile cell transistor MSC100 of the dummy cell 200.

Here, the voltage VPP1 is applied at about 0 to 3 volts in an operation mode for re-adjusting the transistor MSC100 to a desired threshold voltage, and is applied to a power supply voltage VCC or a constant voltage after the operation mode is completed. . The first voltage supply unit 410 includes a plurality of NMOS transistors MSN200 and MSN205 and a plurality of PMOS transistors MSP200 and MSP205. In addition, the second voltage supply unit 420 may receive a second control signal ( ) And the third control signal It operates by inputting. That is, the second control signal ( A voltage VPP2 of a predetermined level is supplied to the dummy data line DD / L electrically connected to the drain terminal of the nonvolatile cell transistor MSC100. And the third control signal. In response, the dummy data line DD / L is discharged to the ground voltage VSS. The voltage VPP2 is applied at about 6-9 volts in an operation mode for re-adjusting the transistor MSC100 to a desired threshold voltage, and is applied at a power supply voltage VCC or a constant voltage after the operation mode is completed. The second voltage supply unit 420 includes a plurality of NMOS transistors MSN210, MSN215, and MSN220 and a plurality of PMOS transistors MSP210, MSP215, and MSP220.

5 is an operation timing diagram according to the present invention. 4 to 5, the operation according to the present invention will be described.

When the dummy cell driving circuit according to the present invention enters an operation mode for re-adjusting the dummy cell to a desired threshold voltage, a sense amplifier enable signal Transitions from a low level to a high level. As a result, the dummy bias line DBIAS connected to the gate terminal of the NMOS transistor MSN10 which is the transfer transistor of the second reference current generator 320 transitions to a low level. Therefore, since the transfer transistor is disabled, the dummy data line DD / L is electrically disconnected from the dummy sensing line DS0. In this state, the low level control signal to the first voltage supply unit 410 (hereinafter referred to as a control gate voltage supply unit). Is applied, and the control signal The first voltage VPP1 is applied to the control gate terminal of the dummy cell MSC100. In this case, the first voltage VPP1 generally maintains the power supply voltage VCC or a constant voltage and then enters an operation mode for re-adjusting the dummy cell MSC100 to a desired threshold voltage. VPP1) is applied at a predetermined voltage level for self-convergence. The predetermined voltage level is supplied at a voltage of about 0 volts to 3 volts.

When the second voltage supply unit 420 (hereinafter referred to as a drain voltage supply unit) enters an operation mode for re-adjusting the dummy cell MSC100 to a desired threshold voltage, a control signal Transitions from the low level to the high level. Accordingly, the second voltage VPP2 is applied to the dummy data line DD / L which is the drain terminal of the dummy cell MSC100 through the PMOS transistor MSP220 which is the transfer transistor of the drain voltage supply unit 420. At this time, the voltage level of the second voltage VPP2 is supplied at a voltage of about 6 volts to 9 volts. As described above, when a voltage required in a weak program mode is applied to the control gate terminal and the drain terminal of the dummy cell MSC100, an electric field is generated in the tunneling film (gate insulating film) of the dummy cell MSC100. As a result, a weak program is performed, and the threshold voltage of the dummy cell MSC100 is increased. In addition, if the program continues, the electric field of the tunneling layer is relaxed by electrons injected into the floating gate of the dummy cell MSC100, and a kind of self-limiting function is acted on the dummy cell MSC100. The increase of the threshold voltage is stopped.

That is, the threshold voltage of the dummy cell MSC100 may be adjusted by the first voltage VPP1 (control gate voltage) applied to the dummy cell MSC100. When the first voltage VPP1 is raised, the threshold voltage of the dummy cell MSC100 converges at a high voltage level. Therefore, the dummy cell MSC100 may be adjusted to a desired specific threshold voltage by the dummy cell driving circuit 400 according to the present invention. Thereafter, when the dummy cell MSC100 is readjusted to a desired threshold voltage, a high level control signal DIS2 is applied to the drain voltage supply unit 420, thereby activating an NMOS transistor MSN220 to thereby activate the dummy cell MSC100. Discharges the drain terminal to the ground voltage VSS.

As described above, in the present invention, a nonvolatile semiconductor memory device capable of electrically programming and erasing operations, particularly a flash memory device, uses a dummy cell, which is a reference of a memory cell, when the data is read in the same structure as that of the memory cell. If desired, the threshold voltage of the dummy cell can be readjusted. As a result, it is possible to prevent margins and malfunctions from occurring during the read operation.

Claims (9)

The memory cell 100 in which a predetermined cell current ICELL flows or is blocked according to a program or erase state, and a dummy cell 200 provided as a nonvolatile cell transistor MSC100 for flowing a predetermined reference current IREF. And a dummy data line DD / L electrically connected to a data line D / L electrically connected to the cell array 100 and a drain terminal of the nonvolatile cell transistor MSC100, respectively. In a dummy cell driving circuit of a nonvolatile semiconductor memory device having an ICELL and a sense amplifier circuit 300 for supplying the reference current IREF, First signal applied from outside In response, a first voltage supply unit 410 for supplying a first voltage (VPP1) of a predetermined level to the control gate terminal of the nonvolatile cell transistor (MSC100) of the dummy cell (200); Second signal applied from outside And third signal Receiving the second signal In response to the second signal VPP2 of a predetermined level to the dummy data line DD / L electrically connected to the drain terminal of the nonvolatile cell transistor MSC100 and supplying the third signal. And a second voltage supply part (420) for discharging the dummy data line (DD / L) to a ground voltage (VSS) in response to the dummy data line. The method of claim 1, And the first voltage VPP1 is applied at a voltage in the range of about 0 volts to 3 volts. The method of claim 1, The second voltage (VPP2) is applied to a voltage in the range of about 6 volts to 7 volts, the dummy cell driving circuit of the nonvolatile semiconductor memory device. The method of claim 1, The first voltage supply unit 410 is composed of first and second MOS transistors MSN200 and MSN205 and third to fourth MOS transistors MSP200 and MSP205. Cell driving circuit. The method of claim 4, wherein The first and second MOS transistors (MSN200, MSN205) are each composed of an n-channel conductive MOS transistor, the dummy cell driving circuit of the nonvolatile semiconductor memory device. The method of claim 4, wherein The third to fourth MOS transistors MSP200 and MSP205 each include a p-channel conductive MOS transistor, and the dummy cell driving circuit of the nonvolatile semiconductor memory device. The method of claim 1, The second voltage supply unit 420 is composed of fifth to seventh MOS transistors MSN210, MSN215, and MSN220 and eighth to tenth MOS transistors MSP210, MSP215, and MSP220. Memory device. The method of claim 7, wherein The fifth to seventh MOS transistors (MSN210, MSN215, MSN220) are each composed of an n-channel conductive MOS transistor, the dummy cell driving circuit of the nonvolatile semiconductor memory device. The method of claim 7, wherein The eighth to tenth MOS transistors (MSP210, MSP215, MSP220) are each formed of a p-channel conductive MOS transistor, the dummy cell driving circuit of the nonvolatile semiconductor memory device.