KR100221073B1 - Synchronous semiconductor memory device - Google Patents

Abstract

[Technical field to which the invention described in the claims belong]

A synchronous semiconductor memory device.

[Technical Challenges to Invent]

Provided are a parallel bit line test circuit and a method of a synchronous semiconductor memory device capable of reducing data skew and test time.

[Summary of the solution of the invention]

A plurality of input / output data sense amplifiers, each having an output terminal connected to a shared data line, and a plurality of memory banks connected to the input / output data sense amplifier and having a plurality of memory cells formed in a matrix of rows and columns on the same chip, and synchronized to an external clock. In the synchronous semiconductor memory device operating in parallel, a parallel bit line test circuit for testing defects of the memory cells through bit lines connected to the memory cells is connected to an output terminal of the plurality of input / output sense amplifiers and is set at a predetermined level in the memory cells. And comparing means for comparing the predetermined data written in the data transfer to the output pad of the synchronous semiconductor memory device.

[Important Uses of the Invention]

It is suitably used for a high speed synchronous semiconductor memory device.

Description

Synchronous Semiconductor Memory Device

1 is a block diagram schematically illustrating banks sharing input / output data sense amplifiers according to the related art.

2 is a schematic block diagram of a synchronous semiconductor memory device constructed in accordance with the present invention.

3 is a detailed circuit diagram for parallel bit line testing according to an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a synchronous semiconductor memory device synchronized with an external clock.

In a synchronous semiconductor memory device (Synchronous DRAM) that performs chip operation in synchronism with the external clock CLK, the external clock CLK cycle becomes small when operating at high frequency, so skew between internal signals is so important that it cannot be ignored. have. Accordingly, the chip structure should be designed to reduce skew between signals, and when the chip capacity is large, a parallel bit line test may be required in a synchronous semiconductor memory device to reduce test time. In addition to parallel bitline testing in a packaged state, parallel bitline testing in a wafer state is also required to improve productivity.

1 is a circuit block diagram of a synchronous semiconductor memory device constructed in accordance with the prior art.

First, as a prerequisite before describing the prior art, in the present specification, a 16-bit operation and a column selection line, for example, a bit line, will be described as limited to a structure in which four data are independently output. It will also be described focusing on reading the data of the two banks 100A and 100B. In the test, the memory cells are located at a predetermined level, for example, by reading data of logical data “0” or “1” and reading the data.

In FIG. 1, the bank 100A is a plurality of memory cell arrays consisting of memory cells arranged in a matrix of rows and columns, and blocks 101A and 101C are input / output data of the banks 100A and 100C. It is a multiplexer composed of transistors necessary to share the sense amplifier 102A. When one bank is activated, 16 data are to be displayed as a whole of the chip, and when the bank 100A is activated, when a detailed DQ allocation (data output DQ is allocated in 4-bit units such as ODD and EVEN) is performed, The data is finally output through the input / output pad 105 via the input / output data sense amplifier 102A, the block 103A composed of the mux, and the read and write driver 104 via 101A. In this case, the data output through the input / output pad 105 is 8 bits of data.

In order to share the data lines DL1 to DL16 by the banks 100A and 100B, the data lines DL1? DL16 are connected up, down, left, and right. As shown in FIG. 1, skew between data exists. That is, referring to the data lines DL1 and DL16, there is a large difference in the length of the path through which data output through the output terminals of the blocks 103A and 103B reaches the read and write drivers 104. It can be seen. As a result, skew between data occurs, which wastes a lot of time in test time and read / write operation.

Accordingly, an object of the present invention is to provide a method of writing and reading a synchronous semiconductor memory device which can reduce skew between data.

Another object of the present invention is to provide a parallel bit line test circuit and a method of a synchronous semiconductor memory device capable of reducing the test time of the bit line.

It is still another object of the present invention to provide a parallel bit line test circuit and a method of a synchronous semiconductor memory device capable of reducing skew between data.

It is still another object of the present invention to provide a parallel bit line test circuit and a method thereof capable of testing in a package state and a wafer state.

According to the technical idea of the present invention for achieving the above object, a plurality of input and output data sense amplifiers each having an output terminal connected to a shared data line, and a plurality of memory cells connected to the input and output data sense amplifier and consisting of a matrix of rows and columns A method of writing and reading a synchronous semiconductor memory device having a plurality of memory banks on a same chip and operating in synchronization with an external clock, the method comprising: connecting the shared data line commonly connected to an output of an input / output sense amplifier between the banks The output pad assignment between the banks is connected to the outputs of the input / output sense amplifiers having different outputs, so that the lengths of the data lines are equally assigned to perform write and read operations for the test under the same loading of the data lines. It features.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

2 is a block diagram constructed in accordance with the present invention.

Referring to the present invention with reference to FIG. 2, the loading of data lines is equalized to reduce skew between data. That is, the data lines DL1 by banks 100A and 100B. Data lines DL1 after the output of the input / output data sense amplifier 102 latches data through block 103 when sharing DL16. DL16 is connected to the output terminal of the corresponding block 103. In other words, the data lines DL1 DL16 is an output terminal DQ4,3,5,2 at the top of the bank 100A between the banks 100A, 100B and an output terminal DQ0,7,1 at the top of the bank 100B. 6, the output terminals DQ6, 1, 7, and 0 at the bottom of the bank 100A are connected to the output terminals DQ2, 5, 3 and 4 at the bottom of the bank 100B.

If it is operated as 16 bits after connecting as in Fig. 2, data output DQ0 In DQ15, the loading of data lines up to the input / output pad 105 is the same, thereby reducing the skew problem between data. According to the above-described method, when a bank is activated, two column selection lines 201 are opened in the case of a pipeline, and four column selection lines 200 are required in the case of 2-bit prefetch. Do. In this data path configuration, in order to perform the parallel bit line test, the output of the input / output data sense amplifier 102A allocated to four DQ units (for example, DQ4, 3, 5, and 2) per array is compared with the comparator 106. ) On the corresponding data line to enable parallel bit line testing in package and wafer conditions. This parallel bitline test will be described in detail in FIG.

3 is a block diagram illustrating a parallel bitline test in accordance with an embodiment of the invention.

Comparator 106-1 8) compares the data of the output of the input / output data sense amplifier 102 and if the data (eg, DQ4,3,5,2) are all "1" or "0", DQ is "0" or Output lines L1 each assigned a value of "1" It is output to the input / output pad 105 through L8). If the data are different in parallel bit line test, DQi (i = 0 7 indicates a high impedance state. And the comparator 106-1 8) is implemented as a NAND gate 107 having four input terminals, but may be implemented as a noah gate or other logic gate.

In the parallel bit line test, the banks 100A and 100B should be activated at the same time when 16 bits are used.

As described above, according to the present invention, it is possible to reduce skew generated between data. The present invention also has the advantage of reducing test time. In addition, the present invention has the advantage that the parallel bit line test can be performed in the wafer state or package state.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (2)

A plurality of input / output data sense amplifiers, each having an output terminal connected to a shared data line, and a plurality of memory banks connected to the input / output data sense amplifier and having a plurality of memory cells formed in a matrix of rows and columns on the same chip, and synchronized to an external clock. A write and read method of a synchronous semiconductor memory device which operates in a sequential manner: the connection of the shared data line commonly connected to the output of the input / output sense amplifier between the banks is an output of the input / output sense amplifier having different output pad assignments between the banks. And writing and reading operations by allocating the same lengths of the data lines. A plurality of input / output data sense amplifiers each having an output terminal connected to a data line, and a plurality of memory banks connected to the input / output data sense amplifier and having a plurality of memory cells having a matrix of rows and columns on the same chip, and synchronized with an external clock. A method for testing a defect of a memory cell through bit lines connected to the memory cells in a synchronous semiconductor memory device, the method comprising: allocating a length of the shared data line connected between the banks to equally load data lines; Testing in the package or wafer state of the semiconductor memory device in the same state.