KR100217909B1 - Method for forming multi metal interconnection layer of semiconductor device - Google Patents
Method for forming multi metal interconnection layer of semiconductor device Download PDFInfo
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- KR100217909B1 KR100217909B1 KR1019960004779A KR19960004779A KR100217909B1 KR 100217909 B1 KR100217909 B1 KR 100217909B1 KR 1019960004779 A KR1019960004779 A KR 1019960004779A KR 19960004779 A KR19960004779 A KR 19960004779A KR 100217909 B1 KR100217909 B1 KR 100217909B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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Abstract
본 발명은 반도체 소자의 다중 금속층 형성 방법에 관한 것으로, 콘택 홀의 단차 및 금속의 층덮힘 불량으로 인해 발생되는 문제점을 해소하기 위하여 금속층간 절연막에 소정 깊이의 트렌치를 형성하고, 상기 트렌치내에 콘택 홀을 형성한다. 그리고 상기 트렌치 및 콘택 홀이 매립되도록 금속을 증착한 후 상기 금속층간 절연막상의 금속을 연마하여 표면을 평탄화시키므로써 후속 공정을 용이하게 실시 할 수 있으며, 고유 저항 값이 낮은 금속을 사용하여 소자의 수율 및 특성이 향상될 수 있도록 한다.The present invention relates to a method for forming a multi-metal layer of a semiconductor device, in order to solve the problems caused by the step difference of the contact hole and the poor layer covering of the metal to form a trench of a predetermined depth in the interlayer insulating film, and to form a contact hole in the trench Form. After the deposition of the metal to fill the trench and the contact hole, the metal on the interlayer insulating film is polished to planarize the surface thereof, thereby facilitating the subsequent process, and the yield of the device using a low resistivity metal. And properties can be improved.
Description
제1(a)도 및 제1(b)도는 종래 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining a method of forming a multiple metal layer of a conventional semiconductor device.
제2(a)도 내지 제2(f)도는 본 발명에 따른 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (f) are cross-sectional views of a device for explaining a method for forming a multi-metal layer of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 및 11 : 실리콘 기판 2 및 12 : 하부 금속층1 and 11: silicon substrate 2 and 12: lower metal layer
3 및 13 : 금속층간 절연막 4 및 15 : 콘택 홀3 and 13: interlayer insulating film 4 and 15: contact hole
6 및 16 : 베리어 금속층 7 및 19 : 상부 금속층6 and 16: Barrier metal layer 7 and 19: Upper metal layer
8 : 보이드 14 : 트렌치8: void 14: trench
17 : 금속17: metal
본 발명은 반도체 소자의 다중 금속층 형성 방법에 관한 것으로, 특히 금속의 층덮힘 특성 및 표면의 평탄도를 향상시킬 수 있도록 한 반도체 소자의 다중 금속층 형성 방법에 관한 것이다.The present invention relates to a method of forming a multi-metal layer of a semiconductor device, and more particularly to a method of forming a multi-metal layer of a semiconductor device to improve the layer covering characteristics and the surface flatness of the metal.
일반적으로 반도체 소자의 제조 공정에서 금속층은 이중 또는 다중 구조로 형성되며, 금속층간의 접속은 금속층간 절연막에 형성되는 콘택 홀(Contact Hole)을 통해 이루어진다. 그런데 반도체 소자가 고집적화됨에 따라 콘택 홀의 크기가 감소되기 때문에 콘택 홀내에 금속을 매립시키는 공정이 어려워지며, 또한 콘택 홀 에서의 평탄도 저하가 문제점으로 발생된다. 그러면 종래 반도체 소자의 다중 금속층 형성 방법을 제1(a) 도 및 제1(b)도를 통해 설명하면 다음과 같다.In general, in the process of manufacturing a semiconductor device, the metal layer is formed in a double or multiple structure, and the connection between the metal layers is made through a contact hole formed in the interlayer insulating film. However, as the semiconductor device is highly integrated, the size of the contact hole is reduced, so that the process of embedding the metal in the contact hole becomes difficult, and the flatness in the contact hole is reduced. A method of forming a multi-metal layer of a conventional semiconductor device will now be described with reference to FIGS. 1 (a) and 1 (b).
종래 반도체 소자의 다중 금속층 형성 방법은 제1(a)도에 도시된 바와 같이 하부 금속층(2)이 형성된 실리콘 기판(1)상에 금속층간 절연막(3)을 형성한 후 하부 금속층(2)의 소정 부분이 노출되도록 금속층간 절연막(3)을 패터닝하여 콘택 홀(4)을 형성한다. 그리고 제1(b)도에 도시된 바와 같이 전체 상부면에 베리어 금속층(6)을 형성한 후 콘택 홀(4)이 매립되도록 전체 상부면에 알루미늄(Al)과 같은 금속(Metal)을 증착하여 상부 금속층(7)을 형성한다. 이후 상기와 같은 공정을 순차적으로 반복 실시하여 다중 구조의 금속층을 형성하는데, 이와 같은 방법을 이용하는 경우 상부 금속층(7)을 형성하기 위한 금속 증착 공정시 콘택 홀(4)내의 단차로 인하여 금속의 층덮힘이 불량해진다. 그러므로 콘택 홀(4)내에 보이드(Void; 8)가 발생되며, 상부 금속층(7) 표면의 평탄도가 저하되어 후속 공정의 진행이 어려워진다. 반면에 금속의 층덮힘을 향상시키기 위하여 콘택 홀(4)내에 텅스텐(W)을 이용하여 플러그(Plug)를 형성하는 방법을 제조 원가를 상승시킬 뿐만 아니라, 텅스텐(W)의 높은 고유 저항 값으로 인해 소자의 특성이 저하되는 단점이 있다.In the conventional method of forming a multi-metal layer of a semiconductor device, as shown in FIG. 1 (a), after forming the interlayer insulating film 3 on the silicon substrate 1 on which the lower metal layer 2 is formed, the lower metal layer 2 is formed. The interlayer insulating film 3 is patterned to expose a predetermined portion to form the contact hole 4. As shown in FIG. 1 (b), the barrier metal layer 6 is formed on the entire upper surface, and then metal such as aluminum is deposited on the entire upper surface so that the contact holes 4 are filled. The upper metal layer 7 is formed. Subsequently, the above process is repeatedly performed to form a multi-layered metal layer. In this case, the metal layer is formed due to a step in the contact hole 4 during the metal deposition process for forming the upper metal layer 7. Coverage is poor. Therefore, voids 8 are generated in the contact hole 4, and the flatness of the surface of the upper metal layer 7 is lowered, making it difficult to proceed with subsequent processes. On the other hand, the method of forming a plug using tungsten (W) in the contact hole (4) to improve the layer covering of the metal not only increases the manufacturing cost but also increases the high resistivity value of the tungsten (W). Due to the disadvantage that the characteristics of the device is deteriorated.
따라서, 본 발명은 금속층간 절연막에 소정 깊이의 트렌치를 형성하고, 트렌치내에 콘택 홀을 형성하여 트렌치 및 콘택 홀이 매립되도록 금속을 증착한 후 금속층간 절연박상의 금속을 연마하여 표면을 평탄화시키므로써 상기한 단점을 해소 할 수 있는 반도체 소자의 다중 금속층 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a trench having a predetermined depth in the interlayer insulating film, forms a contact hole in the trench, deposits a metal to fill the trench and the contact hole, and then polishes the metal in the interlayer metal interlayer to planarize the surface. It is an object of the present invention to provide a method for forming a multi-metal layer of a semiconductor device that can solve the above disadvantages.
상술한 목적을 달성하기 위한 본 발명은 하부 금속층이 형성된 실리콘 기판상에 금속층간 절연막을 형성한 후 상기 금속층간 절연막에 소정 깊이의 트렌치를 형성하는 제1 단계와, 상기 트렌치내에 상기 하부 금속층의 소정 부분이 노출되도록 콘택 홀을 형성하는 제2 단계와, 상기 트렌치 및 상기 콘택홀을 포함한 전체 상부면에 베리어 금속층을 형성한 후 상기 트렌치 및 콘택 홀이 매립되도록 전체 상부면에 금속을 증착하는 제3 단계와, 상기 금속을 리플로우시킨 후 상기 금속층간 절연막의 표면이 노출되는 시점까지 상기 금속을 연마하여 표면을 평탄화시키는 제4 단계와, 전체 상부면에 상부 금속층을 형성하는 제5 단계와, 상기 제1 내지 제5 단계를 순차적으로 반복 실시하는 제6 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a first step of forming an intermetallic insulating film on the silicon substrate on which the lower metal layer is formed, and then forming a trench of a predetermined depth in the interlayer insulating film, and the predetermined of the lower metal layer in the trench A second step of forming a contact hole to expose a portion; and forming a barrier metal layer on an entire upper surface including the trench and the contact hole, and then depositing metal on the entire upper surface so that the trench and the contact hole are embedded. A fourth step of flattening the surface by polishing the metal until the surface of the interlayer insulating film is exposed after reflowing the metal; and a fifth step of forming an upper metal layer on the entire upper surface thereof; It is characterized by consisting of a sixth step of sequentially repeating the first to fifth steps.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2(a)도 내지 제2(f)도는 본 발명에 따른 반도체 소자의 다중 금속층 형성 방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (f) are cross-sectional views of a device for explaining a method of forming a multi-metal layer of a semiconductor device according to the present invention.
제2(a)도는 하부 금속층(12)이 형성된 실리콘 기판(11) 상부에 금속층간 절연막(13)을 형성한 후 금속층간 절연막(13)에 소정 깊이의 트렌치(14)를 형성한 상태의 단면도이고, 제2(b)도는 콘택 바스크(Mask)를 이용한 사진 및 식각 공정으로 트렌치(14)내에 하부 금속층(12)의 소정 부분이 노출되도록 콘택 홀(15)을 형성한 상태의 단면도이다.2 (a) is a cross-sectional view of a state in which a trench 14 having a predetermined depth is formed in the interlayer insulating layer 13 after the interlayer insulating layer 13 is formed on the silicon substrate 11 on which the lower metal layer 12 is formed. 2B is a cross-sectional view of a state in which the contact hole 15 is formed to expose a predetermined portion of the lower metal layer 12 in the trench 14 by a photolithography and an etching process using a contact mask.
제2(c)도는 전체 상부면에 70 내지 130Å 두께의 티타늄(Ti) 및 250 내지 350Å 두껭 l 티타늄 나이트라이드(TiN)를 순차적으로 증착하여 베리어 금속층(16)을 형성한 상태의 단면도이고, 제2(d)도는 실온(Room temperature)에서 트렌치(14) 및 콘택 홀(15)이 매립되도록 전체 상부면에 알루미늄(Al)과 같은 금속(17)을 증착한 후 금속(17)을 리플로우(Reflow)시킨 상태의 단면도이다. 이때, 트렌치(14)에 의해 콘택 홀(15)의 단차가 감소되어 금속(17)의 층덮힘이 양호해지며, 리플로우 공정은 400 내지 500℃의 온도에서 150 내지 200초동안 실시된다.FIG. 2 (c) is a cross-sectional view of a barrier metal layer 16 formed by sequentially depositing titanium (Ti) and 250 to 350 mm thick titanium nitride (TiN) having a thickness of 70 to 130 mm 3 on the entire upper surface thereof. 2 (d) is deposited metal 17, such as aluminum (Al) on the entire upper surface such that the trench 14 and the contact hole 15 is embedded at room temperature, and then the metal 17 is reflowed ( It is a cross-sectional view of the reflowed state. At this time, the step 14 of the contact hole 15 is reduced by the trench 14, so that the layer covering of the metal 17 is good, and the reflow process is performed for 150 to 200 seconds at a temperature of 400 to 500 ° C.
제2(e)도는 화학적 기계 연마(Chemical Mechanical Polishing) 방법으로 금속층간 절연막(13)의 표면이 노출되는 시점까지 금속(17)을 연마하여 표면을 평탄화시킨 상태의 단면도로서, 금속(17) 및 베리어 금속층(16)은 동일한 연마비를 가지며, 이때 연마비는 0.1 내지 0.3㎛/분 정도가 되도록 한다.FIG. 2 (e) is a cross-sectional view of the metal 17 being polished to a point where the surface of the interlayer insulating film 13 is exposed by chemical mechanical polishing, thereby flattening the surface thereof. The barrier metal layer 16 has the same polishing ratio, and the polishing ratio is about 0.1 to 0.3 탆 / minute.
제2(f)도는 전체 상부면에 알루미늄(Al)과 같은 금속을 증착하여 상부 금속층(19)을 형성한 상태의 단면도로서, 이후 상기 제2(a) 도 내지 제2(e) 도에 설명된 공정을 순차적으로 반복 실시하여 다중 구조의 금속층을 형성한다.FIG. 2 (f) is a cross-sectional view of the upper metal layer 19 formed by depositing a metal such as aluminum (Al) on the entire upper surface thereof, and is described later with reference to FIGS. 2 (a) to 2 (e). Process is repeated sequentially to form a metal layer of multiple structures.
상술한 바와 같이 본 발명에 의하면 금속층간 절연막에 소정 길이의 트렌치를 형성하고, 상기 트렌치내에 콘택 홀을 형성한다. 그리고 상기 트렌치 및 콘텍홀이 매립되도록 금속을 증착한 후 상기 금속층간 절연막상의 금속을 연마하여 표면을 평탄화시킨다. 이에 의해 후속 공정을 용이하게 실시할 수 있으며, 고유 저항값이 낮은 금속을 사용하여 소자의 수율 및 특성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, trenches having a predetermined length are formed in the interlayer insulating film, and contact holes are formed in the trenches. After depositing the metal to fill the trench and the contact hole, the metal on the interlayer insulating film is polished to planarize the surface. Thereby, the subsequent process can be easily performed, and there is an excellent effect that the yield and characteristics of the device can be improved by using a metal having a low specific resistance value.
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| KR20010009868A (en) * | 1999-07-14 | 2001-02-05 | 김영환 | Method for forming hole of semiconductor device |
| KR100520075B1 (en) | 2003-06-23 | 2005-10-11 | 삼성전자주식회사 | Ac/dc adapter and notebook computer for using the same |
-
1996
- 1996-02-27 KR KR1019960004779A patent/KR100217909B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970063671A (en) | 1997-09-12 |
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